| Message ID | 20251210-headers-update-v6-18-v2-1-3f726742a4c8@ideasonboard.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series |
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| Related | show |
On Wed, Dec 10, 2025 at 09:19:12AM +0100, Jacopo Mondi wrote: > Update drm_fourcc.h to Linux kernel version v6.18. > > As the upstream drm_fourcc.h version doesn't include definitions > for RAW Bayer formats, some of the symbols we defined > downstream now conflict with new symbols defined in mainline. > > In particular: > > and > Something seem to be missing here :-) > In order not to break the library ABI, maintain the downstream symbols > definitions as they are even if they conflict. > > Signed-off-by: Jacopo Mondi <jacopo.mondi@ideasonboard.com> > Acked-by: Barnabás Pőcze <barnabas.pocze@ideasonboard.com> > --- > include/linux/drm_fourcc.h | 191 ++++++++++++++++++++++++++++++++++++++++++--- > 1 file changed, 180 insertions(+), 11 deletions(-) > > diff --git a/include/linux/drm_fourcc.h b/include/linux/drm_fourcc.h > index db6798776663086c12d321d2ed708edc7ec77f71..e428c33346bae8a8747f6834c434dc0a03eef867 100644 > --- a/include/linux/drm_fourcc.h > +++ b/include/linux/drm_fourcc.h > @@ -222,7 +222,7 @@ extern "C" { > #define DRM_FORMAT_ABGR16161616 fourcc_code('A', 'B', '4', '8') /* [63:0] A:B:G:R 16:16:16:16 little endian */ > > /* > - * Floating point 64bpp RGB > + * Half-Floating point - 16b/component > * IEEE 754-2008 binary16 half-precision float > * [15:0] sign:exponent:mantissa 1:5:10 > */ > @@ -232,6 +232,20 @@ extern "C" { > #define DRM_FORMAT_ARGB16161616F fourcc_code('A', 'R', '4', 'H') /* [63:0] A:R:G:B 16:16:16:16 little endian */ > #define DRM_FORMAT_ABGR16161616F fourcc_code('A', 'B', '4', 'H') /* [63:0] A:B:G:R 16:16:16:16 little endian */ > > +#define DRM_FORMAT_R16F fourcc_code('R', ' ', ' ', 'H') /* [15:0] R 16 little endian */ > +#define DRM_FORMAT_GR1616F fourcc_code('G', 'R', ' ', 'H') /* [31:0] G:R 16:16 little endian */ > +#define DRM_FORMAT_BGR161616F fourcc_code('B', 'G', 'R', 'H') /* [47:0] B:G:R 16:16:16 little endian */ > + > +/* > + * Floating point - 32b/component > + * IEEE 754-2008 binary32 float > + * [31:0] sign:exponent:mantissa 1:8:23 > + */ > +#define DRM_FORMAT_R32F fourcc_code('R', ' ', ' ', 'F') /* [31:0] R 32 little endian */ > +#define DRM_FORMAT_GR3232F fourcc_code('G', 'R', ' ', 'F') /* [63:0] R:G 32:32 little endian */ > +#define DRM_FORMAT_BGR323232F fourcc_code('B', 'G', 'R', 'F') /* [95:0] R:G:B 32:32:32 little endian */ > +#define DRM_FORMAT_ABGR32323232F fourcc_code('A', 'B', '8', 'F') /* [127:0] R:G:B:A 32:32:32:32 little endian */ > + > /* > * RGBA format with 10-bit components packed in 64-bit per pixel, with 6 bits > * of unused padding per component: > @@ -381,6 +395,42 @@ extern "C" { > */ > #define DRM_FORMAT_Q401 fourcc_code('Q', '4', '0', '1') > > +/* > + * 3 plane YCbCr LSB aligned > + * In order to use these formats in a similar fashion to MSB aligned ones > + * implementation can multiply the values by 2^6=64. For that reason the padding > + * must only contain zeros. > + * index 0 = Y plane, [15:0] z:Y [6:10] little endian > + * index 1 = Cr plane, [15:0] z:Cr [6:10] little endian > + * index 2 = Cb plane, [15:0] z:Cb [6:10] little endian > + */ > +#define DRM_FORMAT_S010 fourcc_code('S', '0', '1', '0') /* 2x2 subsampled Cb (1) and Cr (2) planes 10 bits per channel */ > +#define DRM_FORMAT_S210 fourcc_code('S', '2', '1', '0') /* 2x1 subsampled Cb (1) and Cr (2) planes 10 bits per channel */ > +#define DRM_FORMAT_S410 fourcc_code('S', '4', '1', '0') /* non-subsampled Cb (1) and Cr (2) planes 10 bits per channel */ > + > +/* > + * 3 plane YCbCr LSB aligned > + * In order to use these formats in a similar fashion to MSB aligned ones > + * implementation can multiply the values by 2^4=16. For that reason the padding > + * must only contain zeros. > + * index 0 = Y plane, [15:0] z:Y [4:12] little endian > + * index 1 = Cr plane, [15:0] z:Cr [4:12] little endian > + * index 2 = Cb plane, [15:0] z:Cb [4:12] little endian > + */ > +#define DRM_FORMAT_S012 fourcc_code('S', '0', '1', '2') /* 2x2 subsampled Cb (1) and Cr (2) planes 12 bits per channel */ > +#define DRM_FORMAT_S212 fourcc_code('S', '2', '1', '2') /* 2x1 subsampled Cb (1) and Cr (2) planes 12 bits per channel */ > +#define DRM_FORMAT_S412 fourcc_code('S', '4', '1', '2') /* non-subsampled Cb (1) and Cr (2) planes 12 bits per channel */ > + > +/* > + * 3 plane YCbCr > + * index 0 = Y plane, [15:0] Y little endian > + * index 1 = Cr plane, [15:0] Cr little endian > + * index 2 = Cb plane, [15:0] Cb little endian > + */ > +#define DRM_FORMAT_S016 fourcc_code('S', '0', '1', '6') /* 2x2 subsampled Cb (1) and Cr (2) planes 16 bits per channel */ > +#define DRM_FORMAT_S216 fourcc_code('S', '2', '1', '6') /* 2x1 subsampled Cb (1) and Cr (2) planes 16 bits per channel */ > +#define DRM_FORMAT_S416 fourcc_code('S', '4', '1', '6') /* non-subsampled Cb (1) and Cr (2) planes 16 bits per channel */ > + > /* > * 3 plane YCbCr > * index 0: Y plane, [7:0] Y > @@ -489,6 +539,8 @@ extern "C" { > #define DRM_FORMAT_MOD_VENDOR_ARM 0x08 > #define DRM_FORMAT_MOD_VENDOR_ALLWINNER 0x09 > #define DRM_FORMAT_MOD_VENDOR_AMLOGIC 0x0a > +#define DRM_FORMAT_MOD_VENDOR_MTK 0x0b > +#define DRM_FORMAT_MOD_VENDOR_APPLE 0x0c > #define DRM_FORMAT_MOD_VENDOR_MIPI 0x0b > #define DRM_FORMAT_MOD_VENDOR_RPI 0x0c > > @@ -772,6 +824,31 @@ extern "C" { > */ > #define I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC fourcc_mod_code(INTEL, 15) > > +/* > + * Intel Color Control Surfaces (CCS) for graphics ver. 20 unified compression > + * on integrated graphics > + * > + * The main surface is Tile 4 and at plane index 0. For semi-planar formats > + * like NV12, the Y and UV planes are Tile 4 and are located at plane indices > + * 0 and 1, respectively. The CCS for all planes are stored outside of the > + * GEM object in a reserved memory area dedicated for the storage of the > + * CCS data for all compressible GEM objects. > + */ > +#define I915_FORMAT_MOD_4_TILED_LNL_CCS fourcc_mod_code(INTEL, 16) > + > +/* > + * Intel Color Control Surfaces (CCS) for graphics ver. 20 unified compression > + * on discrete graphics > + * > + * The main surface is Tile 4 and at plane index 0. For semi-planar formats > + * like NV12, the Y and UV planes are Tile 4 and are located at plane indices > + * 0 and 1, respectively. The CCS for all planes are stored outside of the > + * GEM object in a reserved memory area dedicated for the storage of the > + * CCS data for all compressible GEM objects. The GEM object must be stored in > + * contiguous memory with a size aligned to 64KB > + */ > +#define I915_FORMAT_MOD_4_TILED_BMG_CCS fourcc_mod_code(INTEL, 17) > + > /* > * IPU3 Bayer packing layout > * > @@ -780,7 +857,7 @@ extern "C" { > * the 6 most significant bits in the last byte unused. The format is little > * endian. > */ > -#define IPU3_FORMAT_MOD_PACKED fourcc_mod_code(INTEL, 13) > +#define IPU3_FORMAT_MOD_PACKED fourcc_mod_code(INTEL, 18) > > /* > * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks > @@ -978,14 +1055,20 @@ extern "C" { > * 2 = Gob Height 8, Turing+ Page Kind mapping > * 3 = Reserved for future use. > * > - * 22:22 s Sector layout. On Tegra GPUs prior to Xavier, there is a further > - * bit remapping step that occurs at an even lower level than the > - * page kind and block linear swizzles. This causes the layout of > - * surfaces mapped in those SOC's GPUs to be incompatible with the > - * equivalent mapping on other GPUs in the same system. > - * > - * 0 = Tegra K1 - Tegra Parker/TX2 Layout. > - * 1 = Desktop GPU and Tegra Xavier+ Layout > + * 22:22 s Sector layout. There is a further bit remapping step that occurs > + * 26:27 at an even lower level than the page kind and block linear > + * swizzles. This causes the bit arrangement of surfaces in memory > + * to differ subtly, and prevents direct sharing of surfaces between > + * GPUs with different layouts. > + * > + * 0 = Tegra K1 - Tegra Parker/TX2 Layout > + * 1 = Pre-GB20x, GB20x 32+ bpp, GB10, Tegra Xavier-Orin Layout > + * 2 = GB20x(Blackwell 2)+ 8 bpp surface layout > + * 3 = GB20x(Blackwell 2)+ 16 bpp surface layout > + * 4 = Reserved for future use. > + * 5 = Reserved for future use. > + * 6 = Reserved for future use. > + * 7 = Reserved for future use. > * > * 25:23 c Lossless Framebuffer Compression type. > * > @@ -1000,7 +1083,7 @@ extern "C" { > * 6 = Reserved for future use > * 7 = Reserved for future use > * > - * 55:25 - Reserved for future use. Must be zero. > + * 55:28 - Reserved for future use. Must be zero. > */ > #define DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(c, s, g, k, h) \ > fourcc_mod_code(NVIDIA, (0x10 | \ > @@ -1008,6 +1091,7 @@ extern "C" { > (((k) & 0xff) << 12) | \ > (((g) & 0x3) << 20) | \ > (((s) & 0x1) << 22) | \ > + (((s) & 0x6) << 25) | \ > (((c) & 0x7) << 23))) > > /* To grandfather in prior block linear format modifiers to the above layout, > @@ -1508,6 +1592,90 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier) > */ > #define AMLOGIC_FBC_OPTION_MEM_SAVING (1ULL << 0) > > +/* MediaTek modifiers > + * Bits Parameter Notes > + * ----- ------------------------ --------------------------------------------- > + * 7: 0 TILE LAYOUT Values are MTK_FMT_MOD_TILE_* > + * 15: 8 COMPRESSION Values are MTK_FMT_MOD_COMPRESS_* > + * 23:16 10 BIT LAYOUT Values are MTK_FMT_MOD_10BIT_LAYOUT_* > + * > + */ > + > +#define DRM_FORMAT_MOD_MTK(__flags) fourcc_mod_code(MTK, __flags) > + > +/* > + * MediaTek Tiled Modifier > + * The lowest 8 bits of the modifier is used to specify the tiling > + * layout. Only the 16L_32S tiling is used for now, but we define an > + * "untiled" version and leave room for future expansion. > + */ > +#define MTK_FMT_MOD_TILE_MASK 0xf > +#define MTK_FMT_MOD_TILE_NONE 0x0 > +#define MTK_FMT_MOD_TILE_16L32S 0x1 > + > +/* > + * Bits 8-15 specify compression options > + */ > +#define MTK_FMT_MOD_COMPRESS_MASK (0xf << 8) > +#define MTK_FMT_MOD_COMPRESS_NONE (0x0 << 8) > +#define MTK_FMT_MOD_COMPRESS_V1 (0x1 << 8) > + > +/* > + * Bits 16-23 specify how the bits of 10 bit formats are > + * stored out in memory > + */ > +#define MTK_FMT_MOD_10BIT_LAYOUT_MASK (0xf << 16) > +#define MTK_FMT_MOD_10BIT_LAYOUT_PACKED (0x0 << 16) > +#define MTK_FMT_MOD_10BIT_LAYOUT_LSBTILED (0x1 << 16) > +#define MTK_FMT_MOD_10BIT_LAYOUT_LSBRASTER (0x2 << 16) > + > +/* alias for the most common tiling format */ > +#define DRM_FORMAT_MOD_MTK_16L_32S_TILE DRM_FORMAT_MOD_MTK(MTK_FMT_MOD_TILE_16L32S) > + > +/* > + * Apple GPU-tiled layouts. > + * > + * Apple GPUs support nonlinear tilings with optional lossless compression. > + * > + * GPU-tiled images are divided into 16KiB tiles: > + * > + * Bytes per pixel Tile size > + * --------------- --------- > + * 1 128x128 > + * 2 128x64 > + * 4 64x64 > + * 8 64x32 > + * 16 32x32 > + * > + * Tiles are raster-order. Pixels within a tile are interleaved (Morton order). > + * > + * Compressed images pad the body to 128-bytes and are immediately followed by a > + * metadata section. The metadata section rounds the image dimensions to > + * powers-of-two and contains 8 bytes for each 16x16 compression subtile. > + * Subtiles are interleaved (Morton order). > + * > + * All images are 128-byte aligned. > + * > + * These layouts fundamentally do not have meaningful strides. No matter how we > + * specify strides for these layouts, userspace unaware of Apple image layouts > + * will be unable to use correctly the specified stride for any purpose. > + * Userspace aware of the image layouts do not use strides. The most "correct" > + * convention would be setting the image stride to 0. Unfortunately, some > + * software assumes the stride is at least (width * bytes per pixel). We > + * therefore require that stride equals (width * bytes per pixel). Since the > + * stride is arbitrary here, we pick the simplest convention. > + * > + * Although containing two sections, compressed image layouts are treated in > + * software as a single plane. This is modelled after AFBC, a similar > + * scheme. Attempting to separate the sections to be "explicit" in DRM would > + * only generate more confusion, as software does not treat the image this way. > + * > + * For detailed information on the hardware image layouts, see > + * https://docs.mesa3d.org/drivers/asahi.html#image-layouts > + */ > +#define DRM_FORMAT_MOD_APPLE_GPU_TILED fourcc_mod_code(APPLE, 1) > +#define DRM_FORMAT_MOD_APPLE_GPU_TILED_COMPRESSED fourcc_mod_code(APPLE, 2) > + > /* > * AMD modifiers > * > @@ -1571,6 +1739,7 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier) > * 64K_D_2D on GFX12 is identical to 64K_D on GFX11. > */ > #define AMD_FMT_MOD_TILE_GFX9_64K_D 10 > +#define AMD_FMT_MOD_TILE_GFX9_4K_D_X 22 > #define AMD_FMT_MOD_TILE_GFX9_64K_S_X 25 > #define AMD_FMT_MOD_TILE_GFX9_64K_D_X 26 > #define AMD_FMT_MOD_TILE_GFX9_64K_R_X 27
On Thu, Dec 11, 2025 at 10:20:23AM +0900, Laurent Pinchart wrote: > On Wed, Dec 10, 2025 at 09:19:12AM +0100, Jacopo Mondi wrote: > > Update drm_fourcc.h to Linux kernel version v6.18. > > > > As the upstream drm_fourcc.h version doesn't include definitions > > for RAW Bayer formats, some of the symbols we defined > > downstream now conflict with new symbols defined in mainline. > > > > In particular: > > > > and > > > > Something seem to be missing here :-) > Ups, dunno what happened. I'll resend > > In order not to break the library ABI, maintain the downstream symbols > > definitions as they are even if they conflict. > > > > Signed-off-by: Jacopo Mondi <jacopo.mondi@ideasonboard.com> > > Acked-by: Barnabás Pőcze <barnabas.pocze@ideasonboard.com> > > --- > > include/linux/drm_fourcc.h | 191 ++++++++++++++++++++++++++++++++++++++++++--- > > 1 file changed, 180 insertions(+), 11 deletions(-) > > > > diff --git a/include/linux/drm_fourcc.h b/include/linux/drm_fourcc.h > > index db6798776663086c12d321d2ed708edc7ec77f71..e428c33346bae8a8747f6834c434dc0a03eef867 100644 > > --- a/include/linux/drm_fourcc.h > > +++ b/include/linux/drm_fourcc.h > > @@ -222,7 +222,7 @@ extern "C" { > > #define DRM_FORMAT_ABGR16161616 fourcc_code('A', 'B', '4', '8') /* [63:0] A:B:G:R 16:16:16:16 little endian */ > > > > /* > > - * Floating point 64bpp RGB > > + * Half-Floating point - 16b/component > > * IEEE 754-2008 binary16 half-precision float > > * [15:0] sign:exponent:mantissa 1:5:10 > > */ > > @@ -232,6 +232,20 @@ extern "C" { > > #define DRM_FORMAT_ARGB16161616F fourcc_code('A', 'R', '4', 'H') /* [63:0] A:R:G:B 16:16:16:16 little endian */ > > #define DRM_FORMAT_ABGR16161616F fourcc_code('A', 'B', '4', 'H') /* [63:0] A:B:G:R 16:16:16:16 little endian */ > > > > +#define DRM_FORMAT_R16F fourcc_code('R', ' ', ' ', 'H') /* [15:0] R 16 little endian */ > > +#define DRM_FORMAT_GR1616F fourcc_code('G', 'R', ' ', 'H') /* [31:0] G:R 16:16 little endian */ > > +#define DRM_FORMAT_BGR161616F fourcc_code('B', 'G', 'R', 'H') /* [47:0] B:G:R 16:16:16 little endian */ > > + > > +/* > > + * Floating point - 32b/component > > + * IEEE 754-2008 binary32 float > > + * [31:0] sign:exponent:mantissa 1:8:23 > > + */ > > +#define DRM_FORMAT_R32F fourcc_code('R', ' ', ' ', 'F') /* [31:0] R 32 little endian */ > > +#define DRM_FORMAT_GR3232F fourcc_code('G', 'R', ' ', 'F') /* [63:0] R:G 32:32 little endian */ > > +#define DRM_FORMAT_BGR323232F fourcc_code('B', 'G', 'R', 'F') /* [95:0] R:G:B 32:32:32 little endian */ > > +#define DRM_FORMAT_ABGR32323232F fourcc_code('A', 'B', '8', 'F') /* [127:0] R:G:B:A 32:32:32:32 little endian */ > > + > > /* > > * RGBA format with 10-bit components packed in 64-bit per pixel, with 6 bits > > * of unused padding per component: > > @@ -381,6 +395,42 @@ extern "C" { > > */ > > #define DRM_FORMAT_Q401 fourcc_code('Q', '4', '0', '1') > > > > +/* > > + * 3 plane YCbCr LSB aligned > > + * In order to use these formats in a similar fashion to MSB aligned ones > > + * implementation can multiply the values by 2^6=64. For that reason the padding > > + * must only contain zeros. > > + * index 0 = Y plane, [15:0] z:Y [6:10] little endian > > + * index 1 = Cr plane, [15:0] z:Cr [6:10] little endian > > + * index 2 = Cb plane, [15:0] z:Cb [6:10] little endian > > + */ > > +#define DRM_FORMAT_S010 fourcc_code('S', '0', '1', '0') /* 2x2 subsampled Cb (1) and Cr (2) planes 10 bits per channel */ > > +#define DRM_FORMAT_S210 fourcc_code('S', '2', '1', '0') /* 2x1 subsampled Cb (1) and Cr (2) planes 10 bits per channel */ > > +#define DRM_FORMAT_S410 fourcc_code('S', '4', '1', '0') /* non-subsampled Cb (1) and Cr (2) planes 10 bits per channel */ > > + > > +/* > > + * 3 plane YCbCr LSB aligned > > + * In order to use these formats in a similar fashion to MSB aligned ones > > + * implementation can multiply the values by 2^4=16. For that reason the padding > > + * must only contain zeros. > > + * index 0 = Y plane, [15:0] z:Y [4:12] little endian > > + * index 1 = Cr plane, [15:0] z:Cr [4:12] little endian > > + * index 2 = Cb plane, [15:0] z:Cb [4:12] little endian > > + */ > > +#define DRM_FORMAT_S012 fourcc_code('S', '0', '1', '2') /* 2x2 subsampled Cb (1) and Cr (2) planes 12 bits per channel */ > > +#define DRM_FORMAT_S212 fourcc_code('S', '2', '1', '2') /* 2x1 subsampled Cb (1) and Cr (2) planes 12 bits per channel */ > > +#define DRM_FORMAT_S412 fourcc_code('S', '4', '1', '2') /* non-subsampled Cb (1) and Cr (2) planes 12 bits per channel */ > > + > > +/* > > + * 3 plane YCbCr > > + * index 0 = Y plane, [15:0] Y little endian > > + * index 1 = Cr plane, [15:0] Cr little endian > > + * index 2 = Cb plane, [15:0] Cb little endian > > + */ > > +#define DRM_FORMAT_S016 fourcc_code('S', '0', '1', '6') /* 2x2 subsampled Cb (1) and Cr (2) planes 16 bits per channel */ > > +#define DRM_FORMAT_S216 fourcc_code('S', '2', '1', '6') /* 2x1 subsampled Cb (1) and Cr (2) planes 16 bits per channel */ > > +#define DRM_FORMAT_S416 fourcc_code('S', '4', '1', '6') /* non-subsampled Cb (1) and Cr (2) planes 16 bits per channel */ > > + > > /* > > * 3 plane YCbCr > > * index 0: Y plane, [7:0] Y > > @@ -489,6 +539,8 @@ extern "C" { > > #define DRM_FORMAT_MOD_VENDOR_ARM 0x08 > > #define DRM_FORMAT_MOD_VENDOR_ALLWINNER 0x09 > > #define DRM_FORMAT_MOD_VENDOR_AMLOGIC 0x0a > > +#define DRM_FORMAT_MOD_VENDOR_MTK 0x0b > > +#define DRM_FORMAT_MOD_VENDOR_APPLE 0x0c > > #define DRM_FORMAT_MOD_VENDOR_MIPI 0x0b > > #define DRM_FORMAT_MOD_VENDOR_RPI 0x0c > > > > @@ -772,6 +824,31 @@ extern "C" { > > */ > > #define I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC fourcc_mod_code(INTEL, 15) > > > > +/* > > + * Intel Color Control Surfaces (CCS) for graphics ver. 20 unified compression > > + * on integrated graphics > > + * > > + * The main surface is Tile 4 and at plane index 0. For semi-planar formats > > + * like NV12, the Y and UV planes are Tile 4 and are located at plane indices > > + * 0 and 1, respectively. The CCS for all planes are stored outside of the > > + * GEM object in a reserved memory area dedicated for the storage of the > > + * CCS data for all compressible GEM objects. > > + */ > > +#define I915_FORMAT_MOD_4_TILED_LNL_CCS fourcc_mod_code(INTEL, 16) > > + > > +/* > > + * Intel Color Control Surfaces (CCS) for graphics ver. 20 unified compression > > + * on discrete graphics > > + * > > + * The main surface is Tile 4 and at plane index 0. For semi-planar formats > > + * like NV12, the Y and UV planes are Tile 4 and are located at plane indices > > + * 0 and 1, respectively. The CCS for all planes are stored outside of the > > + * GEM object in a reserved memory area dedicated for the storage of the > > + * CCS data for all compressible GEM objects. The GEM object must be stored in > > + * contiguous memory with a size aligned to 64KB > > + */ > > +#define I915_FORMAT_MOD_4_TILED_BMG_CCS fourcc_mod_code(INTEL, 17) > > + > > /* > > * IPU3 Bayer packing layout > > * > > @@ -780,7 +857,7 @@ extern "C" { > > * the 6 most significant bits in the last byte unused. The format is little > > * endian. > > */ > > -#define IPU3_FORMAT_MOD_PACKED fourcc_mod_code(INTEL, 13) > > +#define IPU3_FORMAT_MOD_PACKED fourcc_mod_code(INTEL, 18) > > > > /* > > * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks > > @@ -978,14 +1055,20 @@ extern "C" { > > * 2 = Gob Height 8, Turing+ Page Kind mapping > > * 3 = Reserved for future use. > > * > > - * 22:22 s Sector layout. On Tegra GPUs prior to Xavier, there is a further > > - * bit remapping step that occurs at an even lower level than the > > - * page kind and block linear swizzles. This causes the layout of > > - * surfaces mapped in those SOC's GPUs to be incompatible with the > > - * equivalent mapping on other GPUs in the same system. > > - * > > - * 0 = Tegra K1 - Tegra Parker/TX2 Layout. > > - * 1 = Desktop GPU and Tegra Xavier+ Layout > > + * 22:22 s Sector layout. There is a further bit remapping step that occurs > > + * 26:27 at an even lower level than the page kind and block linear > > + * swizzles. This causes the bit arrangement of surfaces in memory > > + * to differ subtly, and prevents direct sharing of surfaces between > > + * GPUs with different layouts. > > + * > > + * 0 = Tegra K1 - Tegra Parker/TX2 Layout > > + * 1 = Pre-GB20x, GB20x 32+ bpp, GB10, Tegra Xavier-Orin Layout > > + * 2 = GB20x(Blackwell 2)+ 8 bpp surface layout > > + * 3 = GB20x(Blackwell 2)+ 16 bpp surface layout > > + * 4 = Reserved for future use. > > + * 5 = Reserved for future use. > > + * 6 = Reserved for future use. > > + * 7 = Reserved for future use. > > * > > * 25:23 c Lossless Framebuffer Compression type. > > * > > @@ -1000,7 +1083,7 @@ extern "C" { > > * 6 = Reserved for future use > > * 7 = Reserved for future use > > * > > - * 55:25 - Reserved for future use. Must be zero. > > + * 55:28 - Reserved for future use. Must be zero. > > */ > > #define DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(c, s, g, k, h) \ > > fourcc_mod_code(NVIDIA, (0x10 | \ > > @@ -1008,6 +1091,7 @@ extern "C" { > > (((k) & 0xff) << 12) | \ > > (((g) & 0x3) << 20) | \ > > (((s) & 0x1) << 22) | \ > > + (((s) & 0x6) << 25) | \ > > (((c) & 0x7) << 23))) > > > > /* To grandfather in prior block linear format modifiers to the above layout, > > @@ -1508,6 +1592,90 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier) > > */ > > #define AMLOGIC_FBC_OPTION_MEM_SAVING (1ULL << 0) > > > > +/* MediaTek modifiers > > + * Bits Parameter Notes > > + * ----- ------------------------ --------------------------------------------- > > + * 7: 0 TILE LAYOUT Values are MTK_FMT_MOD_TILE_* > > + * 15: 8 COMPRESSION Values are MTK_FMT_MOD_COMPRESS_* > > + * 23:16 10 BIT LAYOUT Values are MTK_FMT_MOD_10BIT_LAYOUT_* > > + * > > + */ > > + > > +#define DRM_FORMAT_MOD_MTK(__flags) fourcc_mod_code(MTK, __flags) > > + > > +/* > > + * MediaTek Tiled Modifier > > + * The lowest 8 bits of the modifier is used to specify the tiling > > + * layout. Only the 16L_32S tiling is used for now, but we define an > > + * "untiled" version and leave room for future expansion. > > + */ > > +#define MTK_FMT_MOD_TILE_MASK 0xf > > +#define MTK_FMT_MOD_TILE_NONE 0x0 > > +#define MTK_FMT_MOD_TILE_16L32S 0x1 > > + > > +/* > > + * Bits 8-15 specify compression options > > + */ > > +#define MTK_FMT_MOD_COMPRESS_MASK (0xf << 8) > > +#define MTK_FMT_MOD_COMPRESS_NONE (0x0 << 8) > > +#define MTK_FMT_MOD_COMPRESS_V1 (0x1 << 8) > > + > > +/* > > + * Bits 16-23 specify how the bits of 10 bit formats are > > + * stored out in memory > > + */ > > +#define MTK_FMT_MOD_10BIT_LAYOUT_MASK (0xf << 16) > > +#define MTK_FMT_MOD_10BIT_LAYOUT_PACKED (0x0 << 16) > > +#define MTK_FMT_MOD_10BIT_LAYOUT_LSBTILED (0x1 << 16) > > +#define MTK_FMT_MOD_10BIT_LAYOUT_LSBRASTER (0x2 << 16) > > + > > +/* alias for the most common tiling format */ > > +#define DRM_FORMAT_MOD_MTK_16L_32S_TILE DRM_FORMAT_MOD_MTK(MTK_FMT_MOD_TILE_16L32S) > > + > > +/* > > + * Apple GPU-tiled layouts. > > + * > > + * Apple GPUs support nonlinear tilings with optional lossless compression. > > + * > > + * GPU-tiled images are divided into 16KiB tiles: > > + * > > + * Bytes per pixel Tile size > > + * --------------- --------- > > + * 1 128x128 > > + * 2 128x64 > > + * 4 64x64 > > + * 8 64x32 > > + * 16 32x32 > > + * > > + * Tiles are raster-order. Pixels within a tile are interleaved (Morton order). > > + * > > + * Compressed images pad the body to 128-bytes and are immediately followed by a > > + * metadata section. The metadata section rounds the image dimensions to > > + * powers-of-two and contains 8 bytes for each 16x16 compression subtile. > > + * Subtiles are interleaved (Morton order). > > + * > > + * All images are 128-byte aligned. > > + * > > + * These layouts fundamentally do not have meaningful strides. No matter how we > > + * specify strides for these layouts, userspace unaware of Apple image layouts > > + * will be unable to use correctly the specified stride for any purpose. > > + * Userspace aware of the image layouts do not use strides. The most "correct" > > + * convention would be setting the image stride to 0. Unfortunately, some > > + * software assumes the stride is at least (width * bytes per pixel). We > > + * therefore require that stride equals (width * bytes per pixel). Since the > > + * stride is arbitrary here, we pick the simplest convention. > > + * > > + * Although containing two sections, compressed image layouts are treated in > > + * software as a single plane. This is modelled after AFBC, a similar > > + * scheme. Attempting to separate the sections to be "explicit" in DRM would > > + * only generate more confusion, as software does not treat the image this way. > > + * > > + * For detailed information on the hardware image layouts, see > > + * https://docs.mesa3d.org/drivers/asahi.html#image-layouts > > + */ > > +#define DRM_FORMAT_MOD_APPLE_GPU_TILED fourcc_mod_code(APPLE, 1) > > +#define DRM_FORMAT_MOD_APPLE_GPU_TILED_COMPRESSED fourcc_mod_code(APPLE, 2) > > + > > /* > > * AMD modifiers > > * > > @@ -1571,6 +1739,7 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier) > > * 64K_D_2D on GFX12 is identical to 64K_D on GFX11. > > */ > > #define AMD_FMT_MOD_TILE_GFX9_64K_D 10 > > +#define AMD_FMT_MOD_TILE_GFX9_4K_D_X 22 > > #define AMD_FMT_MOD_TILE_GFX9_64K_S_X 25 > > #define AMD_FMT_MOD_TILE_GFX9_64K_D_X 26 > > #define AMD_FMT_MOD_TILE_GFX9_64K_R_X 27 > > -- > Regards, > > Laurent Pinchart
On Thu, Dec 11, 2025 at 09:43:31AM +0100, Jacopo Mondi wrote: > On Thu, Dec 11, 2025 at 10:20:23AM +0900, Laurent Pinchart wrote: > > On Wed, Dec 10, 2025 at 09:19:12AM +0100, Jacopo Mondi wrote: > > > Update drm_fourcc.h to Linux kernel version v6.18. > > > > > > As the upstream drm_fourcc.h version doesn't include definitions > > > for RAW Bayer formats, some of the symbols we defined > > > downstream now conflict with new symbols defined in mainline. > > > > > > In particular: > > > > > > and > > > > > > > Something seem to be missing here :-) > > > > Ups, dunno what happened. I'll resend > Uh I know what happened. I pasted the defines there defines start with # they're treated like comments by git and discarded I've fixed this and .. see below > > > In order not to break the library ABI, maintain the downstream symbols > > > definitions as they are even if they conflict. > > > > > > Signed-off-by: Jacopo Mondi <jacopo.mondi@ideasonboard.com> > > > Acked-by: Barnabás Pőcze <barnabas.pocze@ideasonboard.com> > > > --- > > > include/linux/drm_fourcc.h | 191 ++++++++++++++++++++++++++++++++++++++++++--- > > > 1 file changed, 180 insertions(+), 11 deletions(-) > > > > > > diff --git a/include/linux/drm_fourcc.h b/include/linux/drm_fourcc.h > > > index db6798776663086c12d321d2ed708edc7ec77f71..e428c33346bae8a8747f6834c434dc0a03eef867 100644 > > > --- a/include/linux/drm_fourcc.h > > > +++ b/include/linux/drm_fourcc.h > > > @@ -222,7 +222,7 @@ extern "C" { > > > #define DRM_FORMAT_ABGR16161616 fourcc_code('A', 'B', '4', '8') /* [63:0] A:B:G:R 16:16:16:16 little endian */ > > > > > > /* > > > - * Floating point 64bpp RGB > > > + * Half-Floating point - 16b/component > > > * IEEE 754-2008 binary16 half-precision float > > > * [15:0] sign:exponent:mantissa 1:5:10 > > > */ > > > @@ -232,6 +232,20 @@ extern "C" { > > > #define DRM_FORMAT_ARGB16161616F fourcc_code('A', 'R', '4', 'H') /* [63:0] A:R:G:B 16:16:16:16 little endian */ > > > #define DRM_FORMAT_ABGR16161616F fourcc_code('A', 'B', '4', 'H') /* [63:0] A:B:G:R 16:16:16:16 little endian */ > > > > > > +#define DRM_FORMAT_R16F fourcc_code('R', ' ', ' ', 'H') /* [15:0] R 16 little endian */ > > > +#define DRM_FORMAT_GR1616F fourcc_code('G', 'R', ' ', 'H') /* [31:0] G:R 16:16 little endian */ > > > +#define DRM_FORMAT_BGR161616F fourcc_code('B', 'G', 'R', 'H') /* [47:0] B:G:R 16:16:16 little endian */ > > > + > > > +/* > > > + * Floating point - 32b/component > > > + * IEEE 754-2008 binary32 float > > > + * [31:0] sign:exponent:mantissa 1:8:23 > > > + */ > > > +#define DRM_FORMAT_R32F fourcc_code('R', ' ', ' ', 'F') /* [31:0] R 32 little endian */ > > > +#define DRM_FORMAT_GR3232F fourcc_code('G', 'R', ' ', 'F') /* [63:0] R:G 32:32 little endian */ > > > +#define DRM_FORMAT_BGR323232F fourcc_code('B', 'G', 'R', 'F') /* [95:0] R:G:B 32:32:32 little endian */ > > > +#define DRM_FORMAT_ABGR32323232F fourcc_code('A', 'B', '8', 'F') /* [127:0] R:G:B:A 32:32:32:32 little endian */ > > > + > > > /* > > > * RGBA format with 10-bit components packed in 64-bit per pixel, with 6 bits > > > * of unused padding per component: > > > @@ -381,6 +395,42 @@ extern "C" { > > > */ > > > #define DRM_FORMAT_Q401 fourcc_code('Q', '4', '0', '1') > > > > > > +/* > > > + * 3 plane YCbCr LSB aligned > > > + * In order to use these formats in a similar fashion to MSB aligned ones > > > + * implementation can multiply the values by 2^6=64. For that reason the padding > > > + * must only contain zeros. > > > + * index 0 = Y plane, [15:0] z:Y [6:10] little endian > > > + * index 1 = Cr plane, [15:0] z:Cr [6:10] little endian > > > + * index 2 = Cb plane, [15:0] z:Cb [6:10] little endian > > > + */ > > > +#define DRM_FORMAT_S010 fourcc_code('S', '0', '1', '0') /* 2x2 subsampled Cb (1) and Cr (2) planes 10 bits per channel */ > > > +#define DRM_FORMAT_S210 fourcc_code('S', '2', '1', '0') /* 2x1 subsampled Cb (1) and Cr (2) planes 10 bits per channel */ > > > +#define DRM_FORMAT_S410 fourcc_code('S', '4', '1', '0') /* non-subsampled Cb (1) and Cr (2) planes 10 bits per channel */ > > > + > > > +/* > > > + * 3 plane YCbCr LSB aligned > > > + * In order to use these formats in a similar fashion to MSB aligned ones > > > + * implementation can multiply the values by 2^4=16. For that reason the padding > > > + * must only contain zeros. > > > + * index 0 = Y plane, [15:0] z:Y [4:12] little endian > > > + * index 1 = Cr plane, [15:0] z:Cr [4:12] little endian > > > + * index 2 = Cb plane, [15:0] z:Cb [4:12] little endian > > > + */ > > > +#define DRM_FORMAT_S012 fourcc_code('S', '0', '1', '2') /* 2x2 subsampled Cb (1) and Cr (2) planes 12 bits per channel */ > > > +#define DRM_FORMAT_S212 fourcc_code('S', '2', '1', '2') /* 2x1 subsampled Cb (1) and Cr (2) planes 12 bits per channel */ > > > +#define DRM_FORMAT_S412 fourcc_code('S', '4', '1', '2') /* non-subsampled Cb (1) and Cr (2) planes 12 bits per channel */ > > > + > > > +/* > > > + * 3 plane YCbCr > > > + * index 0 = Y plane, [15:0] Y little endian > > > + * index 1 = Cr plane, [15:0] Cr little endian > > > + * index 2 = Cb plane, [15:0] Cb little endian > > > + */ > > > +#define DRM_FORMAT_S016 fourcc_code('S', '0', '1', '6') /* 2x2 subsampled Cb (1) and Cr (2) planes 16 bits per channel */ > > > +#define DRM_FORMAT_S216 fourcc_code('S', '2', '1', '6') /* 2x1 subsampled Cb (1) and Cr (2) planes 16 bits per channel */ > > > +#define DRM_FORMAT_S416 fourcc_code('S', '4', '1', '6') /* non-subsampled Cb (1) and Cr (2) planes 16 bits per channel */ > > > + > > > /* > > > * 3 plane YCbCr > > > * index 0: Y plane, [7:0] Y > > > @@ -489,6 +539,8 @@ extern "C" { > > > #define DRM_FORMAT_MOD_VENDOR_ARM 0x08 > > > #define DRM_FORMAT_MOD_VENDOR_ALLWINNER 0x09 > > > #define DRM_FORMAT_MOD_VENDOR_AMLOGIC 0x0a > > > +#define DRM_FORMAT_MOD_VENDOR_MTK 0x0b > > > +#define DRM_FORMAT_MOD_VENDOR_APPLE 0x0c > > > #define DRM_FORMAT_MOD_VENDOR_MIPI 0x0b > > > #define DRM_FORMAT_MOD_VENDOR_RPI 0x0c > > > > > > @@ -772,6 +824,31 @@ extern "C" { > > > */ > > > #define I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC fourcc_mod_code(INTEL, 15) > > > > > > +/* > > > + * Intel Color Control Surfaces (CCS) for graphics ver. 20 unified compression > > > + * on integrated graphics > > > + * > > > + * The main surface is Tile 4 and at plane index 0. For semi-planar formats > > > + * like NV12, the Y and UV planes are Tile 4 and are located at plane indices > > > + * 0 and 1, respectively. The CCS for all planes are stored outside of the > > > + * GEM object in a reserved memory area dedicated for the storage of the > > > + * CCS data for all compressible GEM objects. > > > + */ > > > +#define I915_FORMAT_MOD_4_TILED_LNL_CCS fourcc_mod_code(INTEL, 16) > > > + > > > +/* > > > + * Intel Color Control Surfaces (CCS) for graphics ver. 20 unified compression > > > + * on discrete graphics > > > + * > > > + * The main surface is Tile 4 and at plane index 0. For semi-planar formats > > > + * like NV12, the Y and UV planes are Tile 4 and are located at plane indices > > > + * 0 and 1, respectively. The CCS for all planes are stored outside of the > > > + * GEM object in a reserved memory area dedicated for the storage of the > > > + * CCS data for all compressible GEM objects. The GEM object must be stored in > > > + * contiguous memory with a size aligned to 64KB > > > + */ > > > +#define I915_FORMAT_MOD_4_TILED_BMG_CCS fourcc_mod_code(INTEL, 17) > > > + > > > /* > > > * IPU3 Bayer packing layout > > > * > > > @@ -780,7 +857,7 @@ extern "C" { > > > * the 6 most significant bits in the last byte unused. The format is little > > > * endian. > > > */ > > > -#define IPU3_FORMAT_MOD_PACKED fourcc_mod_code(INTEL, 13) > > > +#define IPU3_FORMAT_MOD_PACKED fourcc_mod_code(INTEL, 18) > > > I've restored this as well, following the same logic as per the other conflicting symbols. I should have done it in this version already. Thanks j > > > /* > > > * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks > > > @@ -978,14 +1055,20 @@ extern "C" { > > > * 2 = Gob Height 8, Turing+ Page Kind mapping > > > * 3 = Reserved for future use. > > > * > > > - * 22:22 s Sector layout. On Tegra GPUs prior to Xavier, there is a further > > > - * bit remapping step that occurs at an even lower level than the > > > - * page kind and block linear swizzles. This causes the layout of > > > - * surfaces mapped in those SOC's GPUs to be incompatible with the > > > - * equivalent mapping on other GPUs in the same system. > > > - * > > > - * 0 = Tegra K1 - Tegra Parker/TX2 Layout. > > > - * 1 = Desktop GPU and Tegra Xavier+ Layout > > > + * 22:22 s Sector layout. There is a further bit remapping step that occurs > > > + * 26:27 at an even lower level than the page kind and block linear > > > + * swizzles. This causes the bit arrangement of surfaces in memory > > > + * to differ subtly, and prevents direct sharing of surfaces between > > > + * GPUs with different layouts. > > > + * > > > + * 0 = Tegra K1 - Tegra Parker/TX2 Layout > > > + * 1 = Pre-GB20x, GB20x 32+ bpp, GB10, Tegra Xavier-Orin Layout > > > + * 2 = GB20x(Blackwell 2)+ 8 bpp surface layout > > > + * 3 = GB20x(Blackwell 2)+ 16 bpp surface layout > > > + * 4 = Reserved for future use. > > > + * 5 = Reserved for future use. > > > + * 6 = Reserved for future use. > > > + * 7 = Reserved for future use. > > > * > > > * 25:23 c Lossless Framebuffer Compression type. > > > * > > > @@ -1000,7 +1083,7 @@ extern "C" { > > > * 6 = Reserved for future use > > > * 7 = Reserved for future use > > > * > > > - * 55:25 - Reserved for future use. Must be zero. > > > + * 55:28 - Reserved for future use. Must be zero. > > > */ > > > #define DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(c, s, g, k, h) \ > > > fourcc_mod_code(NVIDIA, (0x10 | \ > > > @@ -1008,6 +1091,7 @@ extern "C" { > > > (((k) & 0xff) << 12) | \ > > > (((g) & 0x3) << 20) | \ > > > (((s) & 0x1) << 22) | \ > > > + (((s) & 0x6) << 25) | \ > > > (((c) & 0x7) << 23))) > > > > > > /* To grandfather in prior block linear format modifiers to the above layout, > > > @@ -1508,6 +1592,90 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier) > > > */ > > > #define AMLOGIC_FBC_OPTION_MEM_SAVING (1ULL << 0) > > > > > > +/* MediaTek modifiers > > > + * Bits Parameter Notes > > > + * ----- ------------------------ --------------------------------------------- > > > + * 7: 0 TILE LAYOUT Values are MTK_FMT_MOD_TILE_* > > > + * 15: 8 COMPRESSION Values are MTK_FMT_MOD_COMPRESS_* > > > + * 23:16 10 BIT LAYOUT Values are MTK_FMT_MOD_10BIT_LAYOUT_* > > > + * > > > + */ > > > + > > > +#define DRM_FORMAT_MOD_MTK(__flags) fourcc_mod_code(MTK, __flags) > > > + > > > +/* > > > + * MediaTek Tiled Modifier > > > + * The lowest 8 bits of the modifier is used to specify the tiling > > > + * layout. Only the 16L_32S tiling is used for now, but we define an > > > + * "untiled" version and leave room for future expansion. > > > + */ > > > +#define MTK_FMT_MOD_TILE_MASK 0xf > > > +#define MTK_FMT_MOD_TILE_NONE 0x0 > > > +#define MTK_FMT_MOD_TILE_16L32S 0x1 > > > + > > > +/* > > > + * Bits 8-15 specify compression options > > > + */ > > > +#define MTK_FMT_MOD_COMPRESS_MASK (0xf << 8) > > > +#define MTK_FMT_MOD_COMPRESS_NONE (0x0 << 8) > > > +#define MTK_FMT_MOD_COMPRESS_V1 (0x1 << 8) > > > + > > > +/* > > > + * Bits 16-23 specify how the bits of 10 bit formats are > > > + * stored out in memory > > > + */ > > > +#define MTK_FMT_MOD_10BIT_LAYOUT_MASK (0xf << 16) > > > +#define MTK_FMT_MOD_10BIT_LAYOUT_PACKED (0x0 << 16) > > > +#define MTK_FMT_MOD_10BIT_LAYOUT_LSBTILED (0x1 << 16) > > > +#define MTK_FMT_MOD_10BIT_LAYOUT_LSBRASTER (0x2 << 16) > > > + > > > +/* alias for the most common tiling format */ > > > +#define DRM_FORMAT_MOD_MTK_16L_32S_TILE DRM_FORMAT_MOD_MTK(MTK_FMT_MOD_TILE_16L32S) > > > + > > > +/* > > > + * Apple GPU-tiled layouts. > > > + * > > > + * Apple GPUs support nonlinear tilings with optional lossless compression. > > > + * > > > + * GPU-tiled images are divided into 16KiB tiles: > > > + * > > > + * Bytes per pixel Tile size > > > + * --------------- --------- > > > + * 1 128x128 > > > + * 2 128x64 > > > + * 4 64x64 > > > + * 8 64x32 > > > + * 16 32x32 > > > + * > > > + * Tiles are raster-order. Pixels within a tile are interleaved (Morton order). > > > + * > > > + * Compressed images pad the body to 128-bytes and are immediately followed by a > > > + * metadata section. The metadata section rounds the image dimensions to > > > + * powers-of-two and contains 8 bytes for each 16x16 compression subtile. > > > + * Subtiles are interleaved (Morton order). > > > + * > > > + * All images are 128-byte aligned. > > > + * > > > + * These layouts fundamentally do not have meaningful strides. No matter how we > > > + * specify strides for these layouts, userspace unaware of Apple image layouts > > > + * will be unable to use correctly the specified stride for any purpose. > > > + * Userspace aware of the image layouts do not use strides. The most "correct" > > > + * convention would be setting the image stride to 0. Unfortunately, some > > > + * software assumes the stride is at least (width * bytes per pixel). We > > > + * therefore require that stride equals (width * bytes per pixel). Since the > > > + * stride is arbitrary here, we pick the simplest convention. > > > + * > > > + * Although containing two sections, compressed image layouts are treated in > > > + * software as a single plane. This is modelled after AFBC, a similar > > > + * scheme. Attempting to separate the sections to be "explicit" in DRM would > > > + * only generate more confusion, as software does not treat the image this way. > > > + * > > > + * For detailed information on the hardware image layouts, see > > > + * https://docs.mesa3d.org/drivers/asahi.html#image-layouts > > > + */ > > > +#define DRM_FORMAT_MOD_APPLE_GPU_TILED fourcc_mod_code(APPLE, 1) > > > +#define DRM_FORMAT_MOD_APPLE_GPU_TILED_COMPRESSED fourcc_mod_code(APPLE, 2) > > > + > > > /* > > > * AMD modifiers > > > * > > > @@ -1571,6 +1739,7 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier) > > > * 64K_D_2D on GFX12 is identical to 64K_D on GFX11. > > > */ > > > #define AMD_FMT_MOD_TILE_GFX9_64K_D 10 > > > +#define AMD_FMT_MOD_TILE_GFX9_4K_D_X 22 > > > #define AMD_FMT_MOD_TILE_GFX9_64K_S_X 25 > > > #define AMD_FMT_MOD_TILE_GFX9_64K_D_X 26 > > > #define AMD_FMT_MOD_TILE_GFX9_64K_R_X 27 > > > > -- > > Regards, > > > > Laurent Pinchart
diff --git a/include/linux/drm_fourcc.h b/include/linux/drm_fourcc.h index db6798776663086c12d321d2ed708edc7ec77f71..e428c33346bae8a8747f6834c434dc0a03eef867 100644 --- a/include/linux/drm_fourcc.h +++ b/include/linux/drm_fourcc.h @@ -222,7 +222,7 @@ extern "C" { #define DRM_FORMAT_ABGR16161616 fourcc_code('A', 'B', '4', '8') /* [63:0] A:B:G:R 16:16:16:16 little endian */ /* - * Floating point 64bpp RGB + * Half-Floating point - 16b/component * IEEE 754-2008 binary16 half-precision float * [15:0] sign:exponent:mantissa 1:5:10 */ @@ -232,6 +232,20 @@ extern "C" { #define DRM_FORMAT_ARGB16161616F fourcc_code('A', 'R', '4', 'H') /* [63:0] A:R:G:B 16:16:16:16 little endian */ #define DRM_FORMAT_ABGR16161616F fourcc_code('A', 'B', '4', 'H') /* [63:0] A:B:G:R 16:16:16:16 little endian */ +#define DRM_FORMAT_R16F fourcc_code('R', ' ', ' ', 'H') /* [15:0] R 16 little endian */ +#define DRM_FORMAT_GR1616F fourcc_code('G', 'R', ' ', 'H') /* [31:0] G:R 16:16 little endian */ +#define DRM_FORMAT_BGR161616F fourcc_code('B', 'G', 'R', 'H') /* [47:0] B:G:R 16:16:16 little endian */ + +/* + * Floating point - 32b/component + * IEEE 754-2008 binary32 float + * [31:0] sign:exponent:mantissa 1:8:23 + */ +#define DRM_FORMAT_R32F fourcc_code('R', ' ', ' ', 'F') /* [31:0] R 32 little endian */ +#define DRM_FORMAT_GR3232F fourcc_code('G', 'R', ' ', 'F') /* [63:0] R:G 32:32 little endian */ +#define DRM_FORMAT_BGR323232F fourcc_code('B', 'G', 'R', 'F') /* [95:0] R:G:B 32:32:32 little endian */ +#define DRM_FORMAT_ABGR32323232F fourcc_code('A', 'B', '8', 'F') /* [127:0] R:G:B:A 32:32:32:32 little endian */ + /* * RGBA format with 10-bit components packed in 64-bit per pixel, with 6 bits * of unused padding per component: @@ -381,6 +395,42 @@ extern "C" { */ #define DRM_FORMAT_Q401 fourcc_code('Q', '4', '0', '1') +/* + * 3 plane YCbCr LSB aligned + * In order to use these formats in a similar fashion to MSB aligned ones + * implementation can multiply the values by 2^6=64. For that reason the padding + * must only contain zeros. + * index 0 = Y plane, [15:0] z:Y [6:10] little endian + * index 1 = Cr plane, [15:0] z:Cr [6:10] little endian + * index 2 = Cb plane, [15:0] z:Cb [6:10] little endian + */ +#define DRM_FORMAT_S010 fourcc_code('S', '0', '1', '0') /* 2x2 subsampled Cb (1) and Cr (2) planes 10 bits per channel */ +#define DRM_FORMAT_S210 fourcc_code('S', '2', '1', '0') /* 2x1 subsampled Cb (1) and Cr (2) planes 10 bits per channel */ +#define DRM_FORMAT_S410 fourcc_code('S', '4', '1', '0') /* non-subsampled Cb (1) and Cr (2) planes 10 bits per channel */ + +/* + * 3 plane YCbCr LSB aligned + * In order to use these formats in a similar fashion to MSB aligned ones + * implementation can multiply the values by 2^4=16. For that reason the padding + * must only contain zeros. + * index 0 = Y plane, [15:0] z:Y [4:12] little endian + * index 1 = Cr plane, [15:0] z:Cr [4:12] little endian + * index 2 = Cb plane, [15:0] z:Cb [4:12] little endian + */ +#define DRM_FORMAT_S012 fourcc_code('S', '0', '1', '2') /* 2x2 subsampled Cb (1) and Cr (2) planes 12 bits per channel */ +#define DRM_FORMAT_S212 fourcc_code('S', '2', '1', '2') /* 2x1 subsampled Cb (1) and Cr (2) planes 12 bits per channel */ +#define DRM_FORMAT_S412 fourcc_code('S', '4', '1', '2') /* non-subsampled Cb (1) and Cr (2) planes 12 bits per channel */ + +/* + * 3 plane YCbCr + * index 0 = Y plane, [15:0] Y little endian + * index 1 = Cr plane, [15:0] Cr little endian + * index 2 = Cb plane, [15:0] Cb little endian + */ +#define DRM_FORMAT_S016 fourcc_code('S', '0', '1', '6') /* 2x2 subsampled Cb (1) and Cr (2) planes 16 bits per channel */ +#define DRM_FORMAT_S216 fourcc_code('S', '2', '1', '6') /* 2x1 subsampled Cb (1) and Cr (2) planes 16 bits per channel */ +#define DRM_FORMAT_S416 fourcc_code('S', '4', '1', '6') /* non-subsampled Cb (1) and Cr (2) planes 16 bits per channel */ + /* * 3 plane YCbCr * index 0: Y plane, [7:0] Y @@ -489,6 +539,8 @@ extern "C" { #define DRM_FORMAT_MOD_VENDOR_ARM 0x08 #define DRM_FORMAT_MOD_VENDOR_ALLWINNER 0x09 #define DRM_FORMAT_MOD_VENDOR_AMLOGIC 0x0a +#define DRM_FORMAT_MOD_VENDOR_MTK 0x0b +#define DRM_FORMAT_MOD_VENDOR_APPLE 0x0c #define DRM_FORMAT_MOD_VENDOR_MIPI 0x0b #define DRM_FORMAT_MOD_VENDOR_RPI 0x0c @@ -772,6 +824,31 @@ extern "C" { */ #define I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC fourcc_mod_code(INTEL, 15) +/* + * Intel Color Control Surfaces (CCS) for graphics ver. 20 unified compression + * on integrated graphics + * + * The main surface is Tile 4 and at plane index 0. For semi-planar formats + * like NV12, the Y and UV planes are Tile 4 and are located at plane indices + * 0 and 1, respectively. The CCS for all planes are stored outside of the + * GEM object in a reserved memory area dedicated for the storage of the + * CCS data for all compressible GEM objects. + */ +#define I915_FORMAT_MOD_4_TILED_LNL_CCS fourcc_mod_code(INTEL, 16) + +/* + * Intel Color Control Surfaces (CCS) for graphics ver. 20 unified compression + * on discrete graphics + * + * The main surface is Tile 4 and at plane index 0. For semi-planar formats + * like NV12, the Y and UV planes are Tile 4 and are located at plane indices + * 0 and 1, respectively. The CCS for all planes are stored outside of the + * GEM object in a reserved memory area dedicated for the storage of the + * CCS data for all compressible GEM objects. The GEM object must be stored in + * contiguous memory with a size aligned to 64KB + */ +#define I915_FORMAT_MOD_4_TILED_BMG_CCS fourcc_mod_code(INTEL, 17) + /* * IPU3 Bayer packing layout * @@ -780,7 +857,7 @@ extern "C" { * the 6 most significant bits in the last byte unused. The format is little * endian. */ -#define IPU3_FORMAT_MOD_PACKED fourcc_mod_code(INTEL, 13) +#define IPU3_FORMAT_MOD_PACKED fourcc_mod_code(INTEL, 18) /* * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks @@ -978,14 +1055,20 @@ extern "C" { * 2 = Gob Height 8, Turing+ Page Kind mapping * 3 = Reserved for future use. * - * 22:22 s Sector layout. On Tegra GPUs prior to Xavier, there is a further - * bit remapping step that occurs at an even lower level than the - * page kind and block linear swizzles. This causes the layout of - * surfaces mapped in those SOC's GPUs to be incompatible with the - * equivalent mapping on other GPUs in the same system. - * - * 0 = Tegra K1 - Tegra Parker/TX2 Layout. - * 1 = Desktop GPU and Tegra Xavier+ Layout + * 22:22 s Sector layout. There is a further bit remapping step that occurs + * 26:27 at an even lower level than the page kind and block linear + * swizzles. This causes the bit arrangement of surfaces in memory + * to differ subtly, and prevents direct sharing of surfaces between + * GPUs with different layouts. + * + * 0 = Tegra K1 - Tegra Parker/TX2 Layout + * 1 = Pre-GB20x, GB20x 32+ bpp, GB10, Tegra Xavier-Orin Layout + * 2 = GB20x(Blackwell 2)+ 8 bpp surface layout + * 3 = GB20x(Blackwell 2)+ 16 bpp surface layout + * 4 = Reserved for future use. + * 5 = Reserved for future use. + * 6 = Reserved for future use. + * 7 = Reserved for future use. * * 25:23 c Lossless Framebuffer Compression type. * @@ -1000,7 +1083,7 @@ extern "C" { * 6 = Reserved for future use * 7 = Reserved for future use * - * 55:25 - Reserved for future use. Must be zero. + * 55:28 - Reserved for future use. Must be zero. */ #define DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(c, s, g, k, h) \ fourcc_mod_code(NVIDIA, (0x10 | \ @@ -1008,6 +1091,7 @@ extern "C" { (((k) & 0xff) << 12) | \ (((g) & 0x3) << 20) | \ (((s) & 0x1) << 22) | \ + (((s) & 0x6) << 25) | \ (((c) & 0x7) << 23))) /* To grandfather in prior block linear format modifiers to the above layout, @@ -1508,6 +1592,90 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier) */ #define AMLOGIC_FBC_OPTION_MEM_SAVING (1ULL << 0) +/* MediaTek modifiers + * Bits Parameter Notes + * ----- ------------------------ --------------------------------------------- + * 7: 0 TILE LAYOUT Values are MTK_FMT_MOD_TILE_* + * 15: 8 COMPRESSION Values are MTK_FMT_MOD_COMPRESS_* + * 23:16 10 BIT LAYOUT Values are MTK_FMT_MOD_10BIT_LAYOUT_* + * + */ + +#define DRM_FORMAT_MOD_MTK(__flags) fourcc_mod_code(MTK, __flags) + +/* + * MediaTek Tiled Modifier + * The lowest 8 bits of the modifier is used to specify the tiling + * layout. Only the 16L_32S tiling is used for now, but we define an + * "untiled" version and leave room for future expansion. + */ +#define MTK_FMT_MOD_TILE_MASK 0xf +#define MTK_FMT_MOD_TILE_NONE 0x0 +#define MTK_FMT_MOD_TILE_16L32S 0x1 + +/* + * Bits 8-15 specify compression options + */ +#define MTK_FMT_MOD_COMPRESS_MASK (0xf << 8) +#define MTK_FMT_MOD_COMPRESS_NONE (0x0 << 8) +#define MTK_FMT_MOD_COMPRESS_V1 (0x1 << 8) + +/* + * Bits 16-23 specify how the bits of 10 bit formats are + * stored out in memory + */ +#define MTK_FMT_MOD_10BIT_LAYOUT_MASK (0xf << 16) +#define MTK_FMT_MOD_10BIT_LAYOUT_PACKED (0x0 << 16) +#define MTK_FMT_MOD_10BIT_LAYOUT_LSBTILED (0x1 << 16) +#define MTK_FMT_MOD_10BIT_LAYOUT_LSBRASTER (0x2 << 16) + +/* alias for the most common tiling format */ +#define DRM_FORMAT_MOD_MTK_16L_32S_TILE DRM_FORMAT_MOD_MTK(MTK_FMT_MOD_TILE_16L32S) + +/* + * Apple GPU-tiled layouts. + * + * Apple GPUs support nonlinear tilings with optional lossless compression. + * + * GPU-tiled images are divided into 16KiB tiles: + * + * Bytes per pixel Tile size + * --------------- --------- + * 1 128x128 + * 2 128x64 + * 4 64x64 + * 8 64x32 + * 16 32x32 + * + * Tiles are raster-order. Pixels within a tile are interleaved (Morton order). + * + * Compressed images pad the body to 128-bytes and are immediately followed by a + * metadata section. The metadata section rounds the image dimensions to + * powers-of-two and contains 8 bytes for each 16x16 compression subtile. + * Subtiles are interleaved (Morton order). + * + * All images are 128-byte aligned. + * + * These layouts fundamentally do not have meaningful strides. No matter how we + * specify strides for these layouts, userspace unaware of Apple image layouts + * will be unable to use correctly the specified stride for any purpose. + * Userspace aware of the image layouts do not use strides. The most "correct" + * convention would be setting the image stride to 0. Unfortunately, some + * software assumes the stride is at least (width * bytes per pixel). We + * therefore require that stride equals (width * bytes per pixel). Since the + * stride is arbitrary here, we pick the simplest convention. + * + * Although containing two sections, compressed image layouts are treated in + * software as a single plane. This is modelled after AFBC, a similar + * scheme. Attempting to separate the sections to be "explicit" in DRM would + * only generate more confusion, as software does not treat the image this way. + * + * For detailed information on the hardware image layouts, see + * https://docs.mesa3d.org/drivers/asahi.html#image-layouts + */ +#define DRM_FORMAT_MOD_APPLE_GPU_TILED fourcc_mod_code(APPLE, 1) +#define DRM_FORMAT_MOD_APPLE_GPU_TILED_COMPRESSED fourcc_mod_code(APPLE, 2) + /* * AMD modifiers * @@ -1571,6 +1739,7 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier) * 64K_D_2D on GFX12 is identical to 64K_D on GFX11. */ #define AMD_FMT_MOD_TILE_GFX9_64K_D 10 +#define AMD_FMT_MOD_TILE_GFX9_4K_D_X 22 #define AMD_FMT_MOD_TILE_GFX9_64K_S_X 25 #define AMD_FMT_MOD_TILE_GFX9_64K_D_X 26 #define AMD_FMT_MOD_TILE_GFX9_64K_R_X 27