| Message ID | 20251210-headers-update-v6-18-v2-4-3f726742a4c8@ideasonboard.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series |
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| Related | show |
On Wed, Dec 10, 2025 at 09:19:15AM +0100, Jacopo Mondi wrote: > Update v4l2-controls.h to Linux kernel version v6.18. > > No conflicts between downstream symbols and newly added ones. > > Signed-off-by: Jacopo Mondi <jacopo.mondi@ideasonboard.com> > Acked-by: Barnabás Pőcze <barnabas.pocze@ideasonboard.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> > --- > include/linux/v4l2-controls.h | 128 ++++++++++++++++++++++-------------------- > 1 file changed, 67 insertions(+), 61 deletions(-) > > diff --git a/include/linux/v4l2-controls.h b/include/linux/v4l2-controls.h > index 4cfae0414894248bfb63aac83a46f71a5dc771c9..25914de2cd7a39a168f59cd80ed331b4b339659f 100644 > --- a/include/linux/v4l2-controls.h > +++ b/include/linux/v4l2-controls.h > @@ -217,6 +217,13 @@ enum v4l2_colorfx { > */ > #define V4L2_CID_USER_THP7312_BASE (V4L2_CID_USER_BASE + 0x11c0) > > +/* > + * The base for the uvc driver controls. > + * See linux/uvcvideo.h for the list of controls. > + * We reserve 64 controls for this driver. > + */ > +#define V4L2_CID_USER_UVC_BASE (V4L2_CID_USER_BASE + 0x11e0) > + > /* > * The base for Rockchip ISP1 driver controls. > * We reserve 16 controls for this driver. > @@ -1186,7 +1193,7 @@ enum v4l2_flash_strobe_source { > #define V4L2_CID_JPEG_CLASS_BASE (V4L2_CTRL_CLASS_JPEG | 0x900) > #define V4L2_CID_JPEG_CLASS (V4L2_CTRL_CLASS_JPEG | 1) > > -#define V4L2_CID_JPEG_CHROMA_SUBSAMPLING (V4L2_CID_JPEG_CLASS_BASE + 1) > +#define V4L2_CID_JPEG_CHROMA_SUBSAMPLING (V4L2_CID_JPEG_CLASS_BASE + 1) > enum v4l2_jpeg_chroma_subsampling { > V4L2_JPEG_CHROMA_SUBSAMPLING_444 = 0, > V4L2_JPEG_CHROMA_SUBSAMPLING_422 = 1, > @@ -1195,15 +1202,15 @@ enum v4l2_jpeg_chroma_subsampling { > V4L2_JPEG_CHROMA_SUBSAMPLING_410 = 4, > V4L2_JPEG_CHROMA_SUBSAMPLING_GRAY = 5, > }; > -#define V4L2_CID_JPEG_RESTART_INTERVAL (V4L2_CID_JPEG_CLASS_BASE + 2) > -#define V4L2_CID_JPEG_COMPRESSION_QUALITY (V4L2_CID_JPEG_CLASS_BASE + 3) > +#define V4L2_CID_JPEG_RESTART_INTERVAL (V4L2_CID_JPEG_CLASS_BASE + 2) > +#define V4L2_CID_JPEG_COMPRESSION_QUALITY (V4L2_CID_JPEG_CLASS_BASE + 3) > > -#define V4L2_CID_JPEG_ACTIVE_MARKER (V4L2_CID_JPEG_CLASS_BASE + 4) > -#define V4L2_JPEG_ACTIVE_MARKER_APP0 (1 << 0) > -#define V4L2_JPEG_ACTIVE_MARKER_APP1 (1 << 1) > -#define V4L2_JPEG_ACTIVE_MARKER_COM (1 << 16) > -#define V4L2_JPEG_ACTIVE_MARKER_DQT (1 << 17) > -#define V4L2_JPEG_ACTIVE_MARKER_DHT (1 << 18) > +#define V4L2_CID_JPEG_ACTIVE_MARKER (V4L2_CID_JPEG_CLASS_BASE + 4) > +#define V4L2_JPEG_ACTIVE_MARKER_APP0 (1 << 0) > +#define V4L2_JPEG_ACTIVE_MARKER_APP1 (1 << 1) > +#define V4L2_JPEG_ACTIVE_MARKER_COM (1 << 16) > +#define V4L2_JPEG_ACTIVE_MARKER_DQT (1 << 17) > +#define V4L2_JPEG_ACTIVE_MARKER_DHT (1 << 18) > > > /* Image source controls */ > @@ -1236,10 +1243,10 @@ enum v4l2_jpeg_chroma_subsampling { > #define V4L2_CID_DV_CLASS_BASE (V4L2_CTRL_CLASS_DV | 0x900) > #define V4L2_CID_DV_CLASS (V4L2_CTRL_CLASS_DV | 1) > > -#define V4L2_CID_DV_TX_HOTPLUG (V4L2_CID_DV_CLASS_BASE + 1) > -#define V4L2_CID_DV_TX_RXSENSE (V4L2_CID_DV_CLASS_BASE + 2) > -#define V4L2_CID_DV_TX_EDID_PRESENT (V4L2_CID_DV_CLASS_BASE + 3) > -#define V4L2_CID_DV_TX_MODE (V4L2_CID_DV_CLASS_BASE + 4) > +#define V4L2_CID_DV_TX_HOTPLUG (V4L2_CID_DV_CLASS_BASE + 1) > +#define V4L2_CID_DV_TX_RXSENSE (V4L2_CID_DV_CLASS_BASE + 2) > +#define V4L2_CID_DV_TX_EDID_PRESENT (V4L2_CID_DV_CLASS_BASE + 3) > +#define V4L2_CID_DV_TX_MODE (V4L2_CID_DV_CLASS_BASE + 4) > enum v4l2_dv_tx_mode { > V4L2_DV_TX_MODE_DVI_D = 0, > V4L2_DV_TX_MODE_HDMI = 1, > @@ -1260,7 +1267,7 @@ enum v4l2_dv_it_content_type { > V4L2_DV_IT_CONTENT_TYPE_NO_ITC = 4, > }; > > -#define V4L2_CID_DV_RX_POWER_PRESENT (V4L2_CID_DV_CLASS_BASE + 100) > +#define V4L2_CID_DV_RX_POWER_PRESENT (V4L2_CID_DV_CLASS_BASE + 100) > #define V4L2_CID_DV_RX_RGB_RANGE (V4L2_CID_DV_CLASS_BASE + 101) > #define V4L2_CID_DV_RX_IT_CONTENT_TYPE (V4L2_CID_DV_CLASS_BASE + 102) > > @@ -1530,15 +1537,6 @@ struct v4l2_ctrl_h264_pred_weights { > struct v4l2_h264_weight_factors weight_factors[2]; > }; > > -#define V4L2_H264_SLICE_TYPE_P 0 > -#define V4L2_H264_SLICE_TYPE_B 1 > -#define V4L2_H264_SLICE_TYPE_I 2 > -#define V4L2_H264_SLICE_TYPE_SP 3 > -#define V4L2_H264_SLICE_TYPE_SI 4 > - > -#define V4L2_H264_SLICE_FLAG_DIRECT_SPATIAL_MV_PRED 0x01 > -#define V4L2_H264_SLICE_FLAG_SP_FOR_SWITCH 0x02 > - > #define V4L2_H264_TOP_FIELD_REF 0x1 > #define V4L2_H264_BOTTOM_FIELD_REF 0x2 > #define V4L2_H264_FRAME_REF 0x3 > @@ -1559,8 +1557,17 @@ struct v4l2_h264_reference { > * Maximum DPB size, as specified by section 'A.3.1 Level limits > * common to the Baseline, Main, and Extended profiles'. > */ > -#define V4L2_H264_NUM_DPB_ENTRIES 16 > -#define V4L2_H264_REF_LIST_LEN (2 * V4L2_H264_NUM_DPB_ENTRIES) > +#define V4L2_H264_NUM_DPB_ENTRIES 16 > +#define V4L2_H264_REF_LIST_LEN (2 * V4L2_H264_NUM_DPB_ENTRIES) > + > +#define V4L2_H264_SLICE_TYPE_P 0 > +#define V4L2_H264_SLICE_TYPE_B 1 > +#define V4L2_H264_SLICE_TYPE_I 2 > +#define V4L2_H264_SLICE_TYPE_SP 3 > +#define V4L2_H264_SLICE_TYPE_SI 4 > + > +#define V4L2_H264_SLICE_FLAG_DIRECT_SPATIAL_MV_PRED 0x01 > +#define V4L2_H264_SLICE_FLAG_SP_FOR_SWITCH 0x02 > > #define V4L2_CID_STATELESS_H264_SLICE_PARAMS (V4L2_CID_CODEC_STATELESS_BASE + 6) > /** > @@ -1700,7 +1707,6 @@ struct v4l2_ctrl_h264_decode_params { > __u32 flags; > }; > > - > /* Stateless FWHT control, used by the vicodec driver */ > > /* Current FWHT version */ > @@ -2542,44 +2548,10 @@ struct v4l2_ctrl_hevc_scaling_matrix { > __u8 scaling_list_dc_coef_32x32[2]; > }; > > -#define V4L2_CID_COLORIMETRY_CLASS_BASE (V4L2_CTRL_CLASS_COLORIMETRY | 0x900) > -#define V4L2_CID_COLORIMETRY_CLASS (V4L2_CTRL_CLASS_COLORIMETRY | 1) > - > -#define V4L2_CID_COLORIMETRY_HDR10_CLL_INFO (V4L2_CID_COLORIMETRY_CLASS_BASE + 0) > - > -struct v4l2_ctrl_hdr10_cll_info { > - __u16 max_content_light_level; > - __u16 max_pic_average_light_level; > -}; > - > -#define V4L2_CID_COLORIMETRY_HDR10_MASTERING_DISPLAY (V4L2_CID_COLORIMETRY_CLASS_BASE + 1) > - > -#define V4L2_HDR10_MASTERING_PRIMARIES_X_LOW 5 > -#define V4L2_HDR10_MASTERING_PRIMARIES_X_HIGH 37000 > -#define V4L2_HDR10_MASTERING_PRIMARIES_Y_LOW 5 > -#define V4L2_HDR10_MASTERING_PRIMARIES_Y_HIGH 42000 > -#define V4L2_HDR10_MASTERING_WHITE_POINT_X_LOW 5 > -#define V4L2_HDR10_MASTERING_WHITE_POINT_X_HIGH 37000 > -#define V4L2_HDR10_MASTERING_WHITE_POINT_Y_LOW 5 > -#define V4L2_HDR10_MASTERING_WHITE_POINT_Y_HIGH 42000 > -#define V4L2_HDR10_MASTERING_MAX_LUMA_LOW 50000 > -#define V4L2_HDR10_MASTERING_MAX_LUMA_HIGH 100000000 > -#define V4L2_HDR10_MASTERING_MIN_LUMA_LOW 1 > -#define V4L2_HDR10_MASTERING_MIN_LUMA_HIGH 50000 > - > -struct v4l2_ctrl_hdr10_mastering_display { > - __u16 display_primaries_x[3]; > - __u16 display_primaries_y[3]; > - __u16 white_point_x; > - __u16 white_point_y; > - __u32 max_display_mastering_luminance; > - __u32 min_display_mastering_luminance; > -}; > - > /* Stateless VP9 controls */ > > #define V4L2_VP9_LOOP_FILTER_FLAG_DELTA_ENABLED 0x1 > -#define V4L2_VP9_LOOP_FILTER_FLAG_DELTA_UPDATE 0x2 > +#define V4L2_VP9_LOOP_FILTER_FLAG_DELTA_UPDATE 0x2 > > /** > * struct v4l2_vp9_loop_filter - VP9 loop filter parameters > @@ -3506,4 +3478,38 @@ struct v4l2_ctrl_av1_film_grain { > #define V4L2_CID_MPEG_CX2341X_BASE V4L2_CID_CODEC_CX2341X_BASE > #define V4L2_CID_MPEG_MFC51_BASE V4L2_CID_CODEC_MFC51_BASE > > +#define V4L2_CID_COLORIMETRY_CLASS_BASE (V4L2_CTRL_CLASS_COLORIMETRY | 0x900) > +#define V4L2_CID_COLORIMETRY_CLASS (V4L2_CTRL_CLASS_COLORIMETRY | 1) > + > +#define V4L2_CID_COLORIMETRY_HDR10_CLL_INFO (V4L2_CID_COLORIMETRY_CLASS_BASE + 0) > + > +struct v4l2_ctrl_hdr10_cll_info { > + __u16 max_content_light_level; > + __u16 max_pic_average_light_level; > +}; > + > +#define V4L2_CID_COLORIMETRY_HDR10_MASTERING_DISPLAY (V4L2_CID_COLORIMETRY_CLASS_BASE + 1) > + > +#define V4L2_HDR10_MASTERING_PRIMARIES_X_LOW 5 > +#define V4L2_HDR10_MASTERING_PRIMARIES_X_HIGH 37000 > +#define V4L2_HDR10_MASTERING_PRIMARIES_Y_LOW 5 > +#define V4L2_HDR10_MASTERING_PRIMARIES_Y_HIGH 42000 > +#define V4L2_HDR10_MASTERING_WHITE_POINT_X_LOW 5 > +#define V4L2_HDR10_MASTERING_WHITE_POINT_X_HIGH 37000 > +#define V4L2_HDR10_MASTERING_WHITE_POINT_Y_LOW 5 > +#define V4L2_HDR10_MASTERING_WHITE_POINT_Y_HIGH 42000 > +#define V4L2_HDR10_MASTERING_MAX_LUMA_LOW 50000 > +#define V4L2_HDR10_MASTERING_MAX_LUMA_HIGH 100000000 > +#define V4L2_HDR10_MASTERING_MIN_LUMA_LOW 1 > +#define V4L2_HDR10_MASTERING_MIN_LUMA_HIGH 50000 > + > +struct v4l2_ctrl_hdr10_mastering_display { > + __u16 display_primaries_x[3]; > + __u16 display_primaries_y[3]; > + __u16 white_point_x; > + __u16 white_point_y; > + __u32 max_display_mastering_luminance; > + __u32 min_display_mastering_luminance; > +}; > + > #endif
diff --git a/include/linux/v4l2-controls.h b/include/linux/v4l2-controls.h index 4cfae0414894248bfb63aac83a46f71a5dc771c9..25914de2cd7a39a168f59cd80ed331b4b339659f 100644 --- a/include/linux/v4l2-controls.h +++ b/include/linux/v4l2-controls.h @@ -217,6 +217,13 @@ enum v4l2_colorfx { */ #define V4L2_CID_USER_THP7312_BASE (V4L2_CID_USER_BASE + 0x11c0) +/* + * The base for the uvc driver controls. + * See linux/uvcvideo.h for the list of controls. + * We reserve 64 controls for this driver. + */ +#define V4L2_CID_USER_UVC_BASE (V4L2_CID_USER_BASE + 0x11e0) + /* * The base for Rockchip ISP1 driver controls. * We reserve 16 controls for this driver. @@ -1186,7 +1193,7 @@ enum v4l2_flash_strobe_source { #define V4L2_CID_JPEG_CLASS_BASE (V4L2_CTRL_CLASS_JPEG | 0x900) #define V4L2_CID_JPEG_CLASS (V4L2_CTRL_CLASS_JPEG | 1) -#define V4L2_CID_JPEG_CHROMA_SUBSAMPLING (V4L2_CID_JPEG_CLASS_BASE + 1) +#define V4L2_CID_JPEG_CHROMA_SUBSAMPLING (V4L2_CID_JPEG_CLASS_BASE + 1) enum v4l2_jpeg_chroma_subsampling { V4L2_JPEG_CHROMA_SUBSAMPLING_444 = 0, V4L2_JPEG_CHROMA_SUBSAMPLING_422 = 1, @@ -1195,15 +1202,15 @@ enum v4l2_jpeg_chroma_subsampling { V4L2_JPEG_CHROMA_SUBSAMPLING_410 = 4, V4L2_JPEG_CHROMA_SUBSAMPLING_GRAY = 5, }; -#define V4L2_CID_JPEG_RESTART_INTERVAL (V4L2_CID_JPEG_CLASS_BASE + 2) -#define V4L2_CID_JPEG_COMPRESSION_QUALITY (V4L2_CID_JPEG_CLASS_BASE + 3) +#define V4L2_CID_JPEG_RESTART_INTERVAL (V4L2_CID_JPEG_CLASS_BASE + 2) +#define V4L2_CID_JPEG_COMPRESSION_QUALITY (V4L2_CID_JPEG_CLASS_BASE + 3) -#define V4L2_CID_JPEG_ACTIVE_MARKER (V4L2_CID_JPEG_CLASS_BASE + 4) -#define V4L2_JPEG_ACTIVE_MARKER_APP0 (1 << 0) -#define V4L2_JPEG_ACTIVE_MARKER_APP1 (1 << 1) -#define V4L2_JPEG_ACTIVE_MARKER_COM (1 << 16) -#define V4L2_JPEG_ACTIVE_MARKER_DQT (1 << 17) -#define V4L2_JPEG_ACTIVE_MARKER_DHT (1 << 18) +#define V4L2_CID_JPEG_ACTIVE_MARKER (V4L2_CID_JPEG_CLASS_BASE + 4) +#define V4L2_JPEG_ACTIVE_MARKER_APP0 (1 << 0) +#define V4L2_JPEG_ACTIVE_MARKER_APP1 (1 << 1) +#define V4L2_JPEG_ACTIVE_MARKER_COM (1 << 16) +#define V4L2_JPEG_ACTIVE_MARKER_DQT (1 << 17) +#define V4L2_JPEG_ACTIVE_MARKER_DHT (1 << 18) /* Image source controls */ @@ -1236,10 +1243,10 @@ enum v4l2_jpeg_chroma_subsampling { #define V4L2_CID_DV_CLASS_BASE (V4L2_CTRL_CLASS_DV | 0x900) #define V4L2_CID_DV_CLASS (V4L2_CTRL_CLASS_DV | 1) -#define V4L2_CID_DV_TX_HOTPLUG (V4L2_CID_DV_CLASS_BASE + 1) -#define V4L2_CID_DV_TX_RXSENSE (V4L2_CID_DV_CLASS_BASE + 2) -#define V4L2_CID_DV_TX_EDID_PRESENT (V4L2_CID_DV_CLASS_BASE + 3) -#define V4L2_CID_DV_TX_MODE (V4L2_CID_DV_CLASS_BASE + 4) +#define V4L2_CID_DV_TX_HOTPLUG (V4L2_CID_DV_CLASS_BASE + 1) +#define V4L2_CID_DV_TX_RXSENSE (V4L2_CID_DV_CLASS_BASE + 2) +#define V4L2_CID_DV_TX_EDID_PRESENT (V4L2_CID_DV_CLASS_BASE + 3) +#define V4L2_CID_DV_TX_MODE (V4L2_CID_DV_CLASS_BASE + 4) enum v4l2_dv_tx_mode { V4L2_DV_TX_MODE_DVI_D = 0, V4L2_DV_TX_MODE_HDMI = 1, @@ -1260,7 +1267,7 @@ enum v4l2_dv_it_content_type { V4L2_DV_IT_CONTENT_TYPE_NO_ITC = 4, }; -#define V4L2_CID_DV_RX_POWER_PRESENT (V4L2_CID_DV_CLASS_BASE + 100) +#define V4L2_CID_DV_RX_POWER_PRESENT (V4L2_CID_DV_CLASS_BASE + 100) #define V4L2_CID_DV_RX_RGB_RANGE (V4L2_CID_DV_CLASS_BASE + 101) #define V4L2_CID_DV_RX_IT_CONTENT_TYPE (V4L2_CID_DV_CLASS_BASE + 102) @@ -1530,15 +1537,6 @@ struct v4l2_ctrl_h264_pred_weights { struct v4l2_h264_weight_factors weight_factors[2]; }; -#define V4L2_H264_SLICE_TYPE_P 0 -#define V4L2_H264_SLICE_TYPE_B 1 -#define V4L2_H264_SLICE_TYPE_I 2 -#define V4L2_H264_SLICE_TYPE_SP 3 -#define V4L2_H264_SLICE_TYPE_SI 4 - -#define V4L2_H264_SLICE_FLAG_DIRECT_SPATIAL_MV_PRED 0x01 -#define V4L2_H264_SLICE_FLAG_SP_FOR_SWITCH 0x02 - #define V4L2_H264_TOP_FIELD_REF 0x1 #define V4L2_H264_BOTTOM_FIELD_REF 0x2 #define V4L2_H264_FRAME_REF 0x3 @@ -1559,8 +1557,17 @@ struct v4l2_h264_reference { * Maximum DPB size, as specified by section 'A.3.1 Level limits * common to the Baseline, Main, and Extended profiles'. */ -#define V4L2_H264_NUM_DPB_ENTRIES 16 -#define V4L2_H264_REF_LIST_LEN (2 * V4L2_H264_NUM_DPB_ENTRIES) +#define V4L2_H264_NUM_DPB_ENTRIES 16 +#define V4L2_H264_REF_LIST_LEN (2 * V4L2_H264_NUM_DPB_ENTRIES) + +#define V4L2_H264_SLICE_TYPE_P 0 +#define V4L2_H264_SLICE_TYPE_B 1 +#define V4L2_H264_SLICE_TYPE_I 2 +#define V4L2_H264_SLICE_TYPE_SP 3 +#define V4L2_H264_SLICE_TYPE_SI 4 + +#define V4L2_H264_SLICE_FLAG_DIRECT_SPATIAL_MV_PRED 0x01 +#define V4L2_H264_SLICE_FLAG_SP_FOR_SWITCH 0x02 #define V4L2_CID_STATELESS_H264_SLICE_PARAMS (V4L2_CID_CODEC_STATELESS_BASE + 6) /** @@ -1700,7 +1707,6 @@ struct v4l2_ctrl_h264_decode_params { __u32 flags; }; - /* Stateless FWHT control, used by the vicodec driver */ /* Current FWHT version */ @@ -2542,44 +2548,10 @@ struct v4l2_ctrl_hevc_scaling_matrix { __u8 scaling_list_dc_coef_32x32[2]; }; -#define V4L2_CID_COLORIMETRY_CLASS_BASE (V4L2_CTRL_CLASS_COLORIMETRY | 0x900) -#define V4L2_CID_COLORIMETRY_CLASS (V4L2_CTRL_CLASS_COLORIMETRY | 1) - -#define V4L2_CID_COLORIMETRY_HDR10_CLL_INFO (V4L2_CID_COLORIMETRY_CLASS_BASE + 0) - -struct v4l2_ctrl_hdr10_cll_info { - __u16 max_content_light_level; - __u16 max_pic_average_light_level; -}; - -#define V4L2_CID_COLORIMETRY_HDR10_MASTERING_DISPLAY (V4L2_CID_COLORIMETRY_CLASS_BASE + 1) - -#define V4L2_HDR10_MASTERING_PRIMARIES_X_LOW 5 -#define V4L2_HDR10_MASTERING_PRIMARIES_X_HIGH 37000 -#define V4L2_HDR10_MASTERING_PRIMARIES_Y_LOW 5 -#define V4L2_HDR10_MASTERING_PRIMARIES_Y_HIGH 42000 -#define V4L2_HDR10_MASTERING_WHITE_POINT_X_LOW 5 -#define V4L2_HDR10_MASTERING_WHITE_POINT_X_HIGH 37000 -#define V4L2_HDR10_MASTERING_WHITE_POINT_Y_LOW 5 -#define V4L2_HDR10_MASTERING_WHITE_POINT_Y_HIGH 42000 -#define V4L2_HDR10_MASTERING_MAX_LUMA_LOW 50000 -#define V4L2_HDR10_MASTERING_MAX_LUMA_HIGH 100000000 -#define V4L2_HDR10_MASTERING_MIN_LUMA_LOW 1 -#define V4L2_HDR10_MASTERING_MIN_LUMA_HIGH 50000 - -struct v4l2_ctrl_hdr10_mastering_display { - __u16 display_primaries_x[3]; - __u16 display_primaries_y[3]; - __u16 white_point_x; - __u16 white_point_y; - __u32 max_display_mastering_luminance; - __u32 min_display_mastering_luminance; -}; - /* Stateless VP9 controls */ #define V4L2_VP9_LOOP_FILTER_FLAG_DELTA_ENABLED 0x1 -#define V4L2_VP9_LOOP_FILTER_FLAG_DELTA_UPDATE 0x2 +#define V4L2_VP9_LOOP_FILTER_FLAG_DELTA_UPDATE 0x2 /** * struct v4l2_vp9_loop_filter - VP9 loop filter parameters @@ -3506,4 +3478,38 @@ struct v4l2_ctrl_av1_film_grain { #define V4L2_CID_MPEG_CX2341X_BASE V4L2_CID_CODEC_CX2341X_BASE #define V4L2_CID_MPEG_MFC51_BASE V4L2_CID_CODEC_MFC51_BASE +#define V4L2_CID_COLORIMETRY_CLASS_BASE (V4L2_CTRL_CLASS_COLORIMETRY | 0x900) +#define V4L2_CID_COLORIMETRY_CLASS (V4L2_CTRL_CLASS_COLORIMETRY | 1) + +#define V4L2_CID_COLORIMETRY_HDR10_CLL_INFO (V4L2_CID_COLORIMETRY_CLASS_BASE + 0) + +struct v4l2_ctrl_hdr10_cll_info { + __u16 max_content_light_level; + __u16 max_pic_average_light_level; +}; + +#define V4L2_CID_COLORIMETRY_HDR10_MASTERING_DISPLAY (V4L2_CID_COLORIMETRY_CLASS_BASE + 1) + +#define V4L2_HDR10_MASTERING_PRIMARIES_X_LOW 5 +#define V4L2_HDR10_MASTERING_PRIMARIES_X_HIGH 37000 +#define V4L2_HDR10_MASTERING_PRIMARIES_Y_LOW 5 +#define V4L2_HDR10_MASTERING_PRIMARIES_Y_HIGH 42000 +#define V4L2_HDR10_MASTERING_WHITE_POINT_X_LOW 5 +#define V4L2_HDR10_MASTERING_WHITE_POINT_X_HIGH 37000 +#define V4L2_HDR10_MASTERING_WHITE_POINT_Y_LOW 5 +#define V4L2_HDR10_MASTERING_WHITE_POINT_Y_HIGH 42000 +#define V4L2_HDR10_MASTERING_MAX_LUMA_LOW 50000 +#define V4L2_HDR10_MASTERING_MAX_LUMA_HIGH 100000000 +#define V4L2_HDR10_MASTERING_MIN_LUMA_LOW 1 +#define V4L2_HDR10_MASTERING_MIN_LUMA_HIGH 50000 + +struct v4l2_ctrl_hdr10_mastering_display { + __u16 display_primaries_x[3]; + __u16 display_primaries_y[3]; + __u16 white_point_x; + __u16 white_point_y; + __u32 max_display_mastering_luminance; + __u32 min_display_mastering_luminance; +}; + #endif