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{ "id": 25349, "url": "https://patchwork.libcamera.org/api/1.1/patches/25349/?format=api", "web_url": "https://patchwork.libcamera.org/patch/25349/", "project": { "id": 1, "url": "https://patchwork.libcamera.org/api/1.1/projects/1/?format=api", "name": "libcamera", "link_name": "libcamera", "list_id": "libcamera_core", "list_email": "libcamera-devel@lists.libcamera.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20251204-headers-update-v6-18-v1-1-93135d14a081@ideasonboard.com>", "date": "2025-12-04T15:54:14", "name": "[1/6] include: linux: drm_fourcc.h: Update to v6.18", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "774be903f8bdc406c684e6babfbe45e3fca868ca", "submitter": { "id": 143, "url": "https://patchwork.libcamera.org/api/1.1/people/143/?format=api", "name": "Jacopo Mondi", "email": "jacopo.mondi@ideasonboard.com" }, "delegate": null, "mbox": "https://patchwork.libcamera.org/patch/25349/mbox/", "series": [ { "id": 5635, "url": "https://patchwork.libcamera.org/api/1.1/series/5635/?format=api", "web_url": "https://patchwork.libcamera.org/project/libcamera/list/?series=5635", "date": "2025-12-04T15:54:13", "name": "include: linux: Update headers to Linux v6.18", "version": 1, "mbox": "https://patchwork.libcamera.org/series/5635/mbox/" } ], "comments": "https://patchwork.libcamera.org/api/patches/25349/comments/", "check": "pending", "checks": "https://patchwork.libcamera.org/api/patches/25349/checks/", "tags": {}, "headers": { "Return-Path": "<libcamera-devel-bounces@lists.libcamera.org>", "X-Original-To": "parsemail@patchwork.libcamera.org", "Delivered-To": "parsemail@patchwork.libcamera.org", "Received": [ "from lancelot.ideasonboard.com (lancelot.ideasonboard.com\n\t[92.243.16.209])\n\tby patchwork.libcamera.org (Postfix) with ESMTPS id E5DA9C3260\n\tfor <parsemail@patchwork.libcamera.org>;\n\tThu, 4 Dec 2025 15:54:43 +0000 (UTC)", "from lancelot.ideasonboard.com (localhost [IPv6:::1])\n\tby lancelot.ideasonboard.com (Postfix) with ESMTP id 79F0961105;\n\tThu, 4 Dec 2025 16:54:41 +0100 (CET)", "from perceval.ideasonboard.com (perceval.ideasonboard.com\n\t[IPv6:2001:4b98:dc2:55:216:3eff:fef7:d647])\n\tby lancelot.ideasonboard.com (Postfix) with ESMTPS id 8DCBB609E0\n\tfor <libcamera-devel@lists.libcamera.org>;\n\tThu, 4 Dec 2025 16:54:39 +0100 (CET)", "from [192.168.1.182] (93-46-82-201.ip106.fastwebnet.it\n\t[93.46.82.201])\n\tby perceval.ideasonboard.com (Postfix) with ESMTPSA id 7D2FFE91;\n\tThu, 4 Dec 2025 16:52:22 +0100 (CET)" ], "Authentication-Results": "lancelot.ideasonboard.com; dkim=pass (1024-bit key;\n\tunprotected) header.d=ideasonboard.com header.i=@ideasonboard.com\n\theader.b=\"ZxbuPRJ3\"; dkim-atps=neutral", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com;\n\ts=mail; t=1764863542;\n\tbh=D+2HNa4Rc4PsukmGvXDb7y2/cPHyfwXKwKdjcamsDUI=;\n\th=From:Date:Subject:References:In-Reply-To:To:Cc:From;\n\tb=ZxbuPRJ3szQo8sogSRz8l9U+BVGoGILC6GoJn7C8yTO0dbp8FwyRpniCCbwCy2qhn\n\tbhdEg2g0Ykk9iFOA4uBXZhG9/75xMiN7bSxIqPzlhZW1YUgTEKeX3rx3K8gh9nHGmG\n\t5hWnQTwOZM3NTkYS7U0G+l2j7GnLQDzCRPmJpBwg=", "From": "Jacopo Mondi <jacopo.mondi@ideasonboard.com>", "Date": "Thu, 04 Dec 2025 16:54:14 +0100", "Subject": "[PATCH 1/6] include: linux: drm_fourcc.h: Update to v6.18", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "<20251204-headers-update-v6-18-v1-1-93135d14a081@ideasonboard.com>", "References": "<20251204-headers-update-v6-18-v1-0-93135d14a081@ideasonboard.com>", "In-Reply-To": "<20251204-headers-update-v6-18-v1-0-93135d14a081@ideasonboard.com>", "To": "libcamera-devel@lists.libcamera.org", "Cc": "Jacopo Mondi <jacopo.mondi@ideasonboard.com>", "X-Mailer": "b4 0.14.2", "X-Developer-Signature": "v=1; a=openpgp-sha256; l=13302;\n\ti=jacopo.mondi@ideasonboard.com; h=from:subject:message-id;\n\tbh=D+2HNa4Rc4PsukmGvXDb7y2/cPHyfwXKwKdjcamsDUI=;\n\tb=owEBbQKS/ZANAwAKAXI0Bo8WoVY8AcsmYgBpMa68mDH8rZ11GO5y7CpnfZoHm9ZjuJAOAEmYm\n\tFVDd9Dh63+JAjMEAAEKAB0WIQS1xD1IgJogio9YOMByNAaPFqFWPAUCaTGuvAAKCRByNAaPFqFW\n\tPGztD/oCK8RdtnS7Pc4EFgrFPcDYD9Qmhm3Wb1IcYG6K4ZNAwj+1hEZFdfjE/OZLsbIJ24sjvtH\n\tcIeEbrWc00avVqdjG/LcCKYyd8KNOKPWFvmhXZkRp+FfQ1FAJhrfuQ5HY4B3zYJ13Q8/ivUHy+I\n\tywA6CgSQQzeOz7w2wEs5BFmDBtAmWAxf8oJvMQhhvUKM2dyeP0ISxNnAHBieHYNJCgbTNYRkU1b\n\t6mzhj6pqPB3uKOvXziaBjSe+LqJ+HImCQ36tNEZd15lD963C6y+Ux1meXrTSRJeg77bNmK0Kdm/\n\tfVf+k5EsRxZeK7/go8atOhY4nwaJiVLEYZYbVyUwuKhnNZcJZRTO+NeCNQxXweo7fJhizSo9zBy\n\t4oyIsFQ2TivStUp3/ONPt89pErycNIsnomchUBg5Bx2So+OEfW2wVTw1x7va5anG+LeudMZwR98\n\tLyI7YirnTwMRFuMIHrnSsOvW5om7nrTeeStyHthM5+dmaQDdNTK/o9UWJEGwc9rYakU6gUBIJ18\n\teZs9Giod5cSTAXrY2ElKg2aqoTDn00iIyjI/ce5iU7IKcyklLRyUySdKhO1gnkKdDvMHCDbA2FT\n\t3NesA4JhC/Co7J1XdWFDV4UJb+sPTOUkGCKAoA1isvQkzHe0B53MdR8XACT3ZDYTpA3/st5Cf9g\n\tW+2bX7KhtTJu5Jw==", "X-Developer-Key": "i=jacopo.mondi@ideasonboard.com; a=openpgp;\n\tfpr=72392EDC88144A65C701EA9BA5826A2587AD026B", "X-BeenThere": "libcamera-devel@lists.libcamera.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "<libcamera-devel.lists.libcamera.org>", "List-Unsubscribe": "<https://lists.libcamera.org/options/libcamera-devel>,\n\t<mailto:libcamera-devel-request@lists.libcamera.org?subject=unsubscribe>", "List-Archive": "<https://lists.libcamera.org/pipermail/libcamera-devel/>", "List-Post": "<mailto:libcamera-devel@lists.libcamera.org>", "List-Help": "<mailto:libcamera-devel-request@lists.libcamera.org?subject=help>", "List-Subscribe": "<https://lists.libcamera.org/listinfo/libcamera-devel>,\n\t<mailto:libcamera-devel-request@lists.libcamera.org?subject=subscribe>", "Errors-To": "libcamera-devel-bounces@lists.libcamera.org", "Sender": "\"libcamera-devel\" <libcamera-devel-bounces@lists.libcamera.org>" }, "content": "Update drm_fourcc.h to Linux kernel version v6.18.\n\nAs the upstream drm_fourcc.h version doesn't include formats\ndefinitions for RAW Bayer formats, we have to re-define some of\nthe symbols we kept downstream as new symbols have been added in\nmainline with the same values.\n\nIn particular:\n-#define IPU3_FORMAT_MOD_PACKED fourcc_mod_code(INTEL, 13)\n+#define IPU3_FORMAT_MOD_PACKED fourcc_mod_code(INTEL, 18)\n\nand\n\n-#define DRM_FORMAT_MOD_VENDOR_MIPI 0x0b\n-#define DRM_FORMAT_MOD_VENDOR_RPI 0x0c\n+#define DRM_FORMAT_MOD_VENDOR_MIPI 0x0e\n+#define DRM_FORMAT_MOD_VENDOR_RPI 0x0f\n\nSigned-off-by: Jacopo Mondi <jacopo.mondi@ideasonboard.com>\n---\n include/linux/drm_fourcc.h | 195 ++++++++++++++++++++++++++++++++++++++++++---\n 1 file changed, 182 insertions(+), 13 deletions(-)", "diff": "diff --git a/include/linux/drm_fourcc.h b/include/linux/drm_fourcc.h\nindex db6798776663086c12d321d2ed708edc7ec77f71..26e2cdddc9625ec494d0c8f944f87d6439c3588d 100644\n--- a/include/linux/drm_fourcc.h\n+++ b/include/linux/drm_fourcc.h\n@@ -222,7 +222,7 @@ extern \"C\" {\n #define DRM_FORMAT_ABGR16161616\tfourcc_code('A', 'B', '4', '8') /* [63:0] A:B:G:R 16:16:16:16 little endian */\n \n /*\n- * Floating point 64bpp RGB\n+ * Half-Floating point - 16b/component\n * IEEE 754-2008 binary16 half-precision float\n * [15:0] sign:exponent:mantissa 1:5:10\n */\n@@ -232,6 +232,20 @@ extern \"C\" {\n #define DRM_FORMAT_ARGB16161616F fourcc_code('A', 'R', '4', 'H') /* [63:0] A:R:G:B 16:16:16:16 little endian */\n #define DRM_FORMAT_ABGR16161616F fourcc_code('A', 'B', '4', 'H') /* [63:0] A:B:G:R 16:16:16:16 little endian */\n \n+#define DRM_FORMAT_R16F fourcc_code('R', ' ', ' ', 'H') /* [15:0] R 16 little endian */\n+#define DRM_FORMAT_GR1616F fourcc_code('G', 'R', ' ', 'H') /* [31:0] G:R 16:16 little endian */\n+#define DRM_FORMAT_BGR161616F fourcc_code('B', 'G', 'R', 'H') /* [47:0] B:G:R 16:16:16 little endian */\n+\n+/*\n+ * Floating point - 32b/component\n+ * IEEE 754-2008 binary32 float\n+ * [31:0] sign:exponent:mantissa 1:8:23\n+ */\n+#define DRM_FORMAT_R32F fourcc_code('R', ' ', ' ', 'F') /* [31:0] R 32 little endian */\n+#define DRM_FORMAT_GR3232F fourcc_code('G', 'R', ' ', 'F') /* [63:0] R:G 32:32 little endian */\n+#define DRM_FORMAT_BGR323232F fourcc_code('B', 'G', 'R', 'F') /* [95:0] R:G:B 32:32:32 little endian */\n+#define DRM_FORMAT_ABGR32323232F fourcc_code('A', 'B', '8', 'F') /* [127:0] R:G:B:A 32:32:32:32 little endian */\n+\n /*\n * RGBA format with 10-bit components packed in 64-bit per pixel, with 6 bits\n * of unused padding per component:\n@@ -381,6 +395,42 @@ extern \"C\" {\n */\n #define DRM_FORMAT_Q401\t\tfourcc_code('Q', '4', '0', '1')\n \n+/*\n+ * 3 plane YCbCr LSB aligned\n+ * In order to use these formats in a similar fashion to MSB aligned ones\n+ * implementation can multiply the values by 2^6=64. For that reason the padding\n+ * must only contain zeros.\n+ * index 0 = Y plane, [15:0] z:Y [6:10] little endian\n+ * index 1 = Cr plane, [15:0] z:Cr [6:10] little endian\n+ * index 2 = Cb plane, [15:0] z:Cb [6:10] little endian\n+ */\n+#define DRM_FORMAT_S010\tfourcc_code('S', '0', '1', '0') /* 2x2 subsampled Cb (1) and Cr (2) planes 10 bits per channel */\n+#define DRM_FORMAT_S210\tfourcc_code('S', '2', '1', '0') /* 2x1 subsampled Cb (1) and Cr (2) planes 10 bits per channel */\n+#define DRM_FORMAT_S410\tfourcc_code('S', '4', '1', '0') /* non-subsampled Cb (1) and Cr (2) planes 10 bits per channel */\n+\n+/*\n+ * 3 plane YCbCr LSB aligned\n+ * In order to use these formats in a similar fashion to MSB aligned ones\n+ * implementation can multiply the values by 2^4=16. For that reason the padding\n+ * must only contain zeros.\n+ * index 0 = Y plane, [15:0] z:Y [4:12] little endian\n+ * index 1 = Cr plane, [15:0] z:Cr [4:12] little endian\n+ * index 2 = Cb plane, [15:0] z:Cb [4:12] little endian\n+ */\n+#define DRM_FORMAT_S012\tfourcc_code('S', '0', '1', '2') /* 2x2 subsampled Cb (1) and Cr (2) planes 12 bits per channel */\n+#define DRM_FORMAT_S212\tfourcc_code('S', '2', '1', '2') /* 2x1 subsampled Cb (1) and Cr (2) planes 12 bits per channel */\n+#define DRM_FORMAT_S412\tfourcc_code('S', '4', '1', '2') /* non-subsampled Cb (1) and Cr (2) planes 12 bits per channel */\n+\n+/*\n+ * 3 plane YCbCr\n+ * index 0 = Y plane, [15:0] Y little endian\n+ * index 1 = Cr plane, [15:0] Cr little endian\n+ * index 2 = Cb plane, [15:0] Cb little endian\n+ */\n+#define DRM_FORMAT_S016\tfourcc_code('S', '0', '1', '6') /* 2x2 subsampled Cb (1) and Cr (2) planes 16 bits per channel */\n+#define DRM_FORMAT_S216\tfourcc_code('S', '2', '1', '6') /* 2x1 subsampled Cb (1) and Cr (2) planes 16 bits per channel */\n+#define DRM_FORMAT_S416\tfourcc_code('S', '4', '1', '6') /* non-subsampled Cb (1) and Cr (2) planes 16 bits per channel */\n+\n /*\n * 3 plane YCbCr\n * index 0: Y plane, [7:0] Y\n@@ -489,8 +539,10 @@ extern \"C\" {\n #define DRM_FORMAT_MOD_VENDOR_ARM 0x08\n #define DRM_FORMAT_MOD_VENDOR_ALLWINNER 0x09\n #define DRM_FORMAT_MOD_VENDOR_AMLOGIC 0x0a\n-#define DRM_FORMAT_MOD_VENDOR_MIPI 0x0b\n-#define DRM_FORMAT_MOD_VENDOR_RPI 0x0c\n+#define DRM_FORMAT_MOD_VENDOR_MTK 0x0b\n+#define DRM_FORMAT_MOD_VENDOR_APPLE 0x0c\n+#define DRM_FORMAT_MOD_VENDOR_MIPI 0x0e\n+#define DRM_FORMAT_MOD_VENDOR_RPI 0x0f\n \n /* add more to the end as needed */\n \n@@ -772,6 +824,31 @@ extern \"C\" {\n */\n #define I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC fourcc_mod_code(INTEL, 15)\n \n+/*\n+ * Intel Color Control Surfaces (CCS) for graphics ver. 20 unified compression\n+ * on integrated graphics\n+ *\n+ * The main surface is Tile 4 and at plane index 0. For semi-planar formats\n+ * like NV12, the Y and UV planes are Tile 4 and are located at plane indices\n+ * 0 and 1, respectively. The CCS for all planes are stored outside of the\n+ * GEM object in a reserved memory area dedicated for the storage of the\n+ * CCS data for all compressible GEM objects.\n+ */\n+#define I915_FORMAT_MOD_4_TILED_LNL_CCS fourcc_mod_code(INTEL, 16)\n+\n+/*\n+ * Intel Color Control Surfaces (CCS) for graphics ver. 20 unified compression\n+ * on discrete graphics\n+ *\n+ * The main surface is Tile 4 and at plane index 0. For semi-planar formats\n+ * like NV12, the Y and UV planes are Tile 4 and are located at plane indices\n+ * 0 and 1, respectively. The CCS for all planes are stored outside of the\n+ * GEM object in a reserved memory area dedicated for the storage of the\n+ * CCS data for all compressible GEM objects. The GEM object must be stored in\n+ * contiguous memory with a size aligned to 64KB\n+ */\n+#define I915_FORMAT_MOD_4_TILED_BMG_CCS fourcc_mod_code(INTEL, 17)\n+\n /*\n * IPU3 Bayer packing layout\n *\n@@ -780,7 +857,7 @@ extern \"C\" {\n * the 6 most significant bits in the last byte unused. The format is little\n * endian.\n */\n-#define IPU3_FORMAT_MOD_PACKED fourcc_mod_code(INTEL, 13)\n+#define IPU3_FORMAT_MOD_PACKED fourcc_mod_code(INTEL, 18)\n \n /*\n * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks\n@@ -978,14 +1055,20 @@ extern \"C\" {\n * 2 = Gob Height 8, Turing+ Page Kind mapping\n * 3 = Reserved for future use.\n *\n- * 22:22 s Sector layout. On Tegra GPUs prior to Xavier, there is a further\n- * bit remapping step that occurs at an even lower level than the\n- * page kind and block linear swizzles. This causes the layout of\n- * surfaces mapped in those SOC's GPUs to be incompatible with the\n- * equivalent mapping on other GPUs in the same system.\n- *\n- * 0 = Tegra K1 - Tegra Parker/TX2 Layout.\n- * 1 = Desktop GPU and Tegra Xavier+ Layout\n+ * 22:22 s Sector layout. There is a further bit remapping step that occurs\n+ * 26:27 at an even lower level than the page kind and block linear\n+ * swizzles. This causes the bit arrangement of surfaces in memory\n+ * to differ subtly, and prevents direct sharing of surfaces between\n+ * GPUs with different layouts.\n+ *\n+ * 0 = Tegra K1 - Tegra Parker/TX2 Layout\n+ * 1 = Pre-GB20x, GB20x 32+ bpp, GB10, Tegra Xavier-Orin Layout\n+ * 2 = GB20x(Blackwell 2)+ 8 bpp surface layout\n+ * 3 = GB20x(Blackwell 2)+ 16 bpp surface layout\n+ * 4 = Reserved for future use.\n+ * 5 = Reserved for future use.\n+ * 6 = Reserved for future use.\n+ * 7 = Reserved for future use.\n *\n * 25:23 c Lossless Framebuffer Compression type.\n *\n@@ -1000,7 +1083,7 @@ extern \"C\" {\n * 6 = Reserved for future use\n * 7 = Reserved for future use\n *\n- * 55:25 - Reserved for future use. Must be zero.\n+ * 55:28 - Reserved for future use. Must be zero.\n */\n #define DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(c, s, g, k, h) \\\n \tfourcc_mod_code(NVIDIA, (0x10 | \\\n@@ -1008,6 +1091,7 @@ extern \"C\" {\n \t\t\t\t (((k) & 0xff) << 12) | \\\n \t\t\t\t (((g) & 0x3) << 20) | \\\n \t\t\t\t (((s) & 0x1) << 22) | \\\n+\t\t\t\t (((s) & 0x6) << 25) | \\\n \t\t\t\t (((c) & 0x7) << 23)))\n \n /* To grandfather in prior block linear format modifiers to the above layout,\n@@ -1508,6 +1592,90 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier)\n */\n #define AMLOGIC_FBC_OPTION_MEM_SAVING\t\t(1ULL << 0)\n \n+/* MediaTek modifiers\n+ * Bits Parameter Notes\n+ * ----- ------------------------ ---------------------------------------------\n+ * 7: 0 TILE LAYOUT Values are MTK_FMT_MOD_TILE_*\n+ * 15: 8 COMPRESSION Values are MTK_FMT_MOD_COMPRESS_*\n+ * 23:16 10 BIT LAYOUT Values are MTK_FMT_MOD_10BIT_LAYOUT_*\n+ *\n+ */\n+\n+#define DRM_FORMAT_MOD_MTK(__flags)\t\tfourcc_mod_code(MTK, __flags)\n+\n+/*\n+ * MediaTek Tiled Modifier\n+ * The lowest 8 bits of the modifier is used to specify the tiling\n+ * layout. Only the 16L_32S tiling is used for now, but we define an\n+ * \"untiled\" version and leave room for future expansion.\n+ */\n+#define MTK_FMT_MOD_TILE_MASK 0xf\n+#define MTK_FMT_MOD_TILE_NONE 0x0\n+#define MTK_FMT_MOD_TILE_16L32S 0x1\n+\n+/*\n+ * Bits 8-15 specify compression options\n+ */\n+#define MTK_FMT_MOD_COMPRESS_MASK (0xf << 8)\n+#define MTK_FMT_MOD_COMPRESS_NONE (0x0 << 8)\n+#define MTK_FMT_MOD_COMPRESS_V1 (0x1 << 8)\n+\n+/*\n+ * Bits 16-23 specify how the bits of 10 bit formats are\n+ * stored out in memory\n+ */\n+#define MTK_FMT_MOD_10BIT_LAYOUT_MASK (0xf << 16)\n+#define MTK_FMT_MOD_10BIT_LAYOUT_PACKED (0x0 << 16)\n+#define MTK_FMT_MOD_10BIT_LAYOUT_LSBTILED (0x1 << 16)\n+#define MTK_FMT_MOD_10BIT_LAYOUT_LSBRASTER (0x2 << 16)\n+\n+/* alias for the most common tiling format */\n+#define DRM_FORMAT_MOD_MTK_16L_32S_TILE DRM_FORMAT_MOD_MTK(MTK_FMT_MOD_TILE_16L32S)\n+\n+/*\n+ * Apple GPU-tiled layouts.\n+ *\n+ * Apple GPUs support nonlinear tilings with optional lossless compression.\n+ *\n+ * GPU-tiled images are divided into 16KiB tiles:\n+ *\n+ * Bytes per pixel Tile size\n+ * --------------- ---------\n+ * 1 128x128\n+ * 2 128x64\n+ * 4 64x64\n+ * 8 64x32\n+ * 16 32x32\n+ *\n+ * Tiles are raster-order. Pixels within a tile are interleaved (Morton order).\n+ *\n+ * Compressed images pad the body to 128-bytes and are immediately followed by a\n+ * metadata section. The metadata section rounds the image dimensions to\n+ * powers-of-two and contains 8 bytes for each 16x16 compression subtile.\n+ * Subtiles are interleaved (Morton order).\n+ *\n+ * All images are 128-byte aligned.\n+ *\n+ * These layouts fundamentally do not have meaningful strides. No matter how we\n+ * specify strides for these layouts, userspace unaware of Apple image layouts\n+ * will be unable to use correctly the specified stride for any purpose.\n+ * Userspace aware of the image layouts do not use strides. The most \"correct\"\n+ * convention would be setting the image stride to 0. Unfortunately, some\n+ * software assumes the stride is at least (width * bytes per pixel). We\n+ * therefore require that stride equals (width * bytes per pixel). Since the\n+ * stride is arbitrary here, we pick the simplest convention.\n+ *\n+ * Although containing two sections, compressed image layouts are treated in\n+ * software as a single plane. This is modelled after AFBC, a similar\n+ * scheme. Attempting to separate the sections to be \"explicit\" in DRM would\n+ * only generate more confusion, as software does not treat the image this way.\n+ *\n+ * For detailed information on the hardware image layouts, see\n+ * https://docs.mesa3d.org/drivers/asahi.html#image-layouts\n+ */\n+#define DRM_FORMAT_MOD_APPLE_GPU_TILED fourcc_mod_code(APPLE, 1)\n+#define DRM_FORMAT_MOD_APPLE_GPU_TILED_COMPRESSED fourcc_mod_code(APPLE, 2)\n+\n /*\n * AMD modifiers\n *\n@@ -1571,6 +1739,7 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier)\n * 64K_D_2D on GFX12 is identical to 64K_D on GFX11.\n */\n #define AMD_FMT_MOD_TILE_GFX9_64K_D 10\n+#define AMD_FMT_MOD_TILE_GFX9_4K_D_X 22\n #define AMD_FMT_MOD_TILE_GFX9_64K_S_X 25\n #define AMD_FMT_MOD_TILE_GFX9_64K_D_X 26\n #define AMD_FMT_MOD_TILE_GFX9_64K_R_X 27\n", "prefixes": [ "1/6" ] }