{"id":26608,"url":"https://patchwork.libcamera.org/api/patches/26608/?format=json","web_url":"https://patchwork.libcamera.org/patch/26608/","project":{"id":1,"url":"https://patchwork.libcamera.org/api/projects/1/?format=json","name":"libcamera","link_name":"libcamera","list_id":"libcamera_core","list_email":"libcamera-devel@lists.libcamera.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260504000431.1340150-6-laurent.pinchart@ideasonboard.com>","date":"2026-05-04T00:04:30","name":"[5/6] include: linux: Update to Linux v7.0","commit_ref":null,"pull_url":null,"state":"accepted","archived":false,"hash":"e7b2b31a0704557dcada4d03fc7acfcd361f8f6f","submitter":{"id":2,"url":"https://patchwork.libcamera.org/api/people/2/?format=json","name":"Laurent Pinchart","email":"laurent.pinchart@ideasonboard.com"},"delegate":null,"mbox":"https://patchwork.libcamera.org/patch/26608/mbox/","series":[{"id":5900,"url":"https://patchwork.libcamera.org/api/series/5900/?format=json","web_url":"https://patchwork.libcamera.org/project/libcamera/list/?series=5900","date":"2026-05-04T00:04:25","name":"libcamera: kernel headers update","version":1,"mbox":"https://patchwork.libcamera.org/series/5900/mbox/"}],"comments":"https://patchwork.libcamera.org/api/patches/26608/comments/","check":"pending","checks":"https://patchwork.libcamera.org/api/patches/26608/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"parsemail@patchwork.libcamera.org","Delivered-To":"parsemail@patchwork.libcamera.org","Received":["from lancelot.ideasonboard.com (lancelot.ideasonboard.com\n\t[92.243.16.209])\n\tby patchwork.libcamera.org (Postfix) with ESMTPS id 07F17C32F7\n\tfor ;\n\tMon, 4 May 2026 00:04:45 +0000 (UTC)","from lancelot.ideasonboard.com (localhost [IPv6:::1])\n\tby lancelot.ideasonboard.com (Postfix) with ESMTP id 2EAA162E6A;\n\tMon, 4 May 2026 02:04:45 +0200 (CEST)","from perceval.ideasonboard.com (perceval.ideasonboard.com\n\t[213.167.242.64])\n\tby lancelot.ideasonboard.com (Postfix) with ESMTPS id 4283F6302A\n\tfor ;\n\tMon, 4 May 2026 02:04:40 +0200 (CEST)","from killaraus.ideasonboard.com\n\t(2001-14ba-703d-e500--2a1.rev.dnainternet.fi\n\t[IPv6:2001:14ba:703d:e500::2a1])\n\tby perceval.ideasonboard.com (Postfix) with ESMTPSA id 805169C\n\tfor ;\n\tMon, 4 May 2026 02:04:38 +0200 (CEST)"],"Authentication-Results":"lancelot.ideasonboard.com; dkim=pass (1024-bit key;\n\tunprotected) header.d=ideasonboard.com header.i=@ideasonboard.com\n\theader.b=\"m8ntiktl\"; dkim-atps=neutral","DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com;\n\ts=mail; t=1777853078;\n\tbh=Jae5Kj+ejrHcTwQoNMNC9cvtcUKS6EhYDm/GkryaItM=;\n\th=From:To:Subject:Date:In-Reply-To:References:From;\n\tb=m8ntiktl0x+u0aXh6fvP+kl7VVgtfgdHIzIycEDjhW8p4SuoFM+m79jZI8YEslOuy\n\t5LgU15FSWQ+qpBfCMAG6Nm5IMyzLUle6JFb+lmv8KDs+ePEA3xPHujKh13y1VONr05\n\tZkbISKcSq22Q0JkuChCjeMZk2+7lEnzm6gPFx4yQ=","From":"Laurent Pinchart ","To":"libcamera-devel@lists.libcamera.org","Subject":"[PATCH 5/6] include: linux: Update to Linux v7.0","Date":"Mon, 4 May 2026 03:04:30 +0300","Message-ID":"<20260504000431.1340150-6-laurent.pinchart@ideasonboard.com>","X-Mailer":"git-send-email 2.53.0","In-Reply-To":"<20260504000431.1340150-1-laurent.pinchart@ideasonboard.com>","References":"<20260504000431.1340150-1-laurent.pinchart@ideasonboard.com>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","X-BeenThere":"libcamera-devel@lists.libcamera.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Errors-To":"libcamera-devel-bounces@lists.libcamera.org","Sender":"\"libcamera-devel\" "},"content":"The v7.0 kernel includes the Mali C55 driver. We were carrying a private\ncopy of the corresponding headers, updating to the mainline version\nensures that we test the latest API.\n\nThis update also imports two new headers, drm.h and drm_mode.h. They do\nnot contain SPDX license headers in the upstream kernel yet, which would\ncause a CI failure. Modify them manually until a patch fixing the issue\n([1]) gets merged upstream.\n\n[1] https://lore.kernel.org/dri-devel/20260407104951.1781047-1-laurent.pinchart+renesas@ideasonboard.com/\n\nSigned-off-by: Laurent Pinchart \n---\n include/linux/README | 2 +-\n include/linux/dma-buf.h | 1 +\n include/linux/drm.h | 1465 +++++++++++++++++++++++++++++++\n include/linux/drm_fourcc.h | 12 +-\n include/linux/drm_mode.h | 1535 +++++++++++++++++++++++++++++++++\n include/linux/rkisp1-config.h | 98 +--\n include/linux/stddef.h | 4 +\n include/linux/v4l2-controls.h | 69 ++\n include/linux/videodev2.h | 7 +-\n 9 files changed, 3101 insertions(+), 92 deletions(-)\n create mode 100644 include/linux/drm.h\n create mode 100644 include/linux/drm_mode.h","diff":"diff --git a/include/linux/README b/include/linux/README\nindex 98b7d150cf27..b02952bb28ca 100644\n--- a/include/linux/README\n+++ b/include/linux/README\n@@ -1,4 +1,4 @@\n # SPDX-License-Identifier: CC0-1.0\n \n-Files in this directory are imported from v6.18 of the Linux kernel. Do not\n+Files in this directory are imported from v7.0 of the Linux kernel. Do not\n modify them manually.\ndiff --git a/include/linux/dma-buf.h b/include/linux/dma-buf.h\nindex 5a6fda66d9ad..e827c9d20c5d 100644\n--- a/include/linux/dma-buf.h\n+++ b/include/linux/dma-buf.h\n@@ -20,6 +20,7 @@\n #ifndef _DMA_BUF_UAPI_H_\n #define _DMA_BUF_UAPI_H_\n \n+#include \n #include \n \n /**\ndiff --git a/include/linux/drm.h b/include/linux/drm.h\nnew file mode 100644\nindex 000000000000..5eecc8bed53d\n--- /dev/null\n+++ b/include/linux/drm.h\n@@ -0,0 +1,1465 @@\n+/* SPDX-License-Identifier: MIT */\n+/*\n+ * Header for the Direct Rendering Manager\n+ *\n+ * Author: Rickard E. (Rik) Faith \n+ *\n+ * Acknowledgments:\n+ * Dec 1999, Richard Henderson , move to generic cmpxchg.\n+ */\n+\n+/*\n+ * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.\n+ * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.\n+ * All rights reserved.\n+ */\n+\n+#ifndef _DRM_H_\n+#define _DRM_H_\n+\n+#if defined(__linux__)\n+\n+#include \n+#include \n+typedef unsigned int drm_handle_t;\n+\n+#else /* One of the BSDs */\n+\n+#include \n+#include \n+#include \n+typedef int8_t __s8;\n+typedef uint8_t __u8;\n+typedef int16_t __s16;\n+typedef uint16_t __u16;\n+typedef int32_t __s32;\n+typedef uint32_t __u32;\n+typedef int64_t __s64;\n+typedef uint64_t __u64;\n+typedef size_t __kernel_size_t;\n+typedef unsigned long drm_handle_t;\n+\n+#endif\n+\n+#if defined(__cplusplus)\n+extern \"C\" {\n+#endif\n+\n+#define DRM_NAME\t\"drm\"\t /**< Name in kernel, /dev, and /proc */\n+#define DRM_MIN_ORDER\t5\t /**< At least 2^5 bytes = 32 bytes */\n+#define DRM_MAX_ORDER\t22\t /**< Up to 2^22 bytes = 4MB */\n+#define DRM_RAM_PERCENT 10\t /**< How much system ram can we lock? */\n+\n+#define _DRM_LOCK_HELD\t0x80000000U /**< Hardware lock is held */\n+#define _DRM_LOCK_CONT\t0x40000000U /**< Hardware lock is contended */\n+#define _DRM_LOCK_IS_HELD(lock)\t ((lock) & _DRM_LOCK_HELD)\n+#define _DRM_LOCK_IS_CONT(lock)\t ((lock) & _DRM_LOCK_CONT)\n+#define _DRM_LOCKING_CONTEXT(lock) ((lock) & ~(_DRM_LOCK_HELD|_DRM_LOCK_CONT))\n+\n+typedef unsigned int drm_context_t;\n+typedef unsigned int drm_drawable_t;\n+typedef unsigned int drm_magic_t;\n+\n+/*\n+ * Cliprect.\n+ *\n+ * \\warning: If you change this structure, make sure you change\n+ * XF86DRIClipRectRec in the server as well\n+ *\n+ * \\note KW: Actually it's illegal to change either for\n+ * backwards-compatibility reasons.\n+ */\n+struct drm_clip_rect {\n+\tunsigned short x1;\n+\tunsigned short y1;\n+\tunsigned short x2;\n+\tunsigned short y2;\n+};\n+\n+/*\n+ * Drawable information.\n+ */\n+struct drm_drawable_info {\n+\tunsigned int num_rects;\n+\tstruct drm_clip_rect *rects;\n+};\n+\n+/*\n+ * Texture region,\n+ */\n+struct drm_tex_region {\n+\tunsigned char next;\n+\tunsigned char prev;\n+\tunsigned char in_use;\n+\tunsigned char padding;\n+\tunsigned int age;\n+};\n+\n+/*\n+ * Hardware lock.\n+ *\n+ * The lock structure is a simple cache-line aligned integer. To avoid\n+ * processor bus contention on a multiprocessor system, there should not be any\n+ * other data stored in the same cache line.\n+ */\n+struct drm_hw_lock {\n+\t__volatile__ unsigned int lock;\t\t/**< lock variable */\n+\tchar padding[60];\t\t\t/**< Pad to cache line */\n+};\n+\n+/*\n+ * DRM_IOCTL_VERSION ioctl argument type.\n+ *\n+ * \\sa drmGetVersion().\n+ */\n+struct drm_version {\n+\tint version_major;\t /**< Major version */\n+\tint version_minor;\t /**< Minor version */\n+\tint version_patchlevel;\t /**< Patch level */\n+\t__kernel_size_t name_len;\t /**< Length of name buffer */\n+\tchar *name;\t /**< Name of driver */\n+\t__kernel_size_t date_len;\t /**< Length of date buffer */\n+\tchar *date;\t /**< User-space buffer to hold date */\n+\t__kernel_size_t desc_len;\t /**< Length of desc buffer */\n+\tchar *desc;\t /**< User-space buffer to hold desc */\n+};\n+\n+/*\n+ * DRM_IOCTL_GET_UNIQUE ioctl argument type.\n+ *\n+ * \\sa drmGetBusid() and drmSetBusId().\n+ */\n+struct drm_unique {\n+\t__kernel_size_t unique_len;\t /**< Length of unique */\n+\tchar *unique;\t /**< Unique name for driver instantiation */\n+};\n+\n+struct drm_list {\n+\tint count;\t\t /**< Length of user-space structures */\n+\tstruct drm_version *version;\n+};\n+\n+struct drm_block {\n+\tint unused;\n+};\n+\n+/*\n+ * DRM_IOCTL_CONTROL ioctl argument type.\n+ *\n+ * \\sa drmCtlInstHandler() and drmCtlUninstHandler().\n+ */\n+struct drm_control {\n+\tenum {\n+\t\tDRM_ADD_COMMAND,\n+\t\tDRM_RM_COMMAND,\n+\t\tDRM_INST_HANDLER,\n+\t\tDRM_UNINST_HANDLER\n+\t} func;\n+\tint irq;\n+};\n+\n+/*\n+ * Type of memory to map.\n+ */\n+enum drm_map_type {\n+\t_DRM_FRAME_BUFFER = 0,\t /**< WC (no caching), no core dump */\n+\t_DRM_REGISTERS = 1,\t /**< no caching, no core dump */\n+\t_DRM_SHM = 2,\t\t /**< shared, cached */\n+\t_DRM_AGP = 3,\t\t /**< AGP/GART */\n+\t_DRM_SCATTER_GATHER = 4, /**< Scatter/gather memory for PCI DMA */\n+\t_DRM_CONSISTENT = 5\t /**< Consistent memory for PCI DMA */\n+};\n+\n+/*\n+ * Memory mapping flags.\n+ */\n+enum drm_map_flags {\n+\t_DRM_RESTRICTED = 0x01,\t /**< Cannot be mapped to user-virtual */\n+\t_DRM_READ_ONLY = 0x02,\n+\t_DRM_LOCKED = 0x04,\t /**< shared, cached, locked */\n+\t_DRM_KERNEL = 0x08,\t /**< kernel requires access */\n+\t_DRM_WRITE_COMBINING = 0x10, /**< use write-combining if available */\n+\t_DRM_CONTAINS_LOCK = 0x20, /**< SHM page that contains lock */\n+\t_DRM_REMOVABLE = 0x40,\t /**< Removable mapping */\n+\t_DRM_DRIVER = 0x80\t /**< Managed by driver */\n+};\n+\n+struct drm_ctx_priv_map {\n+\tunsigned int ctx_id;\t /**< Context requesting private mapping */\n+\tvoid *handle;\t\t /**< Handle of map */\n+};\n+\n+/*\n+ * DRM_IOCTL_GET_MAP, DRM_IOCTL_ADD_MAP and DRM_IOCTL_RM_MAP ioctls\n+ * argument type.\n+ *\n+ * \\sa drmAddMap().\n+ */\n+struct drm_map {\n+\tunsigned long offset;\t /**< Requested physical address (0 for SAREA)*/\n+\tunsigned long size;\t /**< Requested physical size (bytes) */\n+\tenum drm_map_type type;\t /**< Type of memory to map */\n+\tenum drm_map_flags flags;\t /**< Flags */\n+\tvoid *handle;\t\t /**< User-space: \"Handle\" to pass to mmap() */\n+\t\t\t\t /**< Kernel-space: kernel-virtual address */\n+\tint mtrr;\t\t /**< MTRR slot used */\n+\t/* Private data */\n+};\n+\n+/*\n+ * DRM_IOCTL_GET_CLIENT ioctl argument type.\n+ */\n+struct drm_client {\n+\tint idx;\t\t/**< Which client desired? */\n+\tint auth;\t\t/**< Is client authenticated? */\n+\tunsigned long pid;\t/**< Process ID */\n+\tunsigned long uid;\t/**< User ID */\n+\tunsigned long magic;\t/**< Magic */\n+\tunsigned long iocs;\t/**< Ioctl count */\n+};\n+\n+enum drm_stat_type {\n+\t_DRM_STAT_LOCK,\n+\t_DRM_STAT_OPENS,\n+\t_DRM_STAT_CLOSES,\n+\t_DRM_STAT_IOCTLS,\n+\t_DRM_STAT_LOCKS,\n+\t_DRM_STAT_UNLOCKS,\n+\t_DRM_STAT_VALUE,\t/**< Generic value */\n+\t_DRM_STAT_BYTE,\t\t/**< Generic byte counter (1024bytes/K) */\n+\t_DRM_STAT_COUNT,\t/**< Generic non-byte counter (1000/k) */\n+\n+\t_DRM_STAT_IRQ,\t\t/**< IRQ */\n+\t_DRM_STAT_PRIMARY,\t/**< Primary DMA bytes */\n+\t_DRM_STAT_SECONDARY,\t/**< Secondary DMA bytes */\n+\t_DRM_STAT_DMA,\t\t/**< DMA */\n+\t_DRM_STAT_SPECIAL,\t/**< Special DMA (e.g., priority or polled) */\n+\t_DRM_STAT_MISSED\t/**< Missed DMA opportunity */\n+\t /* Add to the *END* of the list */\n+};\n+\n+/*\n+ * DRM_IOCTL_GET_STATS ioctl argument type.\n+ */\n+struct drm_stats {\n+\tunsigned long count;\n+\tstruct {\n+\t\tunsigned long value;\n+\t\tenum drm_stat_type type;\n+\t} data[15];\n+};\n+\n+/*\n+ * Hardware locking flags.\n+ */\n+enum drm_lock_flags {\n+\t_DRM_LOCK_READY = 0x01,\t /**< Wait until hardware is ready for DMA */\n+\t_DRM_LOCK_QUIESCENT = 0x02, /**< Wait until hardware quiescent */\n+\t_DRM_LOCK_FLUSH = 0x04,\t /**< Flush this context's DMA queue first */\n+\t_DRM_LOCK_FLUSH_ALL = 0x08, /**< Flush all DMA queues first */\n+\t/* These *HALT* flags aren't supported yet\n+\t -- they will be used to support the\n+\t full-screen DGA-like mode. */\n+\t_DRM_HALT_ALL_QUEUES = 0x10, /**< Halt all current and future queues */\n+\t_DRM_HALT_CUR_QUEUES = 0x20 /**< Halt all current queues */\n+};\n+\n+/*\n+ * DRM_IOCTL_LOCK, DRM_IOCTL_UNLOCK and DRM_IOCTL_FINISH ioctl argument type.\n+ *\n+ * \\sa drmGetLock() and drmUnlock().\n+ */\n+struct drm_lock {\n+\tint context;\n+\tenum drm_lock_flags flags;\n+};\n+\n+/*\n+ * DMA flags\n+ *\n+ * \\warning\n+ * These values \\e must match xf86drm.h.\n+ *\n+ * \\sa drm_dma.\n+ */\n+enum drm_dma_flags {\n+\t/* Flags for DMA buffer dispatch */\n+\t_DRM_DMA_BLOCK = 0x01,\t /**<\n+\t\t\t\t * Block until buffer dispatched.\n+\t\t\t\t *\n+\t\t\t\t * \\note The buffer may not yet have\n+\t\t\t\t * been processed by the hardware --\n+\t\t\t\t * getting a hardware lock with the\n+\t\t\t\t * hardware quiescent will ensure\n+\t\t\t\t * that the buffer has been\n+\t\t\t\t * processed.\n+\t\t\t\t */\n+\t_DRM_DMA_WHILE_LOCKED = 0x02, /**< Dispatch while lock held */\n+\t_DRM_DMA_PRIORITY = 0x04, /**< High priority dispatch */\n+\n+\t/* Flags for DMA buffer request */\n+\t_DRM_DMA_WAIT = 0x10,\t /**< Wait for free buffers */\n+\t_DRM_DMA_SMALLER_OK = 0x20, /**< Smaller-than-requested buffers OK */\n+\t_DRM_DMA_LARGER_OK = 0x40 /**< Larger-than-requested buffers OK */\n+};\n+\n+/*\n+ * DRM_IOCTL_ADD_BUFS and DRM_IOCTL_MARK_BUFS ioctl argument type.\n+ *\n+ * \\sa drmAddBufs().\n+ */\n+struct drm_buf_desc {\n+\tint count;\t\t /**< Number of buffers of this size */\n+\tint size;\t\t /**< Size in bytes */\n+\tint low_mark;\t\t /**< Low water mark */\n+\tint high_mark;\t\t /**< High water mark */\n+\tenum {\n+\t\t_DRM_PAGE_ALIGN = 0x01,\t/**< Align on page boundaries for DMA */\n+\t\t_DRM_AGP_BUFFER = 0x02,\t/**< Buffer is in AGP space */\n+\t\t_DRM_SG_BUFFER = 0x04,\t/**< Scatter/gather memory buffer */\n+\t\t_DRM_FB_BUFFER = 0x08,\t/**< Buffer is in frame buffer */\n+\t\t_DRM_PCI_BUFFER_RO = 0x10 /**< Map PCI DMA buffer read-only */\n+\t} flags;\n+\tunsigned long agp_start; /**<\n+\t\t\t\t * Start address of where the AGP buffers are\n+\t\t\t\t * in the AGP aperture\n+\t\t\t\t */\n+};\n+\n+/*\n+ * DRM_IOCTL_INFO_BUFS ioctl argument type.\n+ */\n+struct drm_buf_info {\n+\tint count;\t\t/**< Entries in list */\n+\tstruct drm_buf_desc *list;\n+};\n+\n+/*\n+ * DRM_IOCTL_FREE_BUFS ioctl argument type.\n+ */\n+struct drm_buf_free {\n+\tint count;\n+\tint *list;\n+};\n+\n+/*\n+ * Buffer information\n+ *\n+ * \\sa drm_buf_map.\n+ */\n+struct drm_buf_pub {\n+\tint idx;\t\t /**< Index into the master buffer list */\n+\tint total;\t\t /**< Buffer size */\n+\tint used;\t\t /**< Amount of buffer in use (for DMA) */\n+\tvoid *address;\t /**< Address of buffer */\n+};\n+\n+/*\n+ * DRM_IOCTL_MAP_BUFS ioctl argument type.\n+ */\n+struct drm_buf_map {\n+\tint count;\t\t/**< Length of the buffer list */\n+#ifdef __cplusplus\n+\tvoid *virt;\n+#else\n+\tvoid *virtual;\t\t/**< Mmap'd area in user-virtual */\n+#endif\n+\tstruct drm_buf_pub *list;\t/**< Buffer information */\n+};\n+\n+/*\n+ * DRM_IOCTL_DMA ioctl argument type.\n+ *\n+ * Indices here refer to the offset into the buffer list in drm_buf_get.\n+ *\n+ * \\sa drmDMA().\n+ */\n+struct drm_dma {\n+\tint context;\t\t\t /**< Context handle */\n+\tint send_count;\t\t\t /**< Number of buffers to send */\n+\tint *send_indices;\t /**< List of handles to buffers */\n+\tint *send_sizes;\t\t /**< Lengths of data to send */\n+\tenum drm_dma_flags flags;\t /**< Flags */\n+\tint request_count;\t\t /**< Number of buffers requested */\n+\tint request_size;\t\t /**< Desired size for buffers */\n+\tint *request_indices;\t /**< Buffer information */\n+\tint *request_sizes;\n+\tint granted_count;\t\t /**< Number of buffers granted */\n+};\n+\n+enum drm_ctx_flags {\n+\t_DRM_CONTEXT_PRESERVED = 0x01,\n+\t_DRM_CONTEXT_2DONLY = 0x02\n+};\n+\n+/*\n+ * DRM_IOCTL_ADD_CTX ioctl argument type.\n+ *\n+ * \\sa drmCreateContext() and drmDestroyContext().\n+ */\n+struct drm_ctx {\n+\tdrm_context_t handle;\n+\tenum drm_ctx_flags flags;\n+};\n+\n+/*\n+ * DRM_IOCTL_RES_CTX ioctl argument type.\n+ */\n+struct drm_ctx_res {\n+\tint count;\n+\tstruct drm_ctx *contexts;\n+};\n+\n+/*\n+ * DRM_IOCTL_ADD_DRAW and DRM_IOCTL_RM_DRAW ioctl argument type.\n+ */\n+struct drm_draw {\n+\tdrm_drawable_t handle;\n+};\n+\n+/*\n+ * DRM_IOCTL_UPDATE_DRAW ioctl argument type.\n+ */\n+typedef enum {\n+\tDRM_DRAWABLE_CLIPRECTS\n+} drm_drawable_info_type_t;\n+\n+struct drm_update_draw {\n+\tdrm_drawable_t handle;\n+\tunsigned int type;\n+\tunsigned int num;\n+\tunsigned long long data;\n+};\n+\n+/*\n+ * DRM_IOCTL_GET_MAGIC and DRM_IOCTL_AUTH_MAGIC ioctl argument type.\n+ */\n+struct drm_auth {\n+\tdrm_magic_t magic;\n+};\n+\n+/*\n+ * DRM_IOCTL_IRQ_BUSID ioctl argument type.\n+ *\n+ * \\sa drmGetInterruptFromBusID().\n+ */\n+struct drm_irq_busid {\n+\tint irq;\t/**< IRQ number */\n+\tint busnum;\t/**< bus number */\n+\tint devnum;\t/**< device number */\n+\tint funcnum;\t/**< function number */\n+};\n+\n+enum drm_vblank_seq_type {\n+\t_DRM_VBLANK_ABSOLUTE = 0x0,\t/**< Wait for specific vblank sequence number */\n+\t_DRM_VBLANK_RELATIVE = 0x1,\t/**< Wait for given number of vblanks */\n+\t/* bits 1-6 are reserved for high crtcs */\n+\t_DRM_VBLANK_HIGH_CRTC_MASK = 0x0000003e,\n+\t_DRM_VBLANK_EVENT = 0x4000000, /**< Send event instead of blocking */\n+\t_DRM_VBLANK_FLIP = 0x8000000, /**< Scheduled buffer swap should flip */\n+\t_DRM_VBLANK_NEXTONMISS = 0x10000000,\t/**< If missed, wait for next vblank */\n+\t_DRM_VBLANK_SECONDARY = 0x20000000,\t/**< Secondary display controller */\n+\t_DRM_VBLANK_SIGNAL = 0x40000000\t/**< Send signal instead of blocking, unsupported */\n+};\n+#define _DRM_VBLANK_HIGH_CRTC_SHIFT 1\n+\n+#define _DRM_VBLANK_TYPES_MASK (_DRM_VBLANK_ABSOLUTE | _DRM_VBLANK_RELATIVE)\n+#define _DRM_VBLANK_FLAGS_MASK (_DRM_VBLANK_EVENT | _DRM_VBLANK_SIGNAL | \\\n+\t\t\t\t_DRM_VBLANK_SECONDARY | _DRM_VBLANK_NEXTONMISS)\n+\n+struct drm_wait_vblank_request {\n+\tenum drm_vblank_seq_type type;\n+\tunsigned int sequence;\n+\tunsigned long signal;\n+};\n+\n+struct drm_wait_vblank_reply {\n+\tenum drm_vblank_seq_type type;\n+\tunsigned int sequence;\n+\tlong tval_sec;\n+\tlong tval_usec;\n+};\n+\n+/*\n+ * DRM_IOCTL_WAIT_VBLANK ioctl argument type.\n+ *\n+ * \\sa drmWaitVBlank().\n+ */\n+union drm_wait_vblank {\n+\tstruct drm_wait_vblank_request request;\n+\tstruct drm_wait_vblank_reply reply;\n+};\n+\n+#define _DRM_PRE_MODESET 1\n+#define _DRM_POST_MODESET 2\n+\n+/*\n+ * DRM_IOCTL_MODESET_CTL ioctl argument type\n+ *\n+ * \\sa drmModesetCtl().\n+ */\n+struct drm_modeset_ctl {\n+\t__u32 crtc;\n+\t__u32 cmd;\n+};\n+\n+/*\n+ * DRM_IOCTL_AGP_ENABLE ioctl argument type.\n+ *\n+ * \\sa drmAgpEnable().\n+ */\n+struct drm_agp_mode {\n+\tunsigned long mode;\t/**< AGP mode */\n+};\n+\n+/*\n+ * DRM_IOCTL_AGP_ALLOC and DRM_IOCTL_AGP_FREE ioctls argument type.\n+ *\n+ * \\sa drmAgpAlloc() and drmAgpFree().\n+ */\n+struct drm_agp_buffer {\n+\tunsigned long size;\t/**< In bytes -- will round to page boundary */\n+\tunsigned long handle;\t/**< Used for binding / unbinding */\n+\tunsigned long type;\t/**< Type of memory to allocate */\n+\tunsigned long physical;\t/**< Physical used by i810 */\n+};\n+\n+/*\n+ * DRM_IOCTL_AGP_BIND and DRM_IOCTL_AGP_UNBIND ioctls argument type.\n+ *\n+ * \\sa drmAgpBind() and drmAgpUnbind().\n+ */\n+struct drm_agp_binding {\n+\tunsigned long handle;\t/**< From drm_agp_buffer */\n+\tunsigned long offset;\t/**< In bytes -- will round to page boundary */\n+};\n+\n+/*\n+ * DRM_IOCTL_AGP_INFO ioctl argument type.\n+ *\n+ * \\sa drmAgpVersionMajor(), drmAgpVersionMinor(), drmAgpGetMode(),\n+ * drmAgpBase(), drmAgpSize(), drmAgpMemoryUsed(), drmAgpMemoryAvail(),\n+ * drmAgpVendorId() and drmAgpDeviceId().\n+ */\n+struct drm_agp_info {\n+\tint agp_version_major;\n+\tint agp_version_minor;\n+\tunsigned long mode;\n+\tunsigned long aperture_base;\t/* physical address */\n+\tunsigned long aperture_size;\t/* bytes */\n+\tunsigned long memory_allowed;\t/* bytes */\n+\tunsigned long memory_used;\n+\n+\t/* PCI information */\n+\tunsigned short id_vendor;\n+\tunsigned short id_device;\n+};\n+\n+/*\n+ * DRM_IOCTL_SG_ALLOC ioctl argument type.\n+ */\n+struct drm_scatter_gather {\n+\tunsigned long size;\t/**< In bytes -- will round to page boundary */\n+\tunsigned long handle;\t/**< Used for mapping / unmapping */\n+};\n+\n+/*\n+ * DRM_IOCTL_SET_VERSION ioctl argument type.\n+ */\n+struct drm_set_version {\n+\tint drm_di_major;\n+\tint drm_di_minor;\n+\tint drm_dd_major;\n+\tint drm_dd_minor;\n+};\n+\n+/**\n+ * struct drm_gem_close - Argument for &DRM_IOCTL_GEM_CLOSE ioctl.\n+ * @handle: Handle of the object to be closed.\n+ * @pad: Padding.\n+ *\n+ * Releases the handle to an mm object.\n+ */\n+struct drm_gem_close {\n+\t__u32 handle;\n+\t__u32 pad;\n+};\n+\n+/**\n+ * struct drm_gem_flink - Argument for &DRM_IOCTL_GEM_FLINK ioctl.\n+ * @handle: Handle for the object being named.\n+ * @name: Returned global name.\n+ *\n+ * Create a global name for an object, returning the name.\n+ *\n+ * Note that the name does not hold a reference; when the object\n+ * is freed, the name goes away.\n+ */\n+struct drm_gem_flink {\n+\t__u32 handle;\n+\t__u32 name;\n+};\n+\n+/**\n+ * struct drm_gem_open - Argument for &DRM_IOCTL_GEM_OPEN ioctl.\n+ * @name: Name of object being opened.\n+ * @handle: Returned handle for the object.\n+ * @size: Returned size of the object\n+ *\n+ * Open an object using the global name, returning a handle and the size.\n+ *\n+ * This handle (of course) holds a reference to the object, so the object\n+ * will not go away until the handle is deleted.\n+ */\n+struct drm_gem_open {\n+\t__u32 name;\n+\t__u32 handle;\n+\t__u64 size;\n+};\n+\n+/**\n+ * struct drm_gem_change_handle - Argument for &DRM_IOCTL_GEM_CHANGE_HANDLE ioctl.\n+ * @handle: The handle of a gem object.\n+ * @new_handle: An available gem handle.\n+ *\n+ * This ioctl changes the handle of a GEM object to the specified one.\n+ * The new handle must be unused. On success the old handle is closed\n+ * and all further IOCTL should refer to the new handle only.\n+ * Calls to DRM_IOCTL_PRIME_FD_TO_HANDLE will return the new handle.\n+ */\n+struct drm_gem_change_handle {\n+\t__u32 handle;\n+\t__u32 new_handle;\n+};\n+\n+/**\n+ * DRM_CAP_DUMB_BUFFER\n+ *\n+ * If set to 1, the driver supports creating dumb buffers via the\n+ * &DRM_IOCTL_MODE_CREATE_DUMB ioctl.\n+ */\n+#define DRM_CAP_DUMB_BUFFER\t\t0x1\n+/**\n+ * DRM_CAP_VBLANK_HIGH_CRTC\n+ *\n+ * If set to 1, the kernel supports specifying a :ref:`CRTC index`\n+ * in the high bits of &drm_wait_vblank_request.type.\n+ *\n+ * Starting kernel version 2.6.39, this capability is always set to 1.\n+ */\n+#define DRM_CAP_VBLANK_HIGH_CRTC\t0x2\n+/**\n+ * DRM_CAP_DUMB_PREFERRED_DEPTH\n+ *\n+ * The preferred bit depth for dumb buffers.\n+ *\n+ * The bit depth is the number of bits used to indicate the color of a single\n+ * pixel excluding any padding. This is different from the number of bits per\n+ * pixel. For instance, XRGB8888 has a bit depth of 24 but has 32 bits per\n+ * pixel.\n+ *\n+ * Note that this preference only applies to dumb buffers, it's irrelevant for\n+ * other types of buffers.\n+ */\n+#define DRM_CAP_DUMB_PREFERRED_DEPTH\t0x3\n+/**\n+ * DRM_CAP_DUMB_PREFER_SHADOW\n+ *\n+ * If set to 1, the driver prefers userspace to render to a shadow buffer\n+ * instead of directly rendering to a dumb buffer. For best speed, userspace\n+ * should do streaming ordered memory copies into the dumb buffer and never\n+ * read from it.\n+ *\n+ * Note that this preference only applies to dumb buffers, it's irrelevant for\n+ * other types of buffers.\n+ */\n+#define DRM_CAP_DUMB_PREFER_SHADOW\t0x4\n+/**\n+ * DRM_CAP_PRIME\n+ *\n+ * Bitfield of supported PRIME sharing capabilities. See &DRM_PRIME_CAP_IMPORT\n+ * and &DRM_PRIME_CAP_EXPORT.\n+ *\n+ * Starting from kernel version 6.6, both &DRM_PRIME_CAP_IMPORT and\n+ * &DRM_PRIME_CAP_EXPORT are always advertised.\n+ *\n+ * PRIME buffers are exposed as dma-buf file descriptors.\n+ * See :ref:`prime_buffer_sharing`.\n+ */\n+#define DRM_CAP_PRIME\t\t\t0x5\n+/**\n+ * DRM_PRIME_CAP_IMPORT\n+ *\n+ * If this bit is set in &DRM_CAP_PRIME, the driver supports importing PRIME\n+ * buffers via the &DRM_IOCTL_PRIME_FD_TO_HANDLE ioctl.\n+ *\n+ * Starting from kernel version 6.6, this bit is always set in &DRM_CAP_PRIME.\n+ */\n+#define DRM_PRIME_CAP_IMPORT\t\t0x1\n+/**\n+ * DRM_PRIME_CAP_EXPORT\n+ *\n+ * If this bit is set in &DRM_CAP_PRIME, the driver supports exporting PRIME\n+ * buffers via the &DRM_IOCTL_PRIME_HANDLE_TO_FD ioctl.\n+ *\n+ * Starting from kernel version 6.6, this bit is always set in &DRM_CAP_PRIME.\n+ */\n+#define DRM_PRIME_CAP_EXPORT\t\t0x2\n+/**\n+ * DRM_CAP_TIMESTAMP_MONOTONIC\n+ *\n+ * If set to 0, the kernel will report timestamps with ``CLOCK_REALTIME`` in\n+ * struct drm_event_vblank. If set to 1, the kernel will report timestamps with\n+ * ``CLOCK_MONOTONIC``. See ``clock_gettime(2)`` for the definition of these\n+ * clocks.\n+ *\n+ * Starting from kernel version 2.6.39, the default value for this capability\n+ * is 1. Starting kernel version 4.15, this capability is always set to 1.\n+ */\n+#define DRM_CAP_TIMESTAMP_MONOTONIC\t0x6\n+/**\n+ * DRM_CAP_ASYNC_PAGE_FLIP\n+ *\n+ * If set to 1, the driver supports &DRM_MODE_PAGE_FLIP_ASYNC for legacy\n+ * page-flips.\n+ */\n+#define DRM_CAP_ASYNC_PAGE_FLIP\t\t0x7\n+/**\n+ * DRM_CAP_CURSOR_WIDTH\n+ *\n+ * The ``CURSOR_WIDTH`` and ``CURSOR_HEIGHT`` capabilities return a valid\n+ * width x height combination for the hardware cursor. The intention is that a\n+ * hardware agnostic userspace can query a cursor plane size to use.\n+ *\n+ * Note that the cross-driver contract is to merely return a valid size;\n+ * drivers are free to attach another meaning on top, eg. i915 returns the\n+ * maximum plane size.\n+ */\n+#define DRM_CAP_CURSOR_WIDTH\t\t0x8\n+/**\n+ * DRM_CAP_CURSOR_HEIGHT\n+ *\n+ * See &DRM_CAP_CURSOR_WIDTH.\n+ */\n+#define DRM_CAP_CURSOR_HEIGHT\t\t0x9\n+/**\n+ * DRM_CAP_ADDFB2_MODIFIERS\n+ *\n+ * If set to 1, the driver supports supplying modifiers in the\n+ * &DRM_IOCTL_MODE_ADDFB2 ioctl.\n+ */\n+#define DRM_CAP_ADDFB2_MODIFIERS\t0x10\n+/**\n+ * DRM_CAP_PAGE_FLIP_TARGET\n+ *\n+ * If set to 1, the driver supports the &DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE and\n+ * &DRM_MODE_PAGE_FLIP_TARGET_RELATIVE flags in\n+ * &drm_mode_crtc_page_flip_target.flags for the &DRM_IOCTL_MODE_PAGE_FLIP\n+ * ioctl.\n+ */\n+#define DRM_CAP_PAGE_FLIP_TARGET\t0x11\n+/**\n+ * DRM_CAP_CRTC_IN_VBLANK_EVENT\n+ *\n+ * If set to 1, the kernel supports reporting the CRTC ID in\n+ * &drm_event_vblank.crtc_id for the &DRM_EVENT_VBLANK and\n+ * &DRM_EVENT_FLIP_COMPLETE events.\n+ *\n+ * Starting kernel version 4.12, this capability is always set to 1.\n+ */\n+#define DRM_CAP_CRTC_IN_VBLANK_EVENT\t0x12\n+/**\n+ * DRM_CAP_SYNCOBJ\n+ *\n+ * If set to 1, the driver supports sync objects. See :ref:`drm_sync_objects`.\n+ */\n+#define DRM_CAP_SYNCOBJ\t\t0x13\n+/**\n+ * DRM_CAP_SYNCOBJ_TIMELINE\n+ *\n+ * If set to 1, the driver supports timeline operations on sync objects. See\n+ * :ref:`drm_sync_objects`.\n+ */\n+#define DRM_CAP_SYNCOBJ_TIMELINE\t0x14\n+/**\n+ * DRM_CAP_ATOMIC_ASYNC_PAGE_FLIP\n+ *\n+ * If set to 1, the driver supports &DRM_MODE_PAGE_FLIP_ASYNC for atomic\n+ * commits.\n+ */\n+#define DRM_CAP_ATOMIC_ASYNC_PAGE_FLIP\t0x15\n+\n+/* DRM_IOCTL_GET_CAP ioctl argument type */\n+struct drm_get_cap {\n+\t__u64 capability;\n+\t__u64 value;\n+};\n+\n+/**\n+ * DRM_CLIENT_CAP_STEREO_3D\n+ *\n+ * If set to 1, the DRM core will expose the stereo 3D capabilities of the\n+ * monitor by advertising the supported 3D layouts in the flags of struct\n+ * drm_mode_modeinfo. See ``DRM_MODE_FLAG_3D_*``.\n+ *\n+ * This capability is always supported for all drivers starting from kernel\n+ * version 3.13.\n+ */\n+#define DRM_CLIENT_CAP_STEREO_3D\t1\n+\n+/**\n+ * DRM_CLIENT_CAP_UNIVERSAL_PLANES\n+ *\n+ * If set to 1, the DRM core will expose all planes (overlay, primary, and\n+ * cursor) to userspace.\n+ *\n+ * This capability has been introduced in kernel version 3.15. Starting from\n+ * kernel version 3.17, this capability is always supported for all drivers.\n+ */\n+#define DRM_CLIENT_CAP_UNIVERSAL_PLANES 2\n+\n+/**\n+ * DRM_CLIENT_CAP_ATOMIC\n+ *\n+ * If set to 1, the DRM core will expose atomic properties to userspace. This\n+ * implicitly enables &DRM_CLIENT_CAP_UNIVERSAL_PLANES and\n+ * &DRM_CLIENT_CAP_ASPECT_RATIO.\n+ *\n+ * If the driver doesn't support atomic mode-setting, enabling this capability\n+ * will fail with -EOPNOTSUPP.\n+ *\n+ * This capability has been introduced in kernel version 4.0. Starting from\n+ * kernel version 4.2, this capability is always supported for atomic-capable\n+ * drivers.\n+ */\n+#define DRM_CLIENT_CAP_ATOMIC\t3\n+\n+/**\n+ * DRM_CLIENT_CAP_ASPECT_RATIO\n+ *\n+ * If set to 1, the DRM core will provide aspect ratio information in modes.\n+ * See ``DRM_MODE_FLAG_PIC_AR_*``.\n+ *\n+ * This capability is always supported for all drivers starting from kernel\n+ * version 4.18.\n+ */\n+#define DRM_CLIENT_CAP_ASPECT_RATIO 4\n+\n+/**\n+ * DRM_CLIENT_CAP_WRITEBACK_CONNECTORS\n+ *\n+ * If set to 1, the DRM core will expose special connectors to be used for\n+ * writing back to memory the scene setup in the commit. The client must enable\n+ * &DRM_CLIENT_CAP_ATOMIC first.\n+ *\n+ * This capability is always supported for atomic-capable drivers starting from\n+ * kernel version 4.19.\n+ */\n+#define DRM_CLIENT_CAP_WRITEBACK_CONNECTORS\t5\n+\n+/**\n+ * DRM_CLIENT_CAP_CURSOR_PLANE_HOTSPOT\n+ *\n+ * Drivers for para-virtualized hardware (e.g. vmwgfx, qxl, virtio and\n+ * virtualbox) have additional restrictions for cursor planes (thus\n+ * making cursor planes on those drivers not truly universal,) e.g.\n+ * they need cursor planes to act like one would expect from a mouse\n+ * cursor and have correctly set hotspot properties.\n+ * If this client cap is not set the DRM core will hide cursor plane on\n+ * those virtualized drivers because not setting it implies that the\n+ * client is not capable of dealing with those extra restictions.\n+ * Clients which do set cursor hotspot and treat the cursor plane\n+ * like a mouse cursor should set this property.\n+ * The client must enable &DRM_CLIENT_CAP_ATOMIC first.\n+ *\n+ * Setting this property on drivers which do not special case\n+ * cursor planes (i.e. non-virtualized drivers) will return\n+ * EOPNOTSUPP, which can be used by userspace to gauge\n+ * requirements of the hardware/drivers they're running on.\n+ *\n+ * This capability is always supported for atomic-capable virtualized\n+ * drivers starting from kernel version 6.6.\n+ */\n+#define DRM_CLIENT_CAP_CURSOR_PLANE_HOTSPOT\t6\n+\n+/**\n+ * DRM_CLIENT_CAP_PLANE_COLOR_PIPELINE\n+ *\n+ * If set to 1 the DRM core will allow setting the COLOR_PIPELINE\n+ * property on a &drm_plane, as well as drm_colorop properties.\n+ *\n+ * Setting of these plane properties will be rejected when this client\n+ * cap is set:\n+ * - COLOR_ENCODING\n+ * - COLOR_RANGE\n+ *\n+ * The client must enable &DRM_CLIENT_CAP_ATOMIC first.\n+ */\n+#define DRM_CLIENT_CAP_PLANE_COLOR_PIPELINE\t7\n+\n+/* DRM_IOCTL_SET_CLIENT_CAP ioctl argument type */\n+struct drm_set_client_cap {\n+\t__u64 capability;\n+\t__u64 value;\n+};\n+\n+#define DRM_RDWR O_RDWR\n+#define DRM_CLOEXEC O_CLOEXEC\n+struct drm_prime_handle {\n+\t__u32 handle;\n+\n+\t/** Flags.. only applicable for handle->fd */\n+\t__u32 flags;\n+\n+\t/** Returned dmabuf file descriptor */\n+\t__s32 fd;\n+};\n+\n+struct drm_syncobj_create {\n+\t__u32 handle;\n+#define DRM_SYNCOBJ_CREATE_SIGNALED (1 << 0)\n+\t__u32 flags;\n+};\n+\n+struct drm_syncobj_destroy {\n+\t__u32 handle;\n+\t__u32 pad;\n+};\n+\n+#define DRM_SYNCOBJ_FD_TO_HANDLE_FLAGS_IMPORT_SYNC_FILE (1 << 0)\n+#define DRM_SYNCOBJ_FD_TO_HANDLE_FLAGS_TIMELINE (1 << 1)\n+#define DRM_SYNCOBJ_HANDLE_TO_FD_FLAGS_EXPORT_SYNC_FILE (1 << 0)\n+#define DRM_SYNCOBJ_HANDLE_TO_FD_FLAGS_TIMELINE (1 << 1)\n+struct drm_syncobj_handle {\n+\t__u32 handle;\n+\t__u32 flags;\n+\n+\t__s32 fd;\n+\t__u32 pad;\n+\n+\t__u64 point;\n+};\n+\n+struct drm_syncobj_transfer {\n+\t__u32 src_handle;\n+\t__u32 dst_handle;\n+\t__u64 src_point;\n+\t__u64 dst_point;\n+\t__u32 flags;\n+\t__u32 pad;\n+};\n+\n+#define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL (1 << 0)\n+#define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT (1 << 1)\n+#define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_AVAILABLE (1 << 2) /* wait for time point to become available */\n+#define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_DEADLINE (1 << 3) /* set fence deadline to deadline_nsec */\n+struct drm_syncobj_wait {\n+\t__u64 handles;\n+\t/* absolute timeout */\n+\t__s64 timeout_nsec;\n+\t__u32 count_handles;\n+\t__u32 flags;\n+\t__u32 first_signaled; /* only valid when not waiting all */\n+\t__u32 pad;\n+\t/**\n+\t * @deadline_nsec - fence deadline hint\n+\t *\n+\t * Deadline hint, in absolute CLOCK_MONOTONIC, to set on backing\n+\t * fence(s) if the DRM_SYNCOBJ_WAIT_FLAGS_WAIT_DEADLINE flag is\n+\t * set.\n+\t */\n+\t__u64 deadline_nsec;\n+};\n+\n+struct drm_syncobj_timeline_wait {\n+\t__u64 handles;\n+\t/* wait on specific timeline point for every handles*/\n+\t__u64 points;\n+\t/* absolute timeout */\n+\t__s64 timeout_nsec;\n+\t__u32 count_handles;\n+\t__u32 flags;\n+\t__u32 first_signaled; /* only valid when not waiting all */\n+\t__u32 pad;\n+\t/**\n+\t * @deadline_nsec - fence deadline hint\n+\t *\n+\t * Deadline hint, in absolute CLOCK_MONOTONIC, to set on backing\n+\t * fence(s) if the DRM_SYNCOBJ_WAIT_FLAGS_WAIT_DEADLINE flag is\n+\t * set.\n+\t */\n+\t__u64 deadline_nsec;\n+};\n+\n+/**\n+ * struct drm_syncobj_eventfd\n+ * @handle: syncobj handle.\n+ * @flags: Zero to wait for the point to be signalled, or\n+ * &DRM_SYNCOBJ_WAIT_FLAGS_WAIT_AVAILABLE to wait for a fence to be\n+ * available for the point.\n+ * @point: syncobj timeline point (set to zero for binary syncobjs).\n+ * @fd: Existing eventfd to sent events to.\n+ * @pad: Must be zero.\n+ *\n+ * Register an eventfd to be signalled by a syncobj. The eventfd counter will\n+ * be incremented by one.\n+ */\n+struct drm_syncobj_eventfd {\n+\t__u32 handle;\n+\t__u32 flags;\n+\t__u64 point;\n+\t__s32 fd;\n+\t__u32 pad;\n+};\n+\n+\n+struct drm_syncobj_array {\n+\t__u64 handles;\n+\t__u32 count_handles;\n+\t__u32 pad;\n+};\n+\n+#define DRM_SYNCOBJ_QUERY_FLAGS_LAST_SUBMITTED (1 << 0) /* last available point on timeline syncobj */\n+struct drm_syncobj_timeline_array {\n+\t__u64 handles;\n+\t__u64 points;\n+\t__u32 count_handles;\n+\t__u32 flags;\n+};\n+\n+\n+/* Query current scanout sequence number */\n+struct drm_crtc_get_sequence {\n+\t__u32 crtc_id;\t\t/* requested crtc_id */\n+\t__u32 active;\t\t/* return: crtc output is active */\n+\t__u64 sequence;\t\t/* return: most recent vblank sequence */\n+\t__s64 sequence_ns;\t/* return: most recent time of first pixel out */\n+};\n+\n+/* Queue event to be delivered at specified sequence. Time stamp marks\n+ * when the first pixel of the refresh cycle leaves the display engine\n+ * for the display\n+ */\n+#define DRM_CRTC_SEQUENCE_RELATIVE\t\t0x00000001\t/* sequence is relative to current */\n+#define DRM_CRTC_SEQUENCE_NEXT_ON_MISS\t\t0x00000002\t/* Use next sequence if we've missed */\n+\n+struct drm_crtc_queue_sequence {\n+\t__u32 crtc_id;\n+\t__u32 flags;\n+\t__u64 sequence;\t\t/* on input, target sequence. on output, actual sequence */\n+\t__u64 user_data;\t/* user data passed to event */\n+};\n+\n+#define DRM_CLIENT_NAME_MAX_LEN\t\t64\n+struct drm_set_client_name {\n+\t__u64 name_len;\n+\t__u64 name;\n+};\n+\n+\n+#if defined(__cplusplus)\n+}\n+#endif\n+\n+#include \"drm_mode.h\"\n+\n+#if defined(__cplusplus)\n+extern \"C\" {\n+#endif\n+\n+#define DRM_IOCTL_BASE\t\t\t'd'\n+#define DRM_IO(nr)\t\t\t_IO(DRM_IOCTL_BASE,nr)\n+#define DRM_IOR(nr,type)\t\t_IOR(DRM_IOCTL_BASE,nr,type)\n+#define DRM_IOW(nr,type)\t\t_IOW(DRM_IOCTL_BASE,nr,type)\n+#define DRM_IOWR(nr,type)\t\t_IOWR(DRM_IOCTL_BASE,nr,type)\n+\n+#define DRM_IOCTL_VERSION\t\tDRM_IOWR(0x00, struct drm_version)\n+#define DRM_IOCTL_GET_UNIQUE\t\tDRM_IOWR(0x01, struct drm_unique)\n+#define DRM_IOCTL_GET_MAGIC\t\tDRM_IOR( 0x02, struct drm_auth)\n+#define DRM_IOCTL_IRQ_BUSID\t\tDRM_IOWR(0x03, struct drm_irq_busid)\n+#define DRM_IOCTL_GET_MAP DRM_IOWR(0x04, struct drm_map)\n+#define DRM_IOCTL_GET_CLIENT DRM_IOWR(0x05, struct drm_client)\n+#define DRM_IOCTL_GET_STATS DRM_IOR( 0x06, struct drm_stats)\n+#define DRM_IOCTL_SET_VERSION\t\tDRM_IOWR(0x07, struct drm_set_version)\n+#define DRM_IOCTL_MODESET_CTL DRM_IOW(0x08, struct drm_modeset_ctl)\n+/**\n+ * DRM_IOCTL_GEM_CLOSE - Close a GEM handle.\n+ *\n+ * GEM handles are not reference-counted by the kernel. User-space is\n+ * responsible for managing their lifetime. For example, if user-space imports\n+ * the same memory object twice on the same DRM file description, the same GEM\n+ * handle is returned by both imports, and user-space needs to ensure\n+ * &DRM_IOCTL_GEM_CLOSE is performed once only. The same situation can happen\n+ * when a memory object is allocated, then exported and imported again on the\n+ * same DRM file description. The &DRM_IOCTL_MODE_GETFB2 IOCTL is an exception\n+ * and always returns fresh new GEM handles even if an existing GEM handle\n+ * already refers to the same memory object before the IOCTL is performed.\n+ */\n+#define DRM_IOCTL_GEM_CLOSE\t\tDRM_IOW (0x09, struct drm_gem_close)\n+#define DRM_IOCTL_GEM_FLINK\t\tDRM_IOWR(0x0a, struct drm_gem_flink)\n+#define DRM_IOCTL_GEM_OPEN\t\tDRM_IOWR(0x0b, struct drm_gem_open)\n+#define DRM_IOCTL_GET_CAP\t\tDRM_IOWR(0x0c, struct drm_get_cap)\n+#define DRM_IOCTL_SET_CLIENT_CAP\tDRM_IOW( 0x0d, struct drm_set_client_cap)\n+\n+#define DRM_IOCTL_SET_UNIQUE\t\tDRM_IOW( 0x10, struct drm_unique)\n+#define DRM_IOCTL_AUTH_MAGIC\t\tDRM_IOW( 0x11, struct drm_auth)\n+#define DRM_IOCTL_BLOCK\t\t\tDRM_IOWR(0x12, struct drm_block)\n+#define DRM_IOCTL_UNBLOCK\t\tDRM_IOWR(0x13, struct drm_block)\n+#define DRM_IOCTL_CONTROL\t\tDRM_IOW( 0x14, struct drm_control)\n+#define DRM_IOCTL_ADD_MAP\t\tDRM_IOWR(0x15, struct drm_map)\n+#define DRM_IOCTL_ADD_BUFS\t\tDRM_IOWR(0x16, struct drm_buf_desc)\n+#define DRM_IOCTL_MARK_BUFS\t\tDRM_IOW( 0x17, struct drm_buf_desc)\n+#define DRM_IOCTL_INFO_BUFS\t\tDRM_IOWR(0x18, struct drm_buf_info)\n+#define DRM_IOCTL_MAP_BUFS\t\tDRM_IOWR(0x19, struct drm_buf_map)\n+#define DRM_IOCTL_FREE_BUFS\t\tDRM_IOW( 0x1a, struct drm_buf_free)\n+\n+#define DRM_IOCTL_RM_MAP\t\tDRM_IOW( 0x1b, struct drm_map)\n+\n+#define DRM_IOCTL_SET_SAREA_CTX\t\tDRM_IOW( 0x1c, struct drm_ctx_priv_map)\n+#define DRM_IOCTL_GET_SAREA_CTX \tDRM_IOWR(0x1d, struct drm_ctx_priv_map)\n+\n+#define DRM_IOCTL_SET_MASTER DRM_IO(0x1e)\n+#define DRM_IOCTL_DROP_MASTER DRM_IO(0x1f)\n+\n+#define DRM_IOCTL_ADD_CTX\t\tDRM_IOWR(0x20, struct drm_ctx)\n+#define DRM_IOCTL_RM_CTX\t\tDRM_IOWR(0x21, struct drm_ctx)\n+#define DRM_IOCTL_MOD_CTX\t\tDRM_IOW( 0x22, struct drm_ctx)\n+#define DRM_IOCTL_GET_CTX\t\tDRM_IOWR(0x23, struct drm_ctx)\n+#define DRM_IOCTL_SWITCH_CTX\t\tDRM_IOW( 0x24, struct drm_ctx)\n+#define DRM_IOCTL_NEW_CTX\t\tDRM_IOW( 0x25, struct drm_ctx)\n+#define DRM_IOCTL_RES_CTX\t\tDRM_IOWR(0x26, struct drm_ctx_res)\n+#define DRM_IOCTL_ADD_DRAW\t\tDRM_IOWR(0x27, struct drm_draw)\n+#define DRM_IOCTL_RM_DRAW\t\tDRM_IOWR(0x28, struct drm_draw)\n+#define DRM_IOCTL_DMA\t\t\tDRM_IOWR(0x29, struct drm_dma)\n+#define DRM_IOCTL_LOCK\t\t\tDRM_IOW( 0x2a, struct drm_lock)\n+#define DRM_IOCTL_UNLOCK\t\tDRM_IOW( 0x2b, struct drm_lock)\n+#define DRM_IOCTL_FINISH\t\tDRM_IOW( 0x2c, struct drm_lock)\n+\n+/**\n+ * DRM_IOCTL_PRIME_HANDLE_TO_FD - Convert a GEM handle to a DMA-BUF FD.\n+ *\n+ * User-space sets &drm_prime_handle.handle with the GEM handle to export and\n+ * &drm_prime_handle.flags, and gets back a DMA-BUF file descriptor in\n+ * &drm_prime_handle.fd.\n+ *\n+ * The export can fail for any driver-specific reason, e.g. because export is\n+ * not supported for this specific GEM handle (but might be for others).\n+ *\n+ * Support for exporting DMA-BUFs is advertised via &DRM_PRIME_CAP_EXPORT.\n+ */\n+#define DRM_IOCTL_PRIME_HANDLE_TO_FD DRM_IOWR(0x2d, struct drm_prime_handle)\n+/**\n+ * DRM_IOCTL_PRIME_FD_TO_HANDLE - Convert a DMA-BUF FD to a GEM handle.\n+ *\n+ * User-space sets &drm_prime_handle.fd with a DMA-BUF file descriptor to\n+ * import, and gets back a GEM handle in &drm_prime_handle.handle.\n+ * &drm_prime_handle.flags is unused.\n+ *\n+ * If an existing GEM handle refers to the memory object backing the DMA-BUF,\n+ * that GEM handle is returned. Therefore user-space which needs to handle\n+ * arbitrary DMA-BUFs must have a user-space lookup data structure to manually\n+ * reference-count duplicated GEM handles. For more information see\n+ * &DRM_IOCTL_GEM_CLOSE.\n+ *\n+ * The import can fail for any driver-specific reason, e.g. because import is\n+ * only supported for DMA-BUFs allocated on this DRM device.\n+ *\n+ * Support for importing DMA-BUFs is advertised via &DRM_PRIME_CAP_IMPORT.\n+ */\n+#define DRM_IOCTL_PRIME_FD_TO_HANDLE DRM_IOWR(0x2e, struct drm_prime_handle)\n+\n+#define DRM_IOCTL_AGP_ACQUIRE\t\tDRM_IO( 0x30)\n+#define DRM_IOCTL_AGP_RELEASE\t\tDRM_IO( 0x31)\n+#define DRM_IOCTL_AGP_ENABLE\t\tDRM_IOW( 0x32, struct drm_agp_mode)\n+#define DRM_IOCTL_AGP_INFO\t\tDRM_IOR( 0x33, struct drm_agp_info)\n+#define DRM_IOCTL_AGP_ALLOC\t\tDRM_IOWR(0x34, struct drm_agp_buffer)\n+#define DRM_IOCTL_AGP_FREE\t\tDRM_IOW( 0x35, struct drm_agp_buffer)\n+#define DRM_IOCTL_AGP_BIND\t\tDRM_IOW( 0x36, struct drm_agp_binding)\n+#define DRM_IOCTL_AGP_UNBIND\t\tDRM_IOW( 0x37, struct drm_agp_binding)\n+\n+#define DRM_IOCTL_SG_ALLOC\t\tDRM_IOWR(0x38, struct drm_scatter_gather)\n+#define DRM_IOCTL_SG_FREE\t\tDRM_IOW( 0x39, struct drm_scatter_gather)\n+\n+#define DRM_IOCTL_WAIT_VBLANK\t\tDRM_IOWR(0x3a, union drm_wait_vblank)\n+\n+#define DRM_IOCTL_CRTC_GET_SEQUENCE\tDRM_IOWR(0x3b, struct drm_crtc_get_sequence)\n+#define DRM_IOCTL_CRTC_QUEUE_SEQUENCE\tDRM_IOWR(0x3c, struct drm_crtc_queue_sequence)\n+\n+#define DRM_IOCTL_UPDATE_DRAW\t\tDRM_IOW(0x3f, struct drm_update_draw)\n+\n+#define DRM_IOCTL_MODE_GETRESOURCES\tDRM_IOWR(0xA0, struct drm_mode_card_res)\n+#define DRM_IOCTL_MODE_GETCRTC\t\tDRM_IOWR(0xA1, struct drm_mode_crtc)\n+#define DRM_IOCTL_MODE_SETCRTC\t\tDRM_IOWR(0xA2, struct drm_mode_crtc)\n+#define DRM_IOCTL_MODE_CURSOR\t\tDRM_IOWR(0xA3, struct drm_mode_cursor)\n+#define DRM_IOCTL_MODE_GETGAMMA\t\tDRM_IOWR(0xA4, struct drm_mode_crtc_lut)\n+#define DRM_IOCTL_MODE_SETGAMMA\t\tDRM_IOWR(0xA5, struct drm_mode_crtc_lut)\n+#define DRM_IOCTL_MODE_GETENCODER\tDRM_IOWR(0xA6, struct drm_mode_get_encoder)\n+#define DRM_IOCTL_MODE_GETCONNECTOR\tDRM_IOWR(0xA7, struct drm_mode_get_connector)\n+#define DRM_IOCTL_MODE_ATTACHMODE\tDRM_IOWR(0xA8, struct drm_mode_mode_cmd) /* deprecated (never worked) */\n+#define DRM_IOCTL_MODE_DETACHMODE\tDRM_IOWR(0xA9, struct drm_mode_mode_cmd) /* deprecated (never worked) */\n+\n+#define DRM_IOCTL_MODE_GETPROPERTY\tDRM_IOWR(0xAA, struct drm_mode_get_property)\n+#define DRM_IOCTL_MODE_SETPROPERTY\tDRM_IOWR(0xAB, struct drm_mode_connector_set_property)\n+#define DRM_IOCTL_MODE_GETPROPBLOB\tDRM_IOWR(0xAC, struct drm_mode_get_blob)\n+#define DRM_IOCTL_MODE_GETFB\t\tDRM_IOWR(0xAD, struct drm_mode_fb_cmd)\n+#define DRM_IOCTL_MODE_ADDFB\t\tDRM_IOWR(0xAE, struct drm_mode_fb_cmd)\n+/**\n+ * DRM_IOCTL_MODE_RMFB - Remove a framebuffer.\n+ *\n+ * This removes a framebuffer previously added via ADDFB/ADDFB2. The IOCTL\n+ * argument is a framebuffer object ID.\n+ *\n+ * Warning: removing a framebuffer currently in-use on an enabled plane will\n+ * disable that plane. The CRTC the plane is linked to may also be disabled\n+ * (depending on driver capabilities).\n+ */\n+#define DRM_IOCTL_MODE_RMFB\t\tDRM_IOWR(0xAF, unsigned int)\n+#define DRM_IOCTL_MODE_PAGE_FLIP\tDRM_IOWR(0xB0, struct drm_mode_crtc_page_flip)\n+#define DRM_IOCTL_MODE_DIRTYFB\t\tDRM_IOWR(0xB1, struct drm_mode_fb_dirty_cmd)\n+\n+/**\n+ * DRM_IOCTL_MODE_CREATE_DUMB - Create a new dumb buffer object.\n+ *\n+ * KMS dumb buffers provide a very primitive way to allocate a buffer object\n+ * suitable for scanout and map it for software rendering. KMS dumb buffers are\n+ * not suitable for hardware-accelerated rendering nor video decoding. KMS dumb\n+ * buffers are not suitable to be displayed on any other device than the KMS\n+ * device where they were allocated from. Also see\n+ * :ref:`kms_dumb_buffer_objects`.\n+ *\n+ * The IOCTL argument is a struct drm_mode_create_dumb.\n+ *\n+ * User-space is expected to create a KMS dumb buffer via this IOCTL, then add\n+ * it as a KMS framebuffer via &DRM_IOCTL_MODE_ADDFB and map it via\n+ * &DRM_IOCTL_MODE_MAP_DUMB.\n+ *\n+ * &DRM_CAP_DUMB_BUFFER indicates whether this IOCTL is supported.\n+ * &DRM_CAP_DUMB_PREFERRED_DEPTH and &DRM_CAP_DUMB_PREFER_SHADOW indicate\n+ * driver preferences for dumb buffers.\n+ */\n+#define DRM_IOCTL_MODE_CREATE_DUMB DRM_IOWR(0xB2, struct drm_mode_create_dumb)\n+#define DRM_IOCTL_MODE_MAP_DUMB DRM_IOWR(0xB3, struct drm_mode_map_dumb)\n+#define DRM_IOCTL_MODE_DESTROY_DUMB DRM_IOWR(0xB4, struct drm_mode_destroy_dumb)\n+#define DRM_IOCTL_MODE_GETPLANERESOURCES DRM_IOWR(0xB5, struct drm_mode_get_plane_res)\n+#define DRM_IOCTL_MODE_GETPLANE\tDRM_IOWR(0xB6, struct drm_mode_get_plane)\n+#define DRM_IOCTL_MODE_SETPLANE\tDRM_IOWR(0xB7, struct drm_mode_set_plane)\n+#define DRM_IOCTL_MODE_ADDFB2\t\tDRM_IOWR(0xB8, struct drm_mode_fb_cmd2)\n+#define DRM_IOCTL_MODE_OBJ_GETPROPERTIES\tDRM_IOWR(0xB9, struct drm_mode_obj_get_properties)\n+#define DRM_IOCTL_MODE_OBJ_SETPROPERTY\tDRM_IOWR(0xBA, struct drm_mode_obj_set_property)\n+#define DRM_IOCTL_MODE_CURSOR2\t\tDRM_IOWR(0xBB, struct drm_mode_cursor2)\n+#define DRM_IOCTL_MODE_ATOMIC\t\tDRM_IOWR(0xBC, struct drm_mode_atomic)\n+#define DRM_IOCTL_MODE_CREATEPROPBLOB\tDRM_IOWR(0xBD, struct drm_mode_create_blob)\n+#define DRM_IOCTL_MODE_DESTROYPROPBLOB\tDRM_IOWR(0xBE, struct drm_mode_destroy_blob)\n+\n+#define DRM_IOCTL_SYNCOBJ_CREATE\tDRM_IOWR(0xBF, struct drm_syncobj_create)\n+#define DRM_IOCTL_SYNCOBJ_DESTROY\tDRM_IOWR(0xC0, struct drm_syncobj_destroy)\n+#define DRM_IOCTL_SYNCOBJ_HANDLE_TO_FD\tDRM_IOWR(0xC1, struct drm_syncobj_handle)\n+#define DRM_IOCTL_SYNCOBJ_FD_TO_HANDLE\tDRM_IOWR(0xC2, struct drm_syncobj_handle)\n+#define DRM_IOCTL_SYNCOBJ_WAIT\t\tDRM_IOWR(0xC3, struct drm_syncobj_wait)\n+#define DRM_IOCTL_SYNCOBJ_RESET\t\tDRM_IOWR(0xC4, struct drm_syncobj_array)\n+#define DRM_IOCTL_SYNCOBJ_SIGNAL\tDRM_IOWR(0xC5, struct drm_syncobj_array)\n+\n+#define DRM_IOCTL_MODE_CREATE_LEASE\tDRM_IOWR(0xC6, struct drm_mode_create_lease)\n+#define DRM_IOCTL_MODE_LIST_LESSEES\tDRM_IOWR(0xC7, struct drm_mode_list_lessees)\n+#define DRM_IOCTL_MODE_GET_LEASE\tDRM_IOWR(0xC8, struct drm_mode_get_lease)\n+#define DRM_IOCTL_MODE_REVOKE_LEASE\tDRM_IOWR(0xC9, struct drm_mode_revoke_lease)\n+\n+#define DRM_IOCTL_SYNCOBJ_TIMELINE_WAIT\tDRM_IOWR(0xCA, struct drm_syncobj_timeline_wait)\n+#define DRM_IOCTL_SYNCOBJ_QUERY\t\tDRM_IOWR(0xCB, struct drm_syncobj_timeline_array)\n+#define DRM_IOCTL_SYNCOBJ_TRANSFER\tDRM_IOWR(0xCC, struct drm_syncobj_transfer)\n+#define DRM_IOCTL_SYNCOBJ_TIMELINE_SIGNAL\tDRM_IOWR(0xCD, struct drm_syncobj_timeline_array)\n+\n+/**\n+ * DRM_IOCTL_MODE_GETFB2 - Get framebuffer metadata.\n+ *\n+ * This queries metadata about a framebuffer. User-space fills\n+ * &drm_mode_fb_cmd2.fb_id as the input, and the kernels fills the rest of the\n+ * struct as the output.\n+ *\n+ * If the client is DRM master or has &CAP_SYS_ADMIN, &drm_mode_fb_cmd2.handles\n+ * will be filled with GEM buffer handles. Fresh new GEM handles are always\n+ * returned, even if another GEM handle referring to the same memory object\n+ * already exists on the DRM file description. The caller is responsible for\n+ * removing the new handles, e.g. via the &DRM_IOCTL_GEM_CLOSE IOCTL. The same\n+ * new handle will be returned for multiple planes in case they use the same\n+ * memory object. Planes are valid until one has a zero handle -- this can be\n+ * used to compute the number of planes.\n+ *\n+ * Otherwise, &drm_mode_fb_cmd2.handles will be zeroed and planes are valid\n+ * until one has a zero &drm_mode_fb_cmd2.pitches.\n+ *\n+ * If the framebuffer has a format modifier, &DRM_MODE_FB_MODIFIERS will be set\n+ * in &drm_mode_fb_cmd2.flags and &drm_mode_fb_cmd2.modifier will contain the\n+ * modifier. Otherwise, user-space must ignore &drm_mode_fb_cmd2.modifier.\n+ *\n+ * To obtain DMA-BUF FDs for each plane without leaking GEM handles, user-space\n+ * can export each handle via &DRM_IOCTL_PRIME_HANDLE_TO_FD, then immediately\n+ * close each unique handle via &DRM_IOCTL_GEM_CLOSE, making sure to not\n+ * double-close handles which are specified multiple times in the array.\n+ */\n+#define DRM_IOCTL_MODE_GETFB2\t\tDRM_IOWR(0xCE, struct drm_mode_fb_cmd2)\n+\n+#define DRM_IOCTL_SYNCOBJ_EVENTFD\tDRM_IOWR(0xCF, struct drm_syncobj_eventfd)\n+\n+/**\n+ * DRM_IOCTL_MODE_CLOSEFB - Close a framebuffer.\n+ *\n+ * This closes a framebuffer previously added via ADDFB/ADDFB2. The IOCTL\n+ * argument is a framebuffer object ID.\n+ *\n+ * This IOCTL is similar to &DRM_IOCTL_MODE_RMFB, except it doesn't disable\n+ * planes and CRTCs. As long as the framebuffer is used by a plane, it's kept\n+ * alive. When the plane no longer uses the framebuffer (because the\n+ * framebuffer is replaced with another one, or the plane is disabled), the\n+ * framebuffer is cleaned up.\n+ *\n+ * This is useful to implement flicker-free transitions between two processes.\n+ *\n+ * Depending on the threat model, user-space may want to ensure that the\n+ * framebuffer doesn't expose any sensitive user information: closed\n+ * framebuffers attached to a plane can be read back by the next DRM master.\n+ */\n+#define DRM_IOCTL_MODE_CLOSEFB\t\tDRM_IOWR(0xD0, struct drm_mode_closefb)\n+\n+/**\n+ * DRM_IOCTL_SET_CLIENT_NAME - Attach a name to a drm_file\n+ *\n+ * Having a name allows for easier tracking and debugging.\n+ * The length of the name (without null ending char) must be\n+ * <= DRM_CLIENT_NAME_MAX_LEN.\n+ * The call will fail if the name contains whitespaces or non-printable chars.\n+ */\n+#define DRM_IOCTL_SET_CLIENT_NAME\tDRM_IOWR(0xD1, struct drm_set_client_name)\n+\n+/**\n+ * DRM_IOCTL_GEM_CHANGE_HANDLE - Move an object to a different handle\n+ *\n+ * Some applications (notably CRIU) need objects to have specific gem handles.\n+ * This ioctl changes the object at one gem handle to use a new gem handle.\n+ */\n+#define DRM_IOCTL_GEM_CHANGE_HANDLE DRM_IOWR(0xD2, struct drm_gem_change_handle)\n+\n+/*\n+ * Device specific ioctls should only be in their respective headers\n+ * The device specific ioctl range is from 0x40 to 0x9f.\n+ * Generic IOCTLS restart at 0xA0.\n+ *\n+ * \\sa drmCommandNone(), drmCommandRead(), drmCommandWrite(), and\n+ * drmCommandReadWrite().\n+ */\n+#define DRM_COMMAND_BASE 0x40\n+#define DRM_COMMAND_END\t\t\t0xA0\n+\n+/**\n+ * struct drm_event - Header for DRM events\n+ * @type: event type.\n+ * @length: total number of payload bytes (including header).\n+ *\n+ * This struct is a header for events written back to user-space on the DRM FD.\n+ * A read on the DRM FD will always only return complete events: e.g. if the\n+ * read buffer is 100 bytes large and there are two 64 byte events pending,\n+ * only one will be returned.\n+ *\n+ * Event types 0 - 0x7fffffff are generic DRM events, 0x80000000 and\n+ * up are chipset specific. Generic DRM events include &DRM_EVENT_VBLANK,\n+ * &DRM_EVENT_FLIP_COMPLETE and &DRM_EVENT_CRTC_SEQUENCE.\n+ */\n+struct drm_event {\n+\t__u32 type;\n+\t__u32 length;\n+};\n+\n+/**\n+ * DRM_EVENT_VBLANK - vertical blanking event\n+ *\n+ * This event is sent in response to &DRM_IOCTL_WAIT_VBLANK with the\n+ * &_DRM_VBLANK_EVENT flag set.\n+ *\n+ * The event payload is a struct drm_event_vblank.\n+ */\n+#define DRM_EVENT_VBLANK 0x01\n+/**\n+ * DRM_EVENT_FLIP_COMPLETE - page-flip completion event\n+ *\n+ * This event is sent in response to an atomic commit or legacy page-flip with\n+ * the &DRM_MODE_PAGE_FLIP_EVENT flag set.\n+ *\n+ * The event payload is a struct drm_event_vblank.\n+ */\n+#define DRM_EVENT_FLIP_COMPLETE 0x02\n+/**\n+ * DRM_EVENT_CRTC_SEQUENCE - CRTC sequence event\n+ *\n+ * This event is sent in response to &DRM_IOCTL_CRTC_QUEUE_SEQUENCE.\n+ *\n+ * The event payload is a struct drm_event_crtc_sequence.\n+ */\n+#define DRM_EVENT_CRTC_SEQUENCE\t0x03\n+\n+struct drm_event_vblank {\n+\tstruct drm_event base;\n+\t__u64 user_data;\n+\t__u32 tv_sec;\n+\t__u32 tv_usec;\n+\t__u32 sequence;\n+\t__u32 crtc_id; /* 0 on older kernels that do not support this */\n+};\n+\n+/* Event delivered at sequence. Time stamp marks when the first pixel\n+ * of the refresh cycle leaves the display engine for the display\n+ */\n+struct drm_event_crtc_sequence {\n+\tstruct drm_event\tbase;\n+\t__u64\t\t\tuser_data;\n+\t__s64\t\t\ttime_ns;\n+\t__u64\t\t\tsequence;\n+};\n+\n+/* typedef area */\n+typedef struct drm_clip_rect drm_clip_rect_t;\n+typedef struct drm_drawable_info drm_drawable_info_t;\n+typedef struct drm_tex_region drm_tex_region_t;\n+typedef struct drm_hw_lock drm_hw_lock_t;\n+typedef struct drm_version drm_version_t;\n+typedef struct drm_unique drm_unique_t;\n+typedef struct drm_list drm_list_t;\n+typedef struct drm_block drm_block_t;\n+typedef struct drm_control drm_control_t;\n+typedef enum drm_map_type drm_map_type_t;\n+typedef enum drm_map_flags drm_map_flags_t;\n+typedef struct drm_ctx_priv_map drm_ctx_priv_map_t;\n+typedef struct drm_map drm_map_t;\n+typedef struct drm_client drm_client_t;\n+typedef enum drm_stat_type drm_stat_type_t;\n+typedef struct drm_stats drm_stats_t;\n+typedef enum drm_lock_flags drm_lock_flags_t;\n+typedef struct drm_lock drm_lock_t;\n+typedef enum drm_dma_flags drm_dma_flags_t;\n+typedef struct drm_buf_desc drm_buf_desc_t;\n+typedef struct drm_buf_info drm_buf_info_t;\n+typedef struct drm_buf_free drm_buf_free_t;\n+typedef struct drm_buf_pub drm_buf_pub_t;\n+typedef struct drm_buf_map drm_buf_map_t;\n+typedef struct drm_dma drm_dma_t;\n+typedef union drm_wait_vblank drm_wait_vblank_t;\n+typedef struct drm_agp_mode drm_agp_mode_t;\n+typedef enum drm_ctx_flags drm_ctx_flags_t;\n+typedef struct drm_ctx drm_ctx_t;\n+typedef struct drm_ctx_res drm_ctx_res_t;\n+typedef struct drm_draw drm_draw_t;\n+typedef struct drm_update_draw drm_update_draw_t;\n+typedef struct drm_auth drm_auth_t;\n+typedef struct drm_irq_busid drm_irq_busid_t;\n+typedef enum drm_vblank_seq_type drm_vblank_seq_type_t;\n+\n+typedef struct drm_agp_buffer drm_agp_buffer_t;\n+typedef struct drm_agp_binding drm_agp_binding_t;\n+typedef struct drm_agp_info drm_agp_info_t;\n+typedef struct drm_scatter_gather drm_scatter_gather_t;\n+typedef struct drm_set_version drm_set_version_t;\n+\n+#if defined(__cplusplus)\n+}\n+#endif\n+\n+#endif\ndiff --git a/include/linux/drm_fourcc.h b/include/linux/drm_fourcc.h\nindex b444c7f895e4..e8a3d949032b 100644\n--- a/include/linux/drm_fourcc.h\n+++ b/include/linux/drm_fourcc.h\n@@ -383,8 +383,8 @@ extern \"C\" {\n * implementation can multiply the values by 2^6=64. For that reason the padding\n * must only contain zeros.\n * index 0 = Y plane, [15:0] z:Y [6:10] little endian\n- * index 1 = Cr plane, [15:0] z:Cr [6:10] little endian\n- * index 2 = Cb plane, [15:0] z:Cb [6:10] little endian\n+ * index 1 = Cb plane, [15:0] z:Cb [6:10] little endian\n+ * index 2 = Cr plane, [15:0] z:Cr [6:10] little endian\n */\n #define DRM_FORMAT_S010\tfourcc_code('S', '0', '1', '0') /* 2x2 subsampled Cb (1) and Cr (2) planes 10 bits per channel */\n #define DRM_FORMAT_S210\tfourcc_code('S', '2', '1', '0') /* 2x1 subsampled Cb (1) and Cr (2) planes 10 bits per channel */\n@@ -396,8 +396,8 @@ extern \"C\" {\n * implementation can multiply the values by 2^4=16. For that reason the padding\n * must only contain zeros.\n * index 0 = Y plane, [15:0] z:Y [4:12] little endian\n- * index 1 = Cr plane, [15:0] z:Cr [4:12] little endian\n- * index 2 = Cb plane, [15:0] z:Cb [4:12] little endian\n+ * index 1 = Cb plane, [15:0] z:Cb [4:12] little endian\n+ * index 2 = Cr plane, [15:0] z:Cr [4:12] little endian\n */\n #define DRM_FORMAT_S012\tfourcc_code('S', '0', '1', '2') /* 2x2 subsampled Cb (1) and Cr (2) planes 12 bits per channel */\n #define DRM_FORMAT_S212\tfourcc_code('S', '2', '1', '2') /* 2x1 subsampled Cb (1) and Cr (2) planes 12 bits per channel */\n@@ -406,8 +406,8 @@ extern \"C\" {\n /*\n * 3 plane YCbCr\n * index 0 = Y plane, [15:0] Y little endian\n- * index 1 = Cr plane, [15:0] Cr little endian\n- * index 2 = Cb plane, [15:0] Cb little endian\n+ * index 1 = Cb plane, [15:0] Cb little endian\n+ * index 2 = Cr plane, [15:0] Cr little endian\n */\n #define DRM_FORMAT_S016\tfourcc_code('S', '0', '1', '6') /* 2x2 subsampled Cb (1) and Cr (2) planes 16 bits per channel */\n #define DRM_FORMAT_S216\tfourcc_code('S', '2', '1', '6') /* 2x1 subsampled Cb (1) and Cr (2) planes 16 bits per channel */\ndiff --git a/include/linux/drm_mode.h b/include/linux/drm_mode.h\nnew file mode 100644\nindex 000000000000..8894b7a80732\n--- /dev/null\n+++ b/include/linux/drm_mode.h\n@@ -0,0 +1,1535 @@\n+/* SPDX-License-Identifier: MIT */\n+/*\n+ * Copyright (c) 2007 Dave Airlie \n+ * Copyright (c) 2007 Jakob Bornecrantz \n+ * Copyright (c) 2008 Red Hat Inc.\n+ * Copyright (c) 2007-2008 Tungsten Graphics, Inc., Cedar Park, TX., USA\n+ * Copyright (c) 2007-2008 Intel Corporation\n+ */\n+\n+#ifndef _DRM_MODE_H\n+#define _DRM_MODE_H\n+\n+#include \"drm.h\"\n+\n+#if defined(__cplusplus)\n+extern \"C\" {\n+#endif\n+\n+/**\n+ * DOC: overview\n+ *\n+ * DRM exposes many UAPI and structure definitions to have a consistent\n+ * and standardized interface with users.\n+ * Userspace can refer to these structure definitions and UAPI formats\n+ * to communicate to drivers.\n+ */\n+\n+#define DRM_CONNECTOR_NAME_LEN\t32\n+#define DRM_DISPLAY_MODE_LEN\t32\n+#define DRM_PROP_NAME_LEN\t32\n+\n+#define DRM_MODE_TYPE_BUILTIN\t(1<<0) /* deprecated */\n+#define DRM_MODE_TYPE_CLOCK_C\t((1<<1) | DRM_MODE_TYPE_BUILTIN) /* deprecated */\n+#define DRM_MODE_TYPE_CRTC_C\t((1<<2) | DRM_MODE_TYPE_BUILTIN) /* deprecated */\n+#define DRM_MODE_TYPE_PREFERRED\t(1<<3)\n+#define DRM_MODE_TYPE_DEFAULT\t(1<<4) /* deprecated */\n+#define DRM_MODE_TYPE_USERDEF\t(1<<5)\n+#define DRM_MODE_TYPE_DRIVER\t(1<<6)\n+\n+#define DRM_MODE_TYPE_ALL\t(DRM_MODE_TYPE_PREFERRED |\t\\\n+\t\t\t\t DRM_MODE_TYPE_USERDEF |\t\\\n+\t\t\t\t DRM_MODE_TYPE_DRIVER)\n+\n+/* Video mode flags */\n+/* bit compatible with the xrandr RR_ definitions (bits 0-13)\n+ *\n+ * ABI warning: Existing userspace really expects\n+ * the mode flags to match the xrandr definitions. Any\n+ * changes that don't match the xrandr definitions will\n+ * likely need a new client cap or some other mechanism\n+ * to avoid breaking existing userspace. This includes\n+ * allocating new flags in the previously unused bits!\n+ */\n+#define DRM_MODE_FLAG_PHSYNC\t\t\t(1<<0)\n+#define DRM_MODE_FLAG_NHSYNC\t\t\t(1<<1)\n+#define DRM_MODE_FLAG_PVSYNC\t\t\t(1<<2)\n+#define DRM_MODE_FLAG_NVSYNC\t\t\t(1<<3)\n+#define DRM_MODE_FLAG_INTERLACE\t\t\t(1<<4)\n+#define DRM_MODE_FLAG_DBLSCAN\t\t\t(1<<5)\n+#define DRM_MODE_FLAG_CSYNC\t\t\t(1<<6)\n+#define DRM_MODE_FLAG_PCSYNC\t\t\t(1<<7)\n+#define DRM_MODE_FLAG_NCSYNC\t\t\t(1<<8)\n+#define DRM_MODE_FLAG_HSKEW\t\t\t(1<<9) /* hskew provided */\n+#define DRM_MODE_FLAG_BCAST\t\t\t(1<<10) /* deprecated */\n+#define DRM_MODE_FLAG_PIXMUX\t\t\t(1<<11) /* deprecated */\n+#define DRM_MODE_FLAG_DBLCLK\t\t\t(1<<12)\n+#define DRM_MODE_FLAG_CLKDIV2\t\t\t(1<<13)\n+ /*\n+ * When adding a new stereo mode don't forget to adjust DRM_MODE_FLAGS_3D_MAX\n+ * (define not exposed to user space).\n+ */\n+#define DRM_MODE_FLAG_3D_MASK\t\t\t(0x1f<<14)\n+#define DRM_MODE_FLAG_3D_NONE\t\t(0<<14)\n+#define DRM_MODE_FLAG_3D_FRAME_PACKING\t\t(1<<14)\n+#define DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE\t(2<<14)\n+#define DRM_MODE_FLAG_3D_LINE_ALTERNATIVE\t(3<<14)\n+#define DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL\t(4<<14)\n+#define DRM_MODE_FLAG_3D_L_DEPTH\t\t(5<<14)\n+#define DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH\t(6<<14)\n+#define DRM_MODE_FLAG_3D_TOP_AND_BOTTOM\t(7<<14)\n+#define DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF\t(8<<14)\n+\n+/* Picture aspect ratio options */\n+#define DRM_MODE_PICTURE_ASPECT_NONE\t\t0\n+#define DRM_MODE_PICTURE_ASPECT_4_3\t\t1\n+#define DRM_MODE_PICTURE_ASPECT_16_9\t\t2\n+#define DRM_MODE_PICTURE_ASPECT_64_27\t\t3\n+#define DRM_MODE_PICTURE_ASPECT_256_135\t\t4\n+\n+/* Content type options */\n+#define DRM_MODE_CONTENT_TYPE_NO_DATA\t\t0\n+#define DRM_MODE_CONTENT_TYPE_GRAPHICS\t\t1\n+#define DRM_MODE_CONTENT_TYPE_PHOTO\t\t2\n+#define DRM_MODE_CONTENT_TYPE_CINEMA\t\t3\n+#define DRM_MODE_CONTENT_TYPE_GAME\t\t4\n+\n+/* Aspect ratio flag bitmask (4 bits 22:19) */\n+#define DRM_MODE_FLAG_PIC_AR_MASK\t\t(0x0F<<19)\n+#define DRM_MODE_FLAG_PIC_AR_NONE \\\n+\t\t\t(DRM_MODE_PICTURE_ASPECT_NONE<<19)\n+#define DRM_MODE_FLAG_PIC_AR_4_3 \\\n+\t\t\t(DRM_MODE_PICTURE_ASPECT_4_3<<19)\n+#define DRM_MODE_FLAG_PIC_AR_16_9 \\\n+\t\t\t(DRM_MODE_PICTURE_ASPECT_16_9<<19)\n+#define DRM_MODE_FLAG_PIC_AR_64_27 \\\n+\t\t\t(DRM_MODE_PICTURE_ASPECT_64_27<<19)\n+#define DRM_MODE_FLAG_PIC_AR_256_135 \\\n+\t\t\t(DRM_MODE_PICTURE_ASPECT_256_135<<19)\n+\n+#define DRM_MODE_FLAG_ALL\t(DRM_MODE_FLAG_PHSYNC |\t\t\\\n+\t\t\t\t DRM_MODE_FLAG_NHSYNC |\t\t\\\n+\t\t\t\t DRM_MODE_FLAG_PVSYNC |\t\t\\\n+\t\t\t\t DRM_MODE_FLAG_NVSYNC |\t\t\\\n+\t\t\t\t DRM_MODE_FLAG_INTERLACE |\t\\\n+\t\t\t\t DRM_MODE_FLAG_DBLSCAN |\t\\\n+\t\t\t\t DRM_MODE_FLAG_CSYNC |\t\t\\\n+\t\t\t\t DRM_MODE_FLAG_PCSYNC |\t\t\\\n+\t\t\t\t DRM_MODE_FLAG_NCSYNC |\t\t\\\n+\t\t\t\t DRM_MODE_FLAG_HSKEW |\t\t\\\n+\t\t\t\t DRM_MODE_FLAG_DBLCLK |\t\t\\\n+\t\t\t\t DRM_MODE_FLAG_CLKDIV2 |\t\\\n+\t\t\t\t DRM_MODE_FLAG_3D_MASK)\n+\n+/* DPMS flags */\n+/* bit compatible with the xorg definitions. */\n+#define DRM_MODE_DPMS_ON\t0\n+#define DRM_MODE_DPMS_STANDBY\t1\n+#define DRM_MODE_DPMS_SUSPEND\t2\n+#define DRM_MODE_DPMS_OFF\t3\n+\n+/* Scaling mode options */\n+#define DRM_MODE_SCALE_NONE\t\t0 /* Unmodified timing (display or\n+\t\t\t\t\t software can still scale) */\n+#define DRM_MODE_SCALE_FULLSCREEN\t1 /* Full screen, ignore aspect */\n+#define DRM_MODE_SCALE_CENTER\t\t2 /* Centered, no scaling */\n+#define DRM_MODE_SCALE_ASPECT\t\t3 /* Full screen, preserve aspect */\n+\n+/* Dithering mode options */\n+#define DRM_MODE_DITHERING_OFF\t0\n+#define DRM_MODE_DITHERING_ON\t1\n+#define DRM_MODE_DITHERING_AUTO 2\n+\n+/* Dirty info options */\n+#define DRM_MODE_DIRTY_OFF 0\n+#define DRM_MODE_DIRTY_ON 1\n+#define DRM_MODE_DIRTY_ANNOTATE 2\n+\n+/* Link Status options */\n+#define DRM_MODE_LINK_STATUS_GOOD\t0\n+#define DRM_MODE_LINK_STATUS_BAD\t1\n+\n+/*\n+ * DRM_MODE_ROTATE_\n+ *\n+ * Signals that a drm plane is been rotated degrees in counter\n+ * clockwise direction.\n+ *\n+ * This define is provided as a convenience, looking up the property id\n+ * using the name->prop id lookup is the preferred method.\n+ */\n+#define DRM_MODE_ROTATE_0 (1<<0)\n+#define DRM_MODE_ROTATE_90 (1<<1)\n+#define DRM_MODE_ROTATE_180 (1<<2)\n+#define DRM_MODE_ROTATE_270 (1<<3)\n+\n+/*\n+ * DRM_MODE_ROTATE_MASK\n+ *\n+ * Bitmask used to look for drm plane rotations.\n+ */\n+#define DRM_MODE_ROTATE_MASK (\\\n+\t\tDRM_MODE_ROTATE_0 | \\\n+\t\tDRM_MODE_ROTATE_90 | \\\n+\t\tDRM_MODE_ROTATE_180 | \\\n+\t\tDRM_MODE_ROTATE_270)\n+\n+/*\n+ * DRM_MODE_REFLECT_\n+ *\n+ * Signals that the contents of a drm plane is reflected along the axis,\n+ * in the same way as mirroring.\n+ * See kerneldoc chapter \"Plane Composition Properties\" for more details.\n+ *\n+ * This define is provided as a convenience, looking up the property id\n+ * using the name->prop id lookup is the preferred method.\n+ */\n+#define DRM_MODE_REFLECT_X (1<<4)\n+#define DRM_MODE_REFLECT_Y (1<<5)\n+\n+/*\n+ * DRM_MODE_REFLECT_MASK\n+ *\n+ * Bitmask used to look for drm plane reflections.\n+ */\n+#define DRM_MODE_REFLECT_MASK (\\\n+\t\tDRM_MODE_REFLECT_X | \\\n+\t\tDRM_MODE_REFLECT_Y)\n+\n+/* Content Protection Flags */\n+#define DRM_MODE_CONTENT_PROTECTION_UNDESIRED\t0\n+#define DRM_MODE_CONTENT_PROTECTION_DESIRED 1\n+#define DRM_MODE_CONTENT_PROTECTION_ENABLED 2\n+\n+/**\n+ * struct drm_mode_modeinfo - Display mode information.\n+ * @clock: pixel clock in kHz\n+ * @hdisplay: horizontal display size\n+ * @hsync_start: horizontal sync start\n+ * @hsync_end: horizontal sync end\n+ * @htotal: horizontal total size\n+ * @hskew: horizontal skew\n+ * @vdisplay: vertical display size\n+ * @vsync_start: vertical sync start\n+ * @vsync_end: vertical sync end\n+ * @vtotal: vertical total size\n+ * @vscan: vertical scan\n+ * @vrefresh: approximate vertical refresh rate in Hz\n+ * @flags: bitmask of misc. flags, see DRM_MODE_FLAG_* defines\n+ * @type: bitmask of type flags, see DRM_MODE_TYPE_* defines\n+ * @name: string describing the mode resolution\n+ *\n+ * This is the user-space API display mode information structure. For the\n+ * kernel version see struct drm_display_mode.\n+ */\n+struct drm_mode_modeinfo {\n+\t__u32 clock;\n+\t__u16 hdisplay;\n+\t__u16 hsync_start;\n+\t__u16 hsync_end;\n+\t__u16 htotal;\n+\t__u16 hskew;\n+\t__u16 vdisplay;\n+\t__u16 vsync_start;\n+\t__u16 vsync_end;\n+\t__u16 vtotal;\n+\t__u16 vscan;\n+\n+\t__u32 vrefresh;\n+\n+\t__u32 flags;\n+\t__u32 type;\n+\tchar name[DRM_DISPLAY_MODE_LEN];\n+};\n+\n+struct drm_mode_card_res {\n+\t__u64 fb_id_ptr;\n+\t__u64 crtc_id_ptr;\n+\t__u64 connector_id_ptr;\n+\t__u64 encoder_id_ptr;\n+\t__u32 count_fbs;\n+\t__u32 count_crtcs;\n+\t__u32 count_connectors;\n+\t__u32 count_encoders;\n+\t__u32 min_width;\n+\t__u32 max_width;\n+\t__u32 min_height;\n+\t__u32 max_height;\n+};\n+\n+struct drm_mode_crtc {\n+\t__u64 set_connectors_ptr;\n+\t__u32 count_connectors;\n+\n+\t__u32 crtc_id; /**< Id */\n+\t__u32 fb_id; /**< Id of framebuffer */\n+\n+\t__u32 x; /**< x Position on the framebuffer */\n+\t__u32 y; /**< y Position on the framebuffer */\n+\n+\t__u32 gamma_size;\n+\t__u32 mode_valid;\n+\tstruct drm_mode_modeinfo mode;\n+};\n+\n+#define DRM_MODE_PRESENT_TOP_FIELD\t(1<<0)\n+#define DRM_MODE_PRESENT_BOTTOM_FIELD\t(1<<1)\n+\n+/* Planes blend with or override other bits on the CRTC */\n+struct drm_mode_set_plane {\n+\t__u32 plane_id;\n+\t__u32 crtc_id;\n+\t__u32 fb_id; /* fb object contains surface format type */\n+\t__u32 flags; /* see above flags */\n+\n+\t/* Signed dest location allows it to be partially off screen */\n+\t__s32 crtc_x;\n+\t__s32 crtc_y;\n+\t__u32 crtc_w;\n+\t__u32 crtc_h;\n+\n+\t/* Source values are 16.16 fixed point */\n+\t__u32 src_x;\n+\t__u32 src_y;\n+\t__u32 src_h;\n+\t__u32 src_w;\n+};\n+\n+/**\n+ * struct drm_mode_get_plane - Get plane metadata.\n+ *\n+ * Userspace can perform a GETPLANE ioctl to retrieve information about a\n+ * plane.\n+ *\n+ * To retrieve the number of formats supported, set @count_format_types to zero\n+ * and call the ioctl. @count_format_types will be updated with the value.\n+ *\n+ * To retrieve these formats, allocate an array with the memory needed to store\n+ * @count_format_types formats. Point @format_type_ptr to this array and call\n+ * the ioctl again (with @count_format_types still set to the value returned in\n+ * the first ioctl call).\n+ */\n+struct drm_mode_get_plane {\n+\t/**\n+\t * @plane_id: Object ID of the plane whose information should be\n+\t * retrieved. Set by caller.\n+\t */\n+\t__u32 plane_id;\n+\n+\t/** @crtc_id: Object ID of the current CRTC. */\n+\t__u32 crtc_id;\n+\t/** @fb_id: Object ID of the current fb. */\n+\t__u32 fb_id;\n+\n+\t/**\n+\t * @possible_crtcs: Bitmask of CRTC's compatible with the plane. CRTC's\n+\t * are created and they receive an index, which corresponds to their\n+\t * position in the bitmask. Bit N corresponds to\n+\t * :ref:`CRTC index` N.\n+\t */\n+\t__u32 possible_crtcs;\n+\t/** @gamma_size: Never used. */\n+\t__u32 gamma_size;\n+\n+\t/** @count_format_types: Number of formats. */\n+\t__u32 count_format_types;\n+\t/**\n+\t * @format_type_ptr: Pointer to ``__u32`` array of formats that are\n+\t * supported by the plane. These formats do not require modifiers.\n+\t */\n+\t__u64 format_type_ptr;\n+};\n+\n+struct drm_mode_get_plane_res {\n+\t__u64 plane_id_ptr;\n+\t__u32 count_planes;\n+};\n+\n+#define DRM_MODE_ENCODER_NONE\t0\n+#define DRM_MODE_ENCODER_DAC\t1\n+#define DRM_MODE_ENCODER_TMDS\t2\n+#define DRM_MODE_ENCODER_LVDS\t3\n+#define DRM_MODE_ENCODER_TVDAC\t4\n+#define DRM_MODE_ENCODER_VIRTUAL 5\n+#define DRM_MODE_ENCODER_DSI\t6\n+#define DRM_MODE_ENCODER_DPMST\t7\n+#define DRM_MODE_ENCODER_DPI\t8\n+\n+struct drm_mode_get_encoder {\n+\t__u32 encoder_id;\n+\t__u32 encoder_type;\n+\n+\t__u32 crtc_id; /**< Id of crtc */\n+\n+\t__u32 possible_crtcs;\n+\t__u32 possible_clones;\n+};\n+\n+/* This is for connectors with multiple signal types. */\n+/* Try to match DRM_MODE_CONNECTOR_X as closely as possible. */\n+enum drm_mode_subconnector {\n+\tDRM_MODE_SUBCONNECTOR_Automatic = 0, /* DVI-I, TV */\n+\tDRM_MODE_SUBCONNECTOR_Unknown = 0, /* DVI-I, TV, DP */\n+\tDRM_MODE_SUBCONNECTOR_VGA\t = 1, /* DP */\n+\tDRM_MODE_SUBCONNECTOR_DVID\t = 3, /* DVI-I DP */\n+\tDRM_MODE_SUBCONNECTOR_DVIA\t = 4, /* DVI-I */\n+\tDRM_MODE_SUBCONNECTOR_Composite = 5, /* TV */\n+\tDRM_MODE_SUBCONNECTOR_SVIDEO\t = 6, /* TV */\n+\tDRM_MODE_SUBCONNECTOR_Component = 8, /* TV */\n+\tDRM_MODE_SUBCONNECTOR_SCART\t = 9, /* TV */\n+\tDRM_MODE_SUBCONNECTOR_DisplayPort = 10, /* DP */\n+\tDRM_MODE_SUBCONNECTOR_HDMIA = 11, /* DP */\n+\tDRM_MODE_SUBCONNECTOR_Native = 15, /* DP */\n+\tDRM_MODE_SUBCONNECTOR_Wireless = 18, /* DP */\n+};\n+\n+#define DRM_MODE_CONNECTOR_Unknown\t0\n+#define DRM_MODE_CONNECTOR_VGA\t\t1\n+#define DRM_MODE_CONNECTOR_DVII\t\t2\n+#define DRM_MODE_CONNECTOR_DVID\t\t3\n+#define DRM_MODE_CONNECTOR_DVIA\t\t4\n+#define DRM_MODE_CONNECTOR_Composite\t5\n+#define DRM_MODE_CONNECTOR_SVIDEO\t6\n+#define DRM_MODE_CONNECTOR_LVDS\t\t7\n+#define DRM_MODE_CONNECTOR_Component\t8\n+#define DRM_MODE_CONNECTOR_9PinDIN\t9\n+#define DRM_MODE_CONNECTOR_DisplayPort\t10\n+#define DRM_MODE_CONNECTOR_HDMIA\t11\n+#define DRM_MODE_CONNECTOR_HDMIB\t12\n+#define DRM_MODE_CONNECTOR_TV\t\t13\n+#define DRM_MODE_CONNECTOR_eDP\t\t14\n+#define DRM_MODE_CONNECTOR_VIRTUAL 15\n+#define DRM_MODE_CONNECTOR_DSI\t\t16\n+#define DRM_MODE_CONNECTOR_DPI\t\t17\n+#define DRM_MODE_CONNECTOR_WRITEBACK\t18\n+#define DRM_MODE_CONNECTOR_SPI\t\t19\n+#define DRM_MODE_CONNECTOR_USB\t\t20\n+\n+/**\n+ * struct drm_mode_get_connector - Get connector metadata.\n+ *\n+ * User-space can perform a GETCONNECTOR ioctl to retrieve information about a\n+ * connector. User-space is expected to retrieve encoders, modes and properties\n+ * by performing this ioctl at least twice: the first time to retrieve the\n+ * number of elements, the second time to retrieve the elements themselves.\n+ *\n+ * To retrieve the number of elements, set @count_props and @count_encoders to\n+ * zero, set @count_modes to 1, and set @modes_ptr to a temporary struct\n+ * drm_mode_modeinfo element.\n+ *\n+ * To retrieve the elements, allocate arrays for @encoders_ptr, @modes_ptr,\n+ * @props_ptr and @prop_values_ptr, then set @count_modes, @count_props and\n+ * @count_encoders to their capacity.\n+ *\n+ * Performing the ioctl only twice may be racy: the number of elements may have\n+ * changed with a hotplug event in-between the two ioctls. User-space is\n+ * expected to retry the last ioctl until the number of elements stabilizes.\n+ * The kernel won't fill any array which doesn't have the expected length.\n+ *\n+ * **Force-probing a connector**\n+ *\n+ * If the @count_modes field is set to zero and the DRM client is the current\n+ * DRM master, the kernel will perform a forced probe on the connector to\n+ * refresh the connector status, modes and EDID. A forced-probe can be slow,\n+ * might cause flickering and the ioctl will block.\n+ *\n+ * User-space needs to force-probe connectors to ensure their metadata is\n+ * up-to-date at startup and after receiving a hot-plug event. User-space\n+ * may perform a forced-probe when the user explicitly requests it. User-space\n+ * shouldn't perform a forced-probe in other situations.\n+ */\n+struct drm_mode_get_connector {\n+\t/** @encoders_ptr: Pointer to ``__u32`` array of object IDs. */\n+\t__u64 encoders_ptr;\n+\t/** @modes_ptr: Pointer to struct drm_mode_modeinfo array. */\n+\t__u64 modes_ptr;\n+\t/** @props_ptr: Pointer to ``__u32`` array of property IDs. */\n+\t__u64 props_ptr;\n+\t/** @prop_values_ptr: Pointer to ``__u64`` array of property values. */\n+\t__u64 prop_values_ptr;\n+\n+\t/** @count_modes: Number of modes. */\n+\t__u32 count_modes;\n+\t/** @count_props: Number of properties. */\n+\t__u32 count_props;\n+\t/** @count_encoders: Number of encoders. */\n+\t__u32 count_encoders;\n+\n+\t/** @encoder_id: Object ID of the current encoder. */\n+\t__u32 encoder_id;\n+\t/** @connector_id: Object ID of the connector. */\n+\t__u32 connector_id;\n+\t/**\n+\t * @connector_type: Type of the connector.\n+\t *\n+\t * See DRM_MODE_CONNECTOR_* defines.\n+\t */\n+\t__u32 connector_type;\n+\t/**\n+\t * @connector_type_id: Type-specific connector number.\n+\t *\n+\t * This is not an object ID. This is a per-type connector number. Each\n+\t * (type, type_id) combination is unique across all connectors of a DRM\n+\t * device.\n+\t *\n+\t * The (type, type_id) combination is not a stable identifier: the\n+\t * type_id can change depending on the driver probe order.\n+\t */\n+\t__u32 connector_type_id;\n+\n+\t/**\n+\t * @connection: Status of the connector.\n+\t *\n+\t * See enum drm_connector_status.\n+\t */\n+\t__u32 connection;\n+\t/** @mm_width: Width of the connected sink in millimeters. */\n+\t__u32 mm_width;\n+\t/** @mm_height: Height of the connected sink in millimeters. */\n+\t__u32 mm_height;\n+\t/**\n+\t * @subpixel: Subpixel order of the connected sink.\n+\t *\n+\t * See enum subpixel_order.\n+\t */\n+\t__u32 subpixel;\n+\n+\t/** @pad: Padding, must be zero. */\n+\t__u32 pad;\n+};\n+\n+#define DRM_MODE_PROP_PENDING\t(1<<0) /* deprecated, do not use */\n+#define DRM_MODE_PROP_RANGE\t(1<<1)\n+#define DRM_MODE_PROP_IMMUTABLE\t(1<<2)\n+#define DRM_MODE_PROP_ENUM\t(1<<3) /* enumerated type with text strings */\n+#define DRM_MODE_PROP_BLOB\t(1<<4)\n+#define DRM_MODE_PROP_BITMASK\t(1<<5) /* bitmask of enumerated types */\n+\n+/* non-extended types: legacy bitmask, one bit per type: */\n+#define DRM_MODE_PROP_LEGACY_TYPE ( \\\n+\t\tDRM_MODE_PROP_RANGE | \\\n+\t\tDRM_MODE_PROP_ENUM | \\\n+\t\tDRM_MODE_PROP_BLOB | \\\n+\t\tDRM_MODE_PROP_BITMASK)\n+\n+/* extended-types: rather than continue to consume a bit per type,\n+ * grab a chunk of the bits to use as integer type id.\n+ */\n+#define DRM_MODE_PROP_EXTENDED_TYPE\t0x0000ffc0\n+#define DRM_MODE_PROP_TYPE(n)\t\t((n) << 6)\n+#define DRM_MODE_PROP_OBJECT\t\tDRM_MODE_PROP_TYPE(1)\n+#define DRM_MODE_PROP_SIGNED_RANGE\tDRM_MODE_PROP_TYPE(2)\n+\n+/* the PROP_ATOMIC flag is used to hide properties from userspace that\n+ * is not aware of atomic properties. This is mostly to work around\n+ * older userspace (DDX drivers) that read/write each prop they find,\n+ * without being aware that this could be triggering a lengthy modeset.\n+ */\n+#define DRM_MODE_PROP_ATOMIC 0x80000000\n+\n+/**\n+ * struct drm_mode_property_enum - Description for an enum/bitfield entry.\n+ * @value: numeric value for this enum entry.\n+ * @name: symbolic name for this enum entry.\n+ *\n+ * See struct drm_property_enum for details.\n+ */\n+struct drm_mode_property_enum {\n+\t__u64 value;\n+\tchar name[DRM_PROP_NAME_LEN];\n+};\n+\n+/**\n+ * struct drm_mode_get_property - Get property metadata.\n+ *\n+ * User-space can perform a GETPROPERTY ioctl to retrieve information about a\n+ * property. The same property may be attached to multiple objects, see\n+ * \"Modeset Base Object Abstraction\".\n+ *\n+ * The meaning of the @values_ptr field changes depending on the property type.\n+ * See &drm_property.flags for more details.\n+ *\n+ * The @enum_blob_ptr and @count_enum_blobs fields are only meaningful when the\n+ * property has the type &DRM_MODE_PROP_ENUM or &DRM_MODE_PROP_BITMASK. For\n+ * backwards compatibility, the kernel will always set @count_enum_blobs to\n+ * zero when the property has the type &DRM_MODE_PROP_BLOB. User-space must\n+ * ignore these two fields if the property has a different type.\n+ *\n+ * User-space is expected to retrieve values and enums by performing this ioctl\n+ * at least twice: the first time to retrieve the number of elements, the\n+ * second time to retrieve the elements themselves.\n+ *\n+ * To retrieve the number of elements, set @count_values and @count_enum_blobs\n+ * to zero, then call the ioctl. @count_values will be updated with the number\n+ * of elements. If the property has the type &DRM_MODE_PROP_ENUM or\n+ * &DRM_MODE_PROP_BITMASK, @count_enum_blobs will be updated as well.\n+ *\n+ * To retrieve the elements themselves, allocate an array for @values_ptr and\n+ * set @count_values to its capacity. If the property has the type\n+ * &DRM_MODE_PROP_ENUM or &DRM_MODE_PROP_BITMASK, allocate an array for\n+ * @enum_blob_ptr and set @count_enum_blobs to its capacity. Calling the ioctl\n+ * again will fill the arrays.\n+ */\n+struct drm_mode_get_property {\n+\t/** @values_ptr: Pointer to a ``__u64`` array. */\n+\t__u64 values_ptr;\n+\t/** @enum_blob_ptr: Pointer to a struct drm_mode_property_enum array. */\n+\t__u64 enum_blob_ptr;\n+\n+\t/**\n+\t * @prop_id: Object ID of the property which should be retrieved. Set\n+\t * by the caller.\n+\t */\n+\t__u32 prop_id;\n+\t/**\n+\t * @flags: ``DRM_MODE_PROP_*`` bitfield. See &drm_property.flags for\n+\t * a definition of the flags.\n+\t */\n+\t__u32 flags;\n+\t/**\n+\t * @name: Symbolic property name. User-space should use this field to\n+\t * recognize properties.\n+\t */\n+\tchar name[DRM_PROP_NAME_LEN];\n+\n+\t/** @count_values: Number of elements in @values_ptr. */\n+\t__u32 count_values;\n+\t/** @count_enum_blobs: Number of elements in @enum_blob_ptr. */\n+\t__u32 count_enum_blobs;\n+};\n+\n+struct drm_mode_connector_set_property {\n+\t__u64 value;\n+\t__u32 prop_id;\n+\t__u32 connector_id;\n+};\n+\n+#define DRM_MODE_OBJECT_CRTC 0xcccccccc\n+#define DRM_MODE_OBJECT_CONNECTOR 0xc0c0c0c0\n+#define DRM_MODE_OBJECT_ENCODER 0xe0e0e0e0\n+#define DRM_MODE_OBJECT_MODE 0xdededede\n+#define DRM_MODE_OBJECT_PROPERTY 0xb0b0b0b0\n+#define DRM_MODE_OBJECT_FB 0xfbfbfbfb\n+#define DRM_MODE_OBJECT_BLOB 0xbbbbbbbb\n+#define DRM_MODE_OBJECT_PLANE 0xeeeeeeee\n+#define DRM_MODE_OBJECT_COLOROP 0xfafafafa\n+#define DRM_MODE_OBJECT_ANY 0\n+\n+struct drm_mode_obj_get_properties {\n+\t__u64 props_ptr;\n+\t__u64 prop_values_ptr;\n+\t__u32 count_props;\n+\t__u32 obj_id;\n+\t__u32 obj_type;\n+};\n+\n+struct drm_mode_obj_set_property {\n+\t__u64 value;\n+\t__u32 prop_id;\n+\t__u32 obj_id;\n+\t__u32 obj_type;\n+};\n+\n+struct drm_mode_get_blob {\n+\t__u32 blob_id;\n+\t__u32 length;\n+\t__u64 data;\n+};\n+\n+struct drm_mode_fb_cmd {\n+\t__u32 fb_id;\n+\t__u32 width;\n+\t__u32 height;\n+\t__u32 pitch;\n+\t__u32 bpp;\n+\t__u32 depth;\n+\t/* driver specific handle */\n+\t__u32 handle;\n+};\n+\n+#define DRM_MODE_FB_INTERLACED\t(1<<0) /* for interlaced framebuffers */\n+#define DRM_MODE_FB_MODIFIERS\t(1<<1) /* enables ->modifier[] */\n+\n+/**\n+ * struct drm_mode_fb_cmd2 - Frame-buffer metadata.\n+ *\n+ * This struct holds frame-buffer metadata. There are two ways to use it:\n+ *\n+ * - User-space can fill this struct and perform a &DRM_IOCTL_MODE_ADDFB2\n+ * ioctl to register a new frame-buffer. The new frame-buffer object ID will\n+ * be set by the kernel in @fb_id.\n+ * - User-space can set @fb_id and perform a &DRM_IOCTL_MODE_GETFB2 ioctl to\n+ * fetch metadata about an existing frame-buffer.\n+ *\n+ * In case of planar formats, this struct allows up to 4 buffer objects with\n+ * offsets and pitches per plane. The pitch and offset order are dictated by\n+ * the format FourCC as defined by ``drm_fourcc.h``, e.g. NV12 is described as:\n+ *\n+ * YUV 4:2:0 image with a plane of 8-bit Y samples followed by an\n+ * interleaved U/V plane containing 8-bit 2x2 subsampled colour difference\n+ * samples.\n+ *\n+ * So it would consist of a Y plane at ``offsets[0]`` and a UV plane at\n+ * ``offsets[1]``.\n+ *\n+ * To accommodate tiled, compressed, etc formats, a modifier can be specified.\n+ * For more information see the \"Format Modifiers\" section. Note that even\n+ * though it looks like we have a modifier per-plane, we in fact do not. The\n+ * modifier for each plane must be identical. Thus all combinations of\n+ * different data layouts for multi-plane formats must be enumerated as\n+ * separate modifiers.\n+ *\n+ * All of the entries in @handles, @pitches, @offsets and @modifier must be\n+ * zero when unused. Warning, for @offsets and @modifier zero can't be used to\n+ * figure out whether the entry is used or not since it's a valid value (a zero\n+ * offset is common, and a zero modifier is &DRM_FORMAT_MOD_LINEAR).\n+ */\n+struct drm_mode_fb_cmd2 {\n+\t/** @fb_id: Object ID of the frame-buffer. */\n+\t__u32 fb_id;\n+\t/** @width: Width of the frame-buffer. */\n+\t__u32 width;\n+\t/** @height: Height of the frame-buffer. */\n+\t__u32 height;\n+\t/**\n+\t * @pixel_format: FourCC format code, see ``DRM_FORMAT_*`` constants in\n+\t * ``drm_fourcc.h``.\n+\t */\n+\t__u32 pixel_format;\n+\t/**\n+\t * @flags: Frame-buffer flags (see &DRM_MODE_FB_INTERLACED and\n+\t * &DRM_MODE_FB_MODIFIERS).\n+\t */\n+\t__u32 flags;\n+\n+\t/**\n+\t * @handles: GEM buffer handle, one per plane. Set to 0 if the plane is\n+\t * unused. The same handle can be used for multiple planes.\n+\t */\n+\t__u32 handles[4];\n+\t/** @pitches: Pitch (aka. stride) in bytes, one per plane. */\n+\t__u32 pitches[4];\n+\t/** @offsets: Offset into the buffer in bytes, one per plane. */\n+\t__u32 offsets[4];\n+\t/**\n+\t * @modifier: Format modifier, one per plane. See ``DRM_FORMAT_MOD_*``\n+\t * constants in ``drm_fourcc.h``. All planes must use the same\n+\t * modifier. Ignored unless &DRM_MODE_FB_MODIFIERS is set in @flags.\n+\t */\n+\t__u64 modifier[4];\n+};\n+\n+#define DRM_MODE_FB_DIRTY_ANNOTATE_COPY 0x01\n+#define DRM_MODE_FB_DIRTY_ANNOTATE_FILL 0x02\n+#define DRM_MODE_FB_DIRTY_FLAGS 0x03\n+\n+#define DRM_MODE_FB_DIRTY_MAX_CLIPS 256\n+\n+/*\n+ * Mark a region of a framebuffer as dirty.\n+ *\n+ * Some hardware does not automatically update display contents\n+ * as a hardware or software draw to a framebuffer. This ioctl\n+ * allows userspace to tell the kernel and the hardware what\n+ * regions of the framebuffer have changed.\n+ *\n+ * The kernel or hardware is free to update more then just the\n+ * region specified by the clip rects. The kernel or hardware\n+ * may also delay and/or coalesce several calls to dirty into a\n+ * single update.\n+ *\n+ * Userspace may annotate the updates, the annotates are a\n+ * promise made by the caller that the change is either a copy\n+ * of pixels or a fill of a single color in the region specified.\n+ *\n+ * If the DRM_MODE_FB_DIRTY_ANNOTATE_COPY flag is given then\n+ * the number of updated regions are half of num_clips given,\n+ * where the clip rects are paired in src and dst. The width and\n+ * height of each one of the pairs must match.\n+ *\n+ * If the DRM_MODE_FB_DIRTY_ANNOTATE_FILL flag is given the caller\n+ * promises that the region specified of the clip rects is filled\n+ * completely with a single color as given in the color argument.\n+ */\n+\n+struct drm_mode_fb_dirty_cmd {\n+\t__u32 fb_id;\n+\t__u32 flags;\n+\t__u32 color;\n+\t__u32 num_clips;\n+\t__u64 clips_ptr;\n+};\n+\n+struct drm_mode_mode_cmd {\n+\t__u32 connector_id;\n+\tstruct drm_mode_modeinfo mode;\n+};\n+\n+#define DRM_MODE_CURSOR_BO\t0x01\n+#define DRM_MODE_CURSOR_MOVE\t0x02\n+#define DRM_MODE_CURSOR_FLAGS\t0x03\n+\n+/*\n+ * depending on the value in flags different members are used.\n+ *\n+ * CURSOR_BO uses\n+ * crtc_id\n+ * width\n+ * height\n+ * handle - if 0 turns the cursor off\n+ *\n+ * CURSOR_MOVE uses\n+ * crtc_id\n+ * x\n+ * y\n+ */\n+struct drm_mode_cursor {\n+\t__u32 flags;\n+\t__u32 crtc_id;\n+\t__s32 x;\n+\t__s32 y;\n+\t__u32 width;\n+\t__u32 height;\n+\t/* driver specific handle */\n+\t__u32 handle;\n+};\n+\n+struct drm_mode_cursor2 {\n+\t__u32 flags;\n+\t__u32 crtc_id;\n+\t__s32 x;\n+\t__s32 y;\n+\t__u32 width;\n+\t__u32 height;\n+\t/* driver specific handle */\n+\t__u32 handle;\n+\t__s32 hot_x;\n+\t__s32 hot_y;\n+};\n+\n+struct drm_mode_crtc_lut {\n+\t__u32 crtc_id;\n+\t__u32 gamma_size;\n+\n+\t/* pointers to arrays */\n+\t__u64 red;\n+\t__u64 green;\n+\t__u64 blue;\n+};\n+\n+struct drm_color_ctm {\n+\t/*\n+\t * Conversion matrix in S31.32 sign-magnitude\n+\t * (not two's complement!) format.\n+\t *\n+\t * out matrix in\n+\t * |R| |0 1 2| |R|\n+\t * |G| = |3 4 5| x |G|\n+\t * |B| |6 7 8| |B|\n+\t */\n+\t__u64 matrix[9];\n+};\n+\n+struct drm_color_ctm_3x4 {\n+\t/*\n+\t * Conversion matrix with 3x4 dimensions in S31.32 sign-magnitude\n+\t * (not two's complement!) format.\n+\t *\n+\t * out matrix in\n+\t * |R| |0 1 2 3 | | R |\n+\t * |G| = |4 5 6 7 | x | G |\n+\t * |B| |8 9 10 11| | B |\n+\t * |1.0|\n+\t */\n+\t__u64 matrix[12];\n+};\n+\n+struct drm_color_lut {\n+\t/*\n+\t * Values are mapped linearly to 0.0 - 1.0 range, with 0x0 == 0.0 and\n+\t * 0xffff == 1.0.\n+\t */\n+\t__u16 red;\n+\t__u16 green;\n+\t__u16 blue;\n+\t__u16 reserved;\n+};\n+\n+/*\n+ * struct drm_color_lut32\n+ *\n+ * 32-bit per channel color LUT entry, similar to drm_color_lut.\n+ */\n+struct drm_color_lut32 {\n+\t__u32 red;\n+\t__u32 green;\n+\t__u32 blue;\n+\t__u32 reserved;\n+};\n+\n+/**\n+ * enum drm_colorop_type - Type of color operation\n+ *\n+ * drm_colorops can be of many different types. Each type behaves differently\n+ * and defines a different set of properties. This enum defines all types and\n+ * gives a high-level description.\n+ */\n+enum drm_colorop_type {\n+\t/**\n+\t * @DRM_COLOROP_1D_CURVE:\n+\t *\n+\t * enum string \"1D Curve\"\n+\t *\n+\t * A 1D curve that is being applied to all color channels. The\n+\t * curve is specified via the CURVE_1D_TYPE colorop property.\n+\t */\n+\tDRM_COLOROP_1D_CURVE,\n+\n+\t/**\n+\t * @DRM_COLOROP_1D_LUT:\n+\t *\n+\t * enum string \"1D LUT\"\n+\t *\n+\t * A simple 1D LUT of uniformly spaced &drm_color_lut32 entries,\n+\t * packed into a blob via the DATA property. The driver's\n+\t * expected LUT size is advertised via the SIZE property.\n+\t *\n+\t * The DATA blob is an array of struct drm_color_lut32 with size\n+\t * of \"size\".\n+\t */\n+\tDRM_COLOROP_1D_LUT,\n+\n+\t/**\n+\t * @DRM_COLOROP_CTM_3X4:\n+\t *\n+\t * enum string \"3x4 Matrix\"\n+\t *\n+\t * A 3x4 matrix. Its values are specified via the\n+\t * &drm_color_ctm_3x4 struct provided via the DATA property.\n+\t *\n+\t * The DATA blob is a float[12]:\n+\t * out matrix in\n+\t * | R | | 0 1 2 3 | | R |\n+\t * | G | = | 4 5 6 7 | x | G |\n+\t * | B | | 8 9 10 12 | | B |\n+\t */\n+\tDRM_COLOROP_CTM_3X4,\n+\n+\t/**\n+\t * @DRM_COLOROP_MULTIPLIER:\n+\t *\n+\t * enum string \"Multiplier\"\n+\t *\n+\t * A simple multiplier, applied to all color values. The\n+\t * multiplier is specified as a S31.32 via the MULTIPLIER\n+\t * property.\n+\t */\n+\tDRM_COLOROP_MULTIPLIER,\n+\n+\t/**\n+\t * @DRM_COLOROP_3D_LUT:\n+\t *\n+\t * enum string \"3D LUT\"\n+\t *\n+\t * A 3D LUT of &drm_color_lut32 entries,\n+\t * packed into a blob via the DATA property. The driver's expected\n+\t * LUT size is advertised via the SIZE property, i.e., a 3D LUT with\n+\t * 17x17x17 entries will have SIZE set to 17.\n+\t *\n+\t * The DATA blob is a 3D array of struct drm_color_lut32 with dimension\n+\t * length of \"size\".\n+\t * The LUT elements are traversed like so:\n+\t *\n+\t * for B in range 0..n\n+\t * for G in range 0..n\n+\t * for R in range 0..n\n+\t * index = R + n * (G + n * B)\n+\t * color = lut3d[index]\n+\t */\n+\tDRM_COLOROP_3D_LUT,\n+};\n+\n+/**\n+ * enum drm_colorop_lut3d_interpolation_type - type of 3DLUT interpolation\n+ */\n+enum drm_colorop_lut3d_interpolation_type {\n+\t/**\n+\t * @DRM_COLOROP_LUT3D_INTERPOLATION_TETRAHEDRAL:\n+\t *\n+\t * Tetrahedral 3DLUT interpolation\n+\t */\n+\tDRM_COLOROP_LUT3D_INTERPOLATION_TETRAHEDRAL,\n+};\n+\n+/**\n+ * enum drm_colorop_lut1d_interpolation_type - type of interpolation for 1D LUTs\n+ */\n+enum drm_colorop_lut1d_interpolation_type {\n+\t/**\n+\t * @DRM_COLOROP_LUT1D_INTERPOLATION_LINEAR:\n+\t *\n+\t * Linear interpolation. Values between points of the LUT will be\n+\t * linearly interpolated.\n+\t */\n+\tDRM_COLOROP_LUT1D_INTERPOLATION_LINEAR,\n+};\n+\n+/**\n+ * struct drm_plane_size_hint - Plane size hints\n+ * @width: The width of the plane in pixel\n+ * @height: The height of the plane in pixel\n+ *\n+ * The plane SIZE_HINTS property blob contains an\n+ * array of struct drm_plane_size_hint.\n+ */\n+struct drm_plane_size_hint {\n+\t__u16 width;\n+\t__u16 height;\n+};\n+\n+/**\n+ * struct hdr_metadata_infoframe - HDR Metadata Infoframe Data.\n+ *\n+ * HDR Metadata Infoframe as per CTA 861.G spec. This is expected\n+ * to match exactly with the spec.\n+ *\n+ * Userspace is expected to pass the metadata information as per\n+ * the format described in this structure.\n+ */\n+struct hdr_metadata_infoframe {\n+\t/**\n+\t * @eotf: Electro-Optical Transfer Function (EOTF)\n+\t * used in the stream.\n+\t */\n+\t__u8 eotf;\n+\t/**\n+\t * @metadata_type: Static_Metadata_Descriptor_ID.\n+\t */\n+\t__u8 metadata_type;\n+\t/**\n+\t * @display_primaries: Color Primaries of the Data.\n+\t * These are coded as unsigned 16-bit values in units of\n+\t * 0.00002, where 0x0000 represents zero and 0xC350\n+\t * represents 1.0000.\n+\t * @display_primaries.x: X coordinate of color primary.\n+\t * @display_primaries.y: Y coordinate of color primary.\n+\t */\n+\tstruct {\n+\t\t__u16 x, y;\n+\t} display_primaries[3];\n+\t/**\n+\t * @white_point: White Point of Colorspace Data.\n+\t * These are coded as unsigned 16-bit values in units of\n+\t * 0.00002, where 0x0000 represents zero and 0xC350\n+\t * represents 1.0000.\n+\t * @white_point.x: X coordinate of whitepoint of color primary.\n+\t * @white_point.y: Y coordinate of whitepoint of color primary.\n+\t */\n+\tstruct {\n+\t\t__u16 x, y;\n+\t} white_point;\n+\t/**\n+\t * @max_display_mastering_luminance: Max Mastering Display Luminance.\n+\t * This value is coded as an unsigned 16-bit value in units of 1 cd/m2,\n+\t * where 0x0001 represents 1 cd/m2 and 0xFFFF represents 65535 cd/m2.\n+\t */\n+\t__u16 max_display_mastering_luminance;\n+\t/**\n+\t * @min_display_mastering_luminance: Min Mastering Display Luminance.\n+\t * This value is coded as an unsigned 16-bit value in units of\n+\t * 0.0001 cd/m2, where 0x0001 represents 0.0001 cd/m2 and 0xFFFF\n+\t * represents 6.5535 cd/m2.\n+\t */\n+\t__u16 min_display_mastering_luminance;\n+\t/**\n+\t * @max_cll: Max Content Light Level.\n+\t * This value is coded as an unsigned 16-bit value in units of 1 cd/m2,\n+\t * where 0x0001 represents 1 cd/m2 and 0xFFFF represents 65535 cd/m2.\n+\t */\n+\t__u16 max_cll;\n+\t/**\n+\t * @max_fall: Max Frame Average Light Level.\n+\t * This value is coded as an unsigned 16-bit value in units of 1 cd/m2,\n+\t * where 0x0001 represents 1 cd/m2 and 0xFFFF represents 65535 cd/m2.\n+\t */\n+\t__u16 max_fall;\n+};\n+\n+/**\n+ * struct hdr_output_metadata - HDR output metadata\n+ *\n+ * Metadata Information to be passed from userspace\n+ */\n+struct hdr_output_metadata {\n+\t/**\n+\t * @metadata_type: Static_Metadata_Descriptor_ID.\n+\t */\n+\t__u32 metadata_type;\n+\t/**\n+\t * @hdmi_metadata_type1: HDR Metadata Infoframe.\n+\t */\n+\tunion {\n+\t\tstruct hdr_metadata_infoframe hdmi_metadata_type1;\n+\t};\n+};\n+\n+/**\n+ * DRM_MODE_PAGE_FLIP_EVENT\n+ *\n+ * Request that the kernel sends back a vblank event (see\n+ * struct drm_event_vblank) with the &DRM_EVENT_FLIP_COMPLETE type when the\n+ * page-flip is done.\n+ *\n+ * When used with atomic uAPI, one event will be delivered per CRTC included in\n+ * the atomic commit. A CRTC is included in an atomic commit if one of its\n+ * properties is set, or if a property is set on a connector or plane linked\n+ * via the CRTC_ID property to the CRTC. At least one CRTC must be included,\n+ * and all pulled in CRTCs must be either previously or newly powered on (in\n+ * other words, a powered off CRTC which stays off cannot be included in the\n+ * atomic commit).\n+ */\n+#define DRM_MODE_PAGE_FLIP_EVENT 0x01\n+/**\n+ * DRM_MODE_PAGE_FLIP_ASYNC\n+ *\n+ * Request that the page-flip is performed as soon as possible, ie. with no\n+ * delay due to waiting for vblank. This may cause tearing to be visible on\n+ * the screen.\n+ *\n+ * When used with atomic uAPI, the driver will return an error if the hardware\n+ * doesn't support performing an asynchronous page-flip for this update.\n+ * User-space should handle this, e.g. by falling back to a regular page-flip.\n+ *\n+ * Note, some hardware might need to perform one last synchronous page-flip\n+ * before being able to switch to asynchronous page-flips. As an exception,\n+ * the driver will return success even though that first page-flip is not\n+ * asynchronous.\n+ */\n+#define DRM_MODE_PAGE_FLIP_ASYNC 0x02\n+#define DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE 0x4\n+#define DRM_MODE_PAGE_FLIP_TARGET_RELATIVE 0x8\n+#define DRM_MODE_PAGE_FLIP_TARGET (DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE | \\\n+\t\t\t\t DRM_MODE_PAGE_FLIP_TARGET_RELATIVE)\n+/**\n+ * DRM_MODE_PAGE_FLIP_FLAGS\n+ *\n+ * Bitmask of flags suitable for &drm_mode_crtc_page_flip_target.flags.\n+ */\n+#define DRM_MODE_PAGE_FLIP_FLAGS (DRM_MODE_PAGE_FLIP_EVENT | \\\n+\t\t\t\t DRM_MODE_PAGE_FLIP_ASYNC | \\\n+\t\t\t\t DRM_MODE_PAGE_FLIP_TARGET)\n+\n+/*\n+ * Request a page flip on the specified crtc.\n+ *\n+ * This ioctl will ask KMS to schedule a page flip for the specified\n+ * crtc. Once any pending rendering targeting the specified fb (as of\n+ * ioctl time) has completed, the crtc will be reprogrammed to display\n+ * that fb after the next vertical refresh. The ioctl returns\n+ * immediately, but subsequent rendering to the current fb will block\n+ * in the execbuffer ioctl until the page flip happens. If a page\n+ * flip is already pending as the ioctl is called, EBUSY will be\n+ * returned.\n+ *\n+ * Flag DRM_MODE_PAGE_FLIP_EVENT requests that drm sends back a vblank\n+ * event (see drm.h: struct drm_event_vblank) when the page flip is\n+ * done. The user_data field passed in with this ioctl will be\n+ * returned as the user_data field in the vblank event struct.\n+ *\n+ * Flag DRM_MODE_PAGE_FLIP_ASYNC requests that the flip happen\n+ * 'as soon as possible', meaning that it not delay waiting for vblank.\n+ * This may cause tearing on the screen.\n+ *\n+ * The reserved field must be zero.\n+ */\n+\n+struct drm_mode_crtc_page_flip {\n+\t__u32 crtc_id;\n+\t__u32 fb_id;\n+\t__u32 flags;\n+\t__u32 reserved;\n+\t__u64 user_data;\n+};\n+\n+/*\n+ * Request a page flip on the specified crtc.\n+ *\n+ * Same as struct drm_mode_crtc_page_flip, but supports new flags and\n+ * re-purposes the reserved field:\n+ *\n+ * The sequence field must be zero unless either of the\n+ * DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE/RELATIVE flags is specified. When\n+ * the ABSOLUTE flag is specified, the sequence field denotes the absolute\n+ * vblank sequence when the flip should take effect. When the RELATIVE\n+ * flag is specified, the sequence field denotes the relative (to the\n+ * current one when the ioctl is called) vblank sequence when the flip\n+ * should take effect. NOTE: DRM_IOCTL_WAIT_VBLANK must still be used to\n+ * make sure the vblank sequence before the target one has passed before\n+ * calling this ioctl. The purpose of the\n+ * DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE/RELATIVE flags is merely to clarify\n+ * the target for when code dealing with a page flip runs during a\n+ * vertical blank period.\n+ */\n+\n+struct drm_mode_crtc_page_flip_target {\n+\t__u32 crtc_id;\n+\t__u32 fb_id;\n+\t__u32 flags;\n+\t__u32 sequence;\n+\t__u64 user_data;\n+};\n+\n+/**\n+ * struct drm_mode_create_dumb - Create a KMS dumb buffer for scanout.\n+ * @height: buffer height in pixels\n+ * @width: buffer width in pixels\n+ * @bpp: color mode\n+ * @flags: must be zero\n+ * @handle: buffer object handle\n+ * @pitch: number of bytes between two consecutive lines\n+ * @size: size of the whole buffer in bytes\n+ *\n+ * User-space fills @height, @width, @bpp and @flags. If the IOCTL succeeds,\n+ * the kernel fills @handle, @pitch and @size.\n+ *\n+ * The value of @bpp is a color-mode number describing a specific format\n+ * or a variant thereof. The value often corresponds to the number of bits\n+ * per pixel for most modes, although there are exceptions. Each color mode\n+ * maps to a DRM format plus a number of modes with similar pixel layout.\n+ * Framebuffer layout is always linear.\n+ *\n+ * Support for all modes and formats is optional. Even if dumb-buffer\n+ * creation with a certain color mode succeeds, it is not guaranteed that\n+ * the DRM driver supports any of the related formats. Most drivers support\n+ * a color mode of 32 with a format of DRM_FORMAT_XRGB8888 on their primary\n+ * plane.\n+ *\n+ * +------------+------------------------+------------------------+\n+ * | Color mode | Framebuffer format | Compatible formats |\n+ * +============+========================+========================+\n+ * | 32 | * DRM_FORMAT_XRGB8888 | * DRM_FORMAT_BGRX8888 |\n+ * | | | * DRM_FORMAT_RGBX8888 |\n+ * | | | * DRM_FORMAT_XBGR8888 |\n+ * +------------+------------------------+------------------------+\n+ * | 24 | * DRM_FORMAT_RGB888 | * DRM_FORMAT_BGR888 |\n+ * +------------+------------------------+------------------------+\n+ * | 16 | * DRM_FORMAT_RGB565 | * DRM_FORMAT_BGR565 |\n+ * +------------+------------------------+------------------------+\n+ * | 15 | * DRM_FORMAT_XRGB1555 | * DRM_FORMAT_BGRX1555 |\n+ * | | | * DRM_FORMAT_RGBX1555 |\n+ * | | | * DRM_FORMAT_XBGR1555 |\n+ * +------------+------------------------+------------------------+\n+ * | 8 | * DRM_FORMAT_C8 | * DRM_FORMAT_D8 |\n+ * | | | * DRM_FORMAT_R8 |\n+ * +------------+------------------------+------------------------+\n+ * | 4 | * DRM_FORMAT_C4 | * DRM_FORMAT_D4 |\n+ * | | | * DRM_FORMAT_R4 |\n+ * +------------+------------------------+------------------------+\n+ * | 2 | * DRM_FORMAT_C2 | * DRM_FORMAT_D2 |\n+ * | | | * DRM_FORMAT_R2 |\n+ * +------------+------------------------+------------------------+\n+ * | 1 | * DRM_FORMAT_C1 | * DRM_FORMAT_D1 |\n+ * | | | * DRM_FORMAT_R1 |\n+ * +------------+------------------------+------------------------+\n+ *\n+ * Color modes of 10, 12, 15, 30 and 64 are only supported for use by\n+ * legacy user space. Please don't use them in new code. Other modes\n+ * are not support.\n+ *\n+ * Do not attempt to allocate anything but linear framebuffer memory\n+ * with single-plane RGB data. Allocation of other framebuffer\n+ * layouts requires dedicated ioctls in the respective DRM driver.\n+ */\n+struct drm_mode_create_dumb {\n+\t__u32 height;\n+\t__u32 width;\n+\t__u32 bpp;\n+\t__u32 flags;\n+\n+\t__u32 handle;\n+\t__u32 pitch;\n+\t__u64 size;\n+};\n+\n+/* set up for mmap of a dumb scanout buffer */\n+struct drm_mode_map_dumb {\n+\t/** Handle for the object being mapped. */\n+\t__u32 handle;\n+\t__u32 pad;\n+\t/**\n+\t * Fake offset to use for subsequent mmap call\n+\t *\n+\t * This is a fixed-size type for 32/64 compatibility.\n+\t */\n+\t__u64 offset;\n+};\n+\n+struct drm_mode_destroy_dumb {\n+\t__u32 handle;\n+};\n+\n+/**\n+ * DRM_MODE_ATOMIC_TEST_ONLY\n+ *\n+ * Do not apply the atomic commit, instead check whether the hardware supports\n+ * this configuration.\n+ *\n+ * See &drm_mode_config_funcs.atomic_check for more details on test-only\n+ * commits.\n+ */\n+#define DRM_MODE_ATOMIC_TEST_ONLY 0x0100\n+/**\n+ * DRM_MODE_ATOMIC_NONBLOCK\n+ *\n+ * Do not block while applying the atomic commit. The &DRM_IOCTL_MODE_ATOMIC\n+ * IOCTL returns immediately instead of waiting for the changes to be applied\n+ * in hardware. Note, the driver will still check that the update can be\n+ * applied before retuning.\n+ */\n+#define DRM_MODE_ATOMIC_NONBLOCK 0x0200\n+/**\n+ * DRM_MODE_ATOMIC_ALLOW_MODESET\n+ *\n+ * Allow the update to result in temporary or transient visible artifacts while\n+ * the update is being applied. Applying the update may also take significantly\n+ * more time than a page flip. All visual artifacts will disappear by the time\n+ * the update is completed, as signalled through the vblank event's timestamp\n+ * (see struct drm_event_vblank).\n+ *\n+ * This flag must be set when the KMS update might cause visible artifacts.\n+ * Without this flag such KMS update will return a EINVAL error. What kind of\n+ * update may cause visible artifacts depends on the driver and the hardware.\n+ * User-space that needs to know beforehand if an update might cause visible\n+ * artifacts can use &DRM_MODE_ATOMIC_TEST_ONLY without\n+ * &DRM_MODE_ATOMIC_ALLOW_MODESET to see if it fails.\n+ *\n+ * To the best of the driver's knowledge, visual artifacts are guaranteed to\n+ * not appear when this flag is not set. Some sinks might display visual\n+ * artifacts outside of the driver's control.\n+ */\n+#define DRM_MODE_ATOMIC_ALLOW_MODESET 0x0400\n+\n+/**\n+ * DRM_MODE_ATOMIC_FLAGS\n+ *\n+ * Bitfield of flags accepted by the &DRM_IOCTL_MODE_ATOMIC IOCTL in\n+ * &drm_mode_atomic.flags.\n+ */\n+#define DRM_MODE_ATOMIC_FLAGS (\\\n+\t\tDRM_MODE_PAGE_FLIP_EVENT |\\\n+\t\tDRM_MODE_PAGE_FLIP_ASYNC |\\\n+\t\tDRM_MODE_ATOMIC_TEST_ONLY |\\\n+\t\tDRM_MODE_ATOMIC_NONBLOCK |\\\n+\t\tDRM_MODE_ATOMIC_ALLOW_MODESET)\n+\n+struct drm_mode_atomic {\n+\t__u32 flags;\n+\t__u32 count_objs;\n+\t__u64 objs_ptr;\n+\t__u64 count_props_ptr;\n+\t__u64 props_ptr;\n+\t__u64 prop_values_ptr;\n+\t__u64 reserved;\n+\t__u64 user_data;\n+};\n+\n+struct drm_format_modifier_blob {\n+#define FORMAT_BLOB_CURRENT 1\n+\t/* Version of this blob format */\n+\t__u32 version;\n+\n+\t/* Flags */\n+\t__u32 flags;\n+\n+\t/* Number of fourcc formats supported */\n+\t__u32 count_formats;\n+\n+\t/* Where in this blob the formats exist (in bytes) */\n+\t__u32 formats_offset;\n+\n+\t/* Number of drm_format_modifiers */\n+\t__u32 count_modifiers;\n+\n+\t/* Where in this blob the modifiers exist (in bytes) */\n+\t__u32 modifiers_offset;\n+\n+\t/* __u32 formats[] */\n+\t/* struct drm_format_modifier modifiers[] */\n+};\n+\n+struct drm_format_modifier {\n+\t/* Bitmask of formats in get_plane format list this info applies to. The\n+\t * offset allows a sliding window of which 64 formats (bits).\n+\t *\n+\t * Some examples:\n+\t * In today's world with < 65 formats, and formats 0, and 2 are\n+\t * supported\n+\t * 0x0000000000000005\n+\t *\t\t ^-offset = 0, formats = 5\n+\t *\n+\t * If the number formats grew to 128, and formats 98-102 are\n+\t * supported with the modifier:\n+\t *\n+\t * 0x0000007c00000000 0000000000000000\n+\t *\t\t ^\n+\t *\t\t |__offset = 64, formats = 0x7c00000000\n+\t *\n+\t */\n+\t__u64 formats;\n+\t__u32 offset;\n+\t__u32 pad;\n+\n+\t/* The modifier that applies to the >get_plane format list bitmask. */\n+\t__u64 modifier;\n+};\n+\n+/**\n+ * struct drm_mode_create_blob - Create New blob property\n+ *\n+ * Create a new 'blob' data property, copying length bytes from data pointer,\n+ * and returning new blob ID.\n+ */\n+struct drm_mode_create_blob {\n+\t/** @data: Pointer to data to copy. */\n+\t__u64 data;\n+\t/** @length: Length of data to copy. */\n+\t__u32 length;\n+\t/** @blob_id: Return: new property ID. */\n+\t__u32 blob_id;\n+};\n+\n+/**\n+ * struct drm_mode_destroy_blob - Destroy user blob\n+ * @blob_id: blob_id to destroy\n+ *\n+ * Destroy a user-created blob property.\n+ *\n+ * User-space can release blobs as soon as they do not need to refer to them by\n+ * their blob object ID. For instance, if you are using a MODE_ID blob in an\n+ * atomic commit and you will not make another commit re-using the same ID, you\n+ * can destroy the blob as soon as the commit has been issued, without waiting\n+ * for it to complete.\n+ */\n+struct drm_mode_destroy_blob {\n+\t__u32 blob_id;\n+};\n+\n+/**\n+ * struct drm_mode_create_lease - Create lease\n+ *\n+ * Lease mode resources, creating another drm_master.\n+ *\n+ * The @object_ids array must reference at least one CRTC, one connector and\n+ * one plane if &DRM_CLIENT_CAP_UNIVERSAL_PLANES is enabled. Alternatively,\n+ * the lease can be completely empty.\n+ */\n+struct drm_mode_create_lease {\n+\t/** @object_ids: Pointer to array of object ids (__u32) */\n+\t__u64 object_ids;\n+\t/** @object_count: Number of object ids */\n+\t__u32 object_count;\n+\t/** @flags: flags for new FD (O_CLOEXEC, etc) */\n+\t__u32 flags;\n+\n+\t/** @lessee_id: Return: unique identifier for lessee. */\n+\t__u32 lessee_id;\n+\t/** @fd: Return: file descriptor to new drm_master file */\n+\t__u32 fd;\n+};\n+\n+/**\n+ * struct drm_mode_list_lessees - List lessees\n+ *\n+ * List lesses from a drm_master.\n+ */\n+struct drm_mode_list_lessees {\n+\t/**\n+\t * @count_lessees: Number of lessees.\n+\t *\n+\t * On input, provides length of the array.\n+\t * On output, provides total number. No\n+\t * more than the input number will be written\n+\t * back, so two calls can be used to get\n+\t * the size and then the data.\n+\t */\n+\t__u32 count_lessees;\n+\t/** @pad: Padding. */\n+\t__u32 pad;\n+\n+\t/**\n+\t * @lessees_ptr: Pointer to lessees.\n+\t *\n+\t * Pointer to __u64 array of lessee ids\n+\t */\n+\t__u64 lessees_ptr;\n+};\n+\n+/**\n+ * struct drm_mode_get_lease - Get Lease\n+ *\n+ * Get leased objects.\n+ */\n+struct drm_mode_get_lease {\n+\t/**\n+\t * @count_objects: Number of leased objects.\n+\t *\n+\t * On input, provides length of the array.\n+\t * On output, provides total number. No\n+\t * more than the input number will be written\n+\t * back, so two calls can be used to get\n+\t * the size and then the data.\n+\t */\n+\t__u32 count_objects;\n+\t/** @pad: Padding. */\n+\t__u32 pad;\n+\n+\t/**\n+\t * @objects_ptr: Pointer to objects.\n+\t *\n+\t * Pointer to __u32 array of object ids.\n+\t */\n+\t__u64 objects_ptr;\n+};\n+\n+/**\n+ * struct drm_mode_revoke_lease - Revoke lease\n+ */\n+struct drm_mode_revoke_lease {\n+\t/** @lessee_id: Unique ID of lessee */\n+\t__u32 lessee_id;\n+};\n+\n+/**\n+ * struct drm_mode_rect - Two dimensional rectangle.\n+ * @x1: Horizontal starting coordinate (inclusive).\n+ * @y1: Vertical starting coordinate (inclusive).\n+ * @x2: Horizontal ending coordinate (exclusive).\n+ * @y2: Vertical ending coordinate (exclusive).\n+ *\n+ * With drm subsystem using struct drm_rect to manage rectangular area this\n+ * export it to user-space.\n+ *\n+ * Currently used by drm_mode_atomic blob property FB_DAMAGE_CLIPS.\n+ */\n+struct drm_mode_rect {\n+\t__s32 x1;\n+\t__s32 y1;\n+\t__s32 x2;\n+\t__s32 y2;\n+};\n+\n+/**\n+ * struct drm_mode_closefb\n+ * @fb_id: Framebuffer ID.\n+ * @pad: Must be zero.\n+ */\n+struct drm_mode_closefb {\n+\t__u32 fb_id;\n+\t__u32 pad;\n+};\n+\n+#if defined(__cplusplus)\n+}\n+#endif\n+\n+#endif\ndiff --git a/include/linux/rkisp1-config.h b/include/linux/rkisp1-config.h\nindex d323bfa72d8e..3e8aa77fde18 100644\n--- a/include/linux/rkisp1-config.h\n+++ b/include/linux/rkisp1-config.h\n@@ -9,6 +9,8 @@\n \n #include \n \n+#include \n+\n /* Defect Pixel Cluster Detection */\n #define RKISP1_CIF_ISP_MODULE_DPCC\t\t(1U << 0)\n /* Black Level Subtraction */\n@@ -1158,79 +1160,26 @@ enum rkisp1_ext_params_block_type {\n \tRKISP1_EXT_PARAMS_BLOCK_TYPE_WDR,\n };\n \n-#define RKISP1_EXT_PARAMS_FL_BLOCK_DISABLE\t(1U << 0)\n-#define RKISP1_EXT_PARAMS_FL_BLOCK_ENABLE\t(1U << 1)\n+/* For backward compatibility */\n+#define RKISP1_EXT_PARAMS_FL_BLOCK_DISABLE\tV4L2_ISP_PARAMS_FL_BLOCK_DISABLE\n+#define RKISP1_EXT_PARAMS_FL_BLOCK_ENABLE\tV4L2_ISP_PARAMS_FL_BLOCK_ENABLE\n \n /* A bitmask of parameters blocks supported on the current hardware. */\n #define RKISP1_CID_SUPPORTED_PARAMS_BLOCKS\t(V4L2_CID_USER_RKISP1_BASE + 0x01)\n \n /**\n- * struct rkisp1_ext_params_block_header - RkISP1 extensible parameters block\n- *\t\t\t\t\t header\n+ * rkisp1_ext_params_block_header - RkISP1 extensible parameters block header\n *\n * This structure represents the common part of all the ISP configuration\n- * blocks. Each parameters block shall embed an instance of this structure type\n- * as its first member, followed by the block-specific configuration data. The\n- * driver inspects this common header to discern the block type and its size and\n- * properly handle the block content by casting it to the correct block-specific\n- * type.\n+ * blocks and is identical to :c:type:`v4l2_isp_params_block_header`.\n *\n- * The @type field is one of the values enumerated by\n+ * The type field is one of the values enumerated by\n * :c:type:`rkisp1_ext_params_block_type` and specifies how the data should be\n- * interpreted by the driver. The @size field specifies the size of the\n- * parameters block and is used by the driver for validation purposes.\n+ * interpreted by the driver.\n *\n- * The @flags field is a bitmask of per-block flags RKISP1_EXT_PARAMS_FL_*.\n- *\n- * When userspace wants to configure and enable an ISP block it shall fully\n- * populate the block configuration and set the\n- * RKISP1_EXT_PARAMS_FL_BLOCK_ENABLE bit in the @flags field.\n- *\n- * When userspace simply wants to disable an ISP block the\n- * RKISP1_EXT_PARAMS_FL_BLOCK_DISABLE bit should be set in @flags field. The\n- * driver ignores the rest of the block configuration structure in this case.\n- *\n- * If a new configuration of an ISP block has to be applied userspace shall\n- * fully populate the ISP block configuration and omit setting the\n- * RKISP1_EXT_PARAMS_FL_BLOCK_ENABLE and RKISP1_EXT_PARAMS_FL_BLOCK_DISABLE bits\n- * in the @flags field.\n- *\n- * Setting both the RKISP1_EXT_PARAMS_FL_BLOCK_ENABLE and\n- * RKISP1_EXT_PARAMS_FL_BLOCK_DISABLE bits in the @flags field is not allowed\n- * and not accepted by the driver.\n- *\n- * Userspace is responsible for correctly populating the parameters block header\n- * fields (@type, @flags and @size) and the block-specific parameters.\n- *\n- * For example:\n- *\n- * .. code-block:: c\n- *\n- *\tvoid populate_bls(struct rkisp1_ext_params_block_header *block) {\n- *\t\tstruct rkisp1_ext_params_bls_config *bls =\n- *\t\t\t(struct rkisp1_ext_params_bls_config *)block;\n- *\n- *\t\tbls->header.type = RKISP1_EXT_PARAMS_BLOCK_ID_BLS;\n- *\t\tbls->header.flags = RKISP1_EXT_PARAMS_FL_BLOCK_ENABLE;\n- *\t\tbls->header.size = sizeof(*bls);\n- *\n- *\t\tbls->config.enable_auto = 0;\n- *\t\tbls->config.fixed_val.r = blackLevelRed_;\n- *\t\tbls->config.fixed_val.gr = blackLevelGreenR_;\n- *\t\tbls->config.fixed_val.gb = blackLevelGreenB_;\n- *\t\tbls->config.fixed_val.b = blackLevelBlue_;\n- *\t}\n- *\n- * @type: The parameters block type, see\n- *\t :c:type:`rkisp1_ext_params_block_type`\n- * @flags: A bitmask of block flags\n- * @size: Size (in bytes) of the parameters block, including this header\n+ * The flags field is a bitmask of per-block flags RKISP1_EXT_PARAMS_FL_*.\n */\n-struct rkisp1_ext_params_block_header {\n-\t__u16 type;\n-\t__u16 flags;\n-\t__u32 size;\n-};\n+#define rkisp1_ext_params_block_header v4l2_isp_params_block_header\n \n /**\n * struct rkisp1_ext_params_bls_config - RkISP1 extensible params BLS config\n@@ -1588,27 +1537,14 @@ struct rkisp1_ext_params_wdr_config {\n * @RKISP1_EXT_PARAM_BUFFER_V1: First version of RkISP1 extensible parameters\n */\n enum rksip1_ext_param_buffer_version {\n-\tRKISP1_EXT_PARAM_BUFFER_V1 = 1,\n+\tRKISP1_EXT_PARAM_BUFFER_V1 = V4L2_ISP_PARAMS_VERSION_V1,\n };\n \n /**\n * struct rkisp1_ext_params_cfg - RkISP1 extensible parameters configuration\n *\n- * This struct contains the configuration parameters of the RkISP1 ISP\n- * algorithms, serialized by userspace into a data buffer. Each configuration\n- * parameter block is represented by a block-specific structure which contains a\n- * :c:type:`rkisp1_ext_params_block_header` entry as first member. Userspace\n- * populates the @data buffer with configuration parameters for the blocks that\n- * it intends to configure. As a consequence, the data buffer effective size\n- * changes according to the number of ISP blocks that userspace intends to\n- * configure and is set by userspace in the @data_size field.\n- *\n- * The parameters buffer is versioned by the @version field to allow modifying\n- * and extending its definition. Userspace shall populate the @version field to\n- * inform the driver about the version it intends to use. The driver will parse\n- * and handle the @data buffer according to the data layout specific to the\n- * indicated version and return an error if the desired version is not\n- * supported.\n+ * This is the driver-specific implementation of\n+ * :c:type:`v4l2_isp_params_buffer`.\n *\n * Currently the single RKISP1_EXT_PARAM_BUFFER_V1 version is supported.\n * When a new format version will be added, a mechanism for userspace to query\n@@ -1624,11 +1560,6 @@ enum rksip1_ext_param_buffer_version {\n * the maximum value represents the blocks supported by the kernel driver,\n * independently of the device instance.\n *\n- * For each ISP block that userspace wants to configure, a block-specific\n- * structure is appended to the @data buffer, one after the other without gaps\n- * in between nor overlaps. Userspace shall populate the @data_size field with\n- * the effective size, in bytes, of the @data buffer.\n- *\n * The expected memory layout of the parameters buffer is::\n *\n *\t+-------------------- struct rkisp1_ext_params_cfg -------------------+\n@@ -1678,4 +1609,5 @@ struct rkisp1_ext_params_cfg {\n \t__u8 data[RKISP1_EXT_PARAMS_MAX_SIZE];\n };\n \n+\n #endif /* _RKISP1_CONFIG_H */\ndiff --git a/include/linux/stddef.h b/include/linux/stddef.h\nindex 48ee4438e0ef..457498259494 100644\n--- a/include/linux/stddef.h\n+++ b/include/linux/stddef.h\n@@ -69,6 +69,10 @@\n #define __counted_by_be(m)\n #endif\n \n+#ifndef __counted_by_ptr\n+#define __counted_by_ptr(m)\n+#endif\n+\n #define __kernel_nonstring\n \n #endif /* _LINUX_STDDEF_H */\ndiff --git a/include/linux/v4l2-controls.h b/include/linux/v4l2-controls.h\nindex 25914de2cd7a..c0d9cab3c71e 100644\n--- a/include/linux/v4l2-controls.h\n+++ b/include/linux/v4l2-controls.h\n@@ -230,6 +230,12 @@ enum v4l2_colorfx {\n */\n #define V4L2_CID_USER_RKISP1_BASE\t\t(V4L2_CID_USER_BASE + 0x1220)\n \n+/*\n+ * The base for the Arm Mali-C55 ISP driver controls.\n+ * We reserve 16 controls for this driver\n+ */\n+#define V4L2_CID_USER_MALI_C55_BASE\t\t(V4L2_CID_USER_BASE + 0x1230)\n+\n /* MPEG-class control IDs */\n /* The MPEG controls are applicable to all codec controls\n * and the 'MPEG' part of the define is historical */\n@@ -1186,6 +1192,8 @@ enum v4l2_flash_strobe_source {\n \n #define V4L2_CID_FLASH_CHARGE\t\t\t(V4L2_CID_FLASH_CLASS_BASE + 11)\n #define V4L2_CID_FLASH_READY\t\t\t(V4L2_CID_FLASH_CLASS_BASE + 12)\n+#define V4L2_CID_FLASH_DURATION\t\t\t(V4L2_CID_FLASH_CLASS_BASE + 13)\n+#define V4L2_CID_FLASH_STROBE_OE\t\t(V4L2_CID_FLASH_CLASS_BASE + 14)\n \n \n /* JPEG-class control IDs */\n@@ -2093,6 +2101,8 @@ struct v4l2_ctrl_mpeg2_quantisation {\n #define V4L2_CID_STATELESS_HEVC_DECODE_MODE\t(V4L2_CID_CODEC_STATELESS_BASE + 405)\n #define V4L2_CID_STATELESS_HEVC_START_CODE\t(V4L2_CID_CODEC_STATELESS_BASE + 406)\n #define V4L2_CID_STATELESS_HEVC_ENTRY_POINT_OFFSETS (V4L2_CID_CODEC_STATELESS_BASE + 407)\n+#define V4L2_CID_STATELESS_HEVC_EXT_SPS_ST_RPS (V4L2_CID_CODEC_STATELESS_BASE + 408)\n+#define V4L2_CID_STATELESS_HEVC_EXT_SPS_LT_RPS (V4L2_CID_CODEC_STATELESS_BASE + 409)\n \n enum v4l2_stateless_hevc_decode_mode {\n \tV4L2_STATELESS_HEVC_DECODE_MODE_SLICE_BASED,\n@@ -2548,6 +2558,65 @@ struct v4l2_ctrl_hevc_scaling_matrix {\n \t__u8\tscaling_list_dc_coef_32x32[2];\n };\n \n+#define V4L2_HEVC_EXT_SPS_ST_RPS_FLAG_INTER_REF_PIC_SET_PRED\t0x1\n+\n+/*\n+ * struct v4l2_ctrl_hevc_ext_sps_st_rps - HEVC short term RPS parameters\n+ *\n+ * Dynamic size 1-dimension array for short term RPS. The number of elements\n+ * is v4l2_ctrl_hevc_sps::num_short_term_ref_pic_sets. It can contain up to 65 elements.\n+ *\n+ * @delta_idx_minus1: Specifies the delta compare to the index. See details in section 7.4.8\n+ * \"Short-term reference picture set semantics\" of the specification.\n+ * @delta_rps_sign: Sign of the delta as specified in section 7.4.8 \"Short-term reference picture\n+ * set semantics\" of the specification.\n+ * @abs_delta_rps_minus1: Absolute delta RPS as specified in section 7.4.8 \"Short-term reference\n+ * picture set semantics\" of the specification.\n+ * @num_negative_pics: Number of short-term RPS entries that have picture order count values less\n+ * than the picture order count value of the current picture.\n+ * @num_positive_pics: Number of short-term RPS entries that have picture order count values\n+ * greater than the picture order count value of the current picture.\n+ * @used_by_curr_pic: Bit j specifies if short-term RPS j is used by the current picture.\n+ * @use_delta_flag: Bit j equals to 1 specifies that the j-th entry in the source candidate\n+ * short-term RPS is included in this candidate short-term RPS.\n+ * @delta_poc_s0_minus1: Specifies the negative picture order count delta for the i-th entry in\n+ * the short-term RPS. See details in section 7.4.8 \"Short-term reference\n+ * picture set semantics\" of the specification.\n+ * @delta_poc_s1_minus1: Specifies the positive picture order count delta for the i-th entry in\n+ * the short-term RPS. See details in section 7.4.8 \"Short-term reference\n+ * picture set semantics\" of the specification.\n+ * @flags: See V4L2_HEVC_EXT_SPS_ST_RPS_FLAG_{}\n+ */\n+struct v4l2_ctrl_hevc_ext_sps_st_rps {\n+\t__u8\tdelta_idx_minus1;\n+\t__u8\tdelta_rps_sign;\n+\t__u8\tnum_negative_pics;\n+\t__u8\tnum_positive_pics;\n+\t__u32\tused_by_curr_pic;\n+\t__u32\tuse_delta_flag;\n+\t__u16\tabs_delta_rps_minus1;\n+\t__u16\tdelta_poc_s0_minus1[16];\n+\t__u16\tdelta_poc_s1_minus1[16];\n+\t__u16\tflags;\n+};\n+\n+#define V4L2_HEVC_EXT_SPS_LT_RPS_FLAG_USED_LT\t\t0x1\n+\n+/*\n+ * struct v4l2_ctrl_hevc_ext_sps_lt_rps - HEVC long term RPS parameters\n+ *\n+ * Dynamic size 1-dimension array for long term RPS. The number of elements\n+ * is v4l2_ctrl_hevc_sps::num_long_term_ref_pics_sps. It can contain up to 65 elements.\n+ *\n+ * @lt_ref_pic_poc_lsb_sps: picture order count modulo MaxPicOrderCntLsb of the i-th candidate\n+ * long-term reference picture.\n+ * @flags: See V4L2_HEVC_EXT_SPS_LT_RPS_FLAG_{}\n+ */\n+struct v4l2_ctrl_hevc_ext_sps_lt_rps {\n+\t__u16\tlt_ref_pic_poc_lsb_sps;\n+\t__u16\tflags;\n+};\n+\n /* Stateless VP9 controls */\n \n #define V4L2_VP9_LOOP_FILTER_FLAG_DELTA_ENABLED\t0x1\ndiff --git a/include/linux/videodev2.h b/include/linux/videodev2.h\nindex b40b43d72196..8bccad84ff83 100644\n--- a/include/linux/videodev2.h\n+++ b/include/linux/videodev2.h\n@@ -748,6 +748,7 @@ struct v4l2_pix_format {\n #define V4L2_PIX_FMT_H264_SLICE v4l2_fourcc('S', '2', '6', '4') /* H264 parsed slices */\n #define V4L2_PIX_FMT_HEVC_SLICE v4l2_fourcc('S', '2', '6', '5') /* HEVC parsed slices */\n #define V4L2_PIX_FMT_AV1_FRAME v4l2_fourcc('A', 'V', '1', 'F') /* AV1 parsed frame */\n+#define V4L2_PIX_FMT_AV1 v4l2_fourcc('A', 'V', '0', '1') /* AV1 */\n #define V4L2_PIX_FMT_SPK v4l2_fourcc('S', 'P', 'K', '0') /* Sorenson Spark */\n #define V4L2_PIX_FMT_RV30 v4l2_fourcc('R', 'V', '3', '0') /* RealVideo 8 */\n #define V4L2_PIX_FMT_RV40 v4l2_fourcc('R', 'V', '4', '0') /* RealVideo 9 & 10 */\n@@ -859,9 +860,9 @@ struct v4l2_pix_format {\n #define V4L2_META_FMT_RPI_FE_CFG\tv4l2_fourcc('R', 'P', 'F', 'C') /* PiSP FE configuration */\n #define V4L2_META_FMT_RPI_FE_STATS\tv4l2_fourcc('R', 'P', 'F', 'S') /* PiSP FE stats */\n \n-\n+/* Vendor specific - used for Arm Mali-C55 ISP */\n #define V4L2_META_FMT_MALI_C55_PARAMS\tv4l2_fourcc('C', '5', '5', 'P') /* ARM Mali-C55 Parameters */\n-#define V4L2_META_FMT_MALI_C55_3A_STATS v4l2_fourcc('C', '5', '5', 'S') /* ARM Mali-C55 3A Statistics */\n+#define V4L2_META_FMT_MALI_C55_STATS\tv4l2_fourcc('C', '5', '5', 'S') /* ARM Mali-C55 3A Statistics */\n \n /*\n * Line-based metadata formats. Remember to update v4l_fill_fmtdesc() when\n@@ -1929,6 +1930,8 @@ enum v4l2_ctrl_type {\n \tV4L2_CTRL_TYPE_HEVC_SLICE_PARAMS\t= 0x0272,\n \tV4L2_CTRL_TYPE_HEVC_SCALING_MATRIX\t= 0x0273,\n \tV4L2_CTRL_TYPE_HEVC_DECODE_PARAMS\t= 0x0274,\n+\tV4L2_CTRL_TYPE_HEVC_EXT_SPS_ST_RPS\t= 0x0275,\n+\tV4L2_CTRL_TYPE_HEVC_EXT_SPS_LT_RPS\t= 0x0276,\n \n \tV4L2_CTRL_TYPE_AV1_SEQUENCE\t = 0x280,\n \tV4L2_CTRL_TYPE_AV1_TILE_GROUP_ENTRY = 0x281,\n","prefixes":["5/6"]}