[{"id":37272,"web_url":"https://patchwork.libcamera.org/comment/37272/","msgid":"<20251211012023.GG28860@pendragon.ideasonboard.com>","date":"2025-12-11T01:20:23","subject":"Re: [PATCH v2 1/6] include: linux: drm_fourcc.h: Update to v6.18","submitter":{"id":2,"url":"https://patchwork.libcamera.org/api/people/2/","name":"Laurent Pinchart","email":"laurent.pinchart@ideasonboard.com"},"content":"On Wed, Dec 10, 2025 at 09:19:12AM +0100, Jacopo Mondi wrote:\n> Update drm_fourcc.h to Linux kernel version v6.18.\n> \n> As the upstream drm_fourcc.h version doesn't include definitions\n> for RAW Bayer formats, some of the symbols we defined\n> downstream now conflict with new symbols defined in mainline.\n> \n> In particular:\n> \n> and\n> \n\nSomething seem to be missing here :-)\n\n> In order not to break the library ABI, maintain the downstream symbols\n> definitions as they are even if they conflict.\n> \n> Signed-off-by: Jacopo Mondi \n> Acked-by: Barnabás Pőcze \n> ---\n> include/linux/drm_fourcc.h | 191 ++++++++++++++++++++++++++++++++++++++++++---\n> 1 file changed, 180 insertions(+), 11 deletions(-)\n> \n> diff --git a/include/linux/drm_fourcc.h b/include/linux/drm_fourcc.h\n> index db6798776663086c12d321d2ed708edc7ec77f71..e428c33346bae8a8747f6834c434dc0a03eef867 100644\n> --- a/include/linux/drm_fourcc.h\n> +++ b/include/linux/drm_fourcc.h\n> @@ -222,7 +222,7 @@ extern \"C\" {\n> #define DRM_FORMAT_ABGR16161616\tfourcc_code('A', 'B', '4', '8') /* [63:0] A:B:G:R 16:16:16:16 little endian */\n> \n> /*\n> - * Floating point 64bpp RGB\n> + * Half-Floating point - 16b/component\n> * IEEE 754-2008 binary16 half-precision float\n> * [15:0] sign:exponent:mantissa 1:5:10\n> */\n> @@ -232,6 +232,20 @@ extern \"C\" {\n> #define DRM_FORMAT_ARGB16161616F fourcc_code('A', 'R', '4', 'H') /* [63:0] A:R:G:B 16:16:16:16 little endian */\n> #define DRM_FORMAT_ABGR16161616F fourcc_code('A', 'B', '4', 'H') /* [63:0] A:B:G:R 16:16:16:16 little endian */\n> \n> +#define DRM_FORMAT_R16F fourcc_code('R', ' ', ' ', 'H') /* [15:0] R 16 little endian */\n> +#define DRM_FORMAT_GR1616F fourcc_code('G', 'R', ' ', 'H') /* [31:0] G:R 16:16 little endian */\n> +#define DRM_FORMAT_BGR161616F fourcc_code('B', 'G', 'R', 'H') /* [47:0] B:G:R 16:16:16 little endian */\n> +\n> +/*\n> + * Floating point - 32b/component\n> + * IEEE 754-2008 binary32 float\n> + * [31:0] sign:exponent:mantissa 1:8:23\n> + */\n> +#define DRM_FORMAT_R32F fourcc_code('R', ' ', ' ', 'F') /* [31:0] R 32 little endian */\n> +#define DRM_FORMAT_GR3232F fourcc_code('G', 'R', ' ', 'F') /* [63:0] R:G 32:32 little endian */\n> +#define DRM_FORMAT_BGR323232F fourcc_code('B', 'G', 'R', 'F') /* [95:0] R:G:B 32:32:32 little endian */\n> +#define DRM_FORMAT_ABGR32323232F fourcc_code('A', 'B', '8', 'F') /* [127:0] R:G:B:A 32:32:32:32 little endian */\n> +\n> /*\n> * RGBA format with 10-bit components packed in 64-bit per pixel, with 6 bits\n> * of unused padding per component:\n> @@ -381,6 +395,42 @@ extern \"C\" {\n> */\n> #define DRM_FORMAT_Q401\t\tfourcc_code('Q', '4', '0', '1')\n> \n> +/*\n> + * 3 plane YCbCr LSB aligned\n> + * In order to use these formats in a similar fashion to MSB aligned ones\n> + * implementation can multiply the values by 2^6=64. For that reason the padding\n> + * must only contain zeros.\n> + * index 0 = Y plane, [15:0] z:Y [6:10] little endian\n> + * index 1 = Cr plane, [15:0] z:Cr [6:10] little endian\n> + * index 2 = Cb plane, [15:0] z:Cb [6:10] little endian\n> + */\n> +#define DRM_FORMAT_S010\tfourcc_code('S', '0', '1', '0') /* 2x2 subsampled Cb (1) and Cr (2) planes 10 bits per channel */\n> +#define DRM_FORMAT_S210\tfourcc_code('S', '2', '1', '0') /* 2x1 subsampled Cb (1) and Cr (2) planes 10 bits per channel */\n> +#define DRM_FORMAT_S410\tfourcc_code('S', '4', '1', '0') /* non-subsampled Cb (1) and Cr (2) planes 10 bits per channel */\n> +\n> +/*\n> + * 3 plane YCbCr LSB aligned\n> + * In order to use these formats in a similar fashion to MSB aligned ones\n> + * implementation can multiply the values by 2^4=16. For that reason the padding\n> + * must only contain zeros.\n> + * index 0 = Y plane, [15:0] z:Y [4:12] little endian\n> + * index 1 = Cr plane, [15:0] z:Cr [4:12] little endian\n> + * index 2 = Cb plane, [15:0] z:Cb [4:12] little endian\n> + */\n> +#define DRM_FORMAT_S012\tfourcc_code('S', '0', '1', '2') /* 2x2 subsampled Cb (1) and Cr (2) planes 12 bits per channel */\n> +#define DRM_FORMAT_S212\tfourcc_code('S', '2', '1', '2') /* 2x1 subsampled Cb (1) and Cr (2) planes 12 bits per channel */\n> +#define DRM_FORMAT_S412\tfourcc_code('S', '4', '1', '2') /* non-subsampled Cb (1) and Cr (2) planes 12 bits per channel */\n> +\n> +/*\n> + * 3 plane YCbCr\n> + * index 0 = Y plane, [15:0] Y little endian\n> + * index 1 = Cr plane, [15:0] Cr little endian\n> + * index 2 = Cb plane, [15:0] Cb little endian\n> + */\n> +#define DRM_FORMAT_S016\tfourcc_code('S', '0', '1', '6') /* 2x2 subsampled Cb (1) and Cr (2) planes 16 bits per channel */\n> +#define DRM_FORMAT_S216\tfourcc_code('S', '2', '1', '6') /* 2x1 subsampled Cb (1) and Cr (2) planes 16 bits per channel */\n> +#define DRM_FORMAT_S416\tfourcc_code('S', '4', '1', '6') /* non-subsampled Cb (1) and Cr (2) planes 16 bits per channel */\n> +\n> /*\n> * 3 plane YCbCr\n> * index 0: Y plane, [7:0] Y\n> @@ -489,6 +539,8 @@ extern \"C\" {\n> #define DRM_FORMAT_MOD_VENDOR_ARM 0x08\n> #define DRM_FORMAT_MOD_VENDOR_ALLWINNER 0x09\n> #define DRM_FORMAT_MOD_VENDOR_AMLOGIC 0x0a\n> +#define DRM_FORMAT_MOD_VENDOR_MTK 0x0b\n> +#define DRM_FORMAT_MOD_VENDOR_APPLE 0x0c\n> #define DRM_FORMAT_MOD_VENDOR_MIPI 0x0b\n> #define DRM_FORMAT_MOD_VENDOR_RPI 0x0c\n> \n> @@ -772,6 +824,31 @@ extern \"C\" {\n> */\n> #define I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC fourcc_mod_code(INTEL, 15)\n> \n> +/*\n> + * Intel Color Control Surfaces (CCS) for graphics ver. 20 unified compression\n> + * on integrated graphics\n> + *\n> + * The main surface is Tile 4 and at plane index 0. For semi-planar formats\n> + * like NV12, the Y and UV planes are Tile 4 and are located at plane indices\n> + * 0 and 1, respectively. The CCS for all planes are stored outside of the\n> + * GEM object in a reserved memory area dedicated for the storage of the\n> + * CCS data for all compressible GEM objects.\n> + */\n> +#define I915_FORMAT_MOD_4_TILED_LNL_CCS fourcc_mod_code(INTEL, 16)\n> +\n> +/*\n> + * Intel Color Control Surfaces (CCS) for graphics ver. 20 unified compression\n> + * on discrete graphics\n> + *\n> + * The main surface is Tile 4 and at plane index 0. For semi-planar formats\n> + * like NV12, the Y and UV planes are Tile 4 and are located at plane indices\n> + * 0 and 1, respectively. The CCS for all planes are stored outside of the\n> + * GEM object in a reserved memory area dedicated for the storage of the\n> + * CCS data for all compressible GEM objects. The GEM object must be stored in\n> + * contiguous memory with a size aligned to 64KB\n> + */\n> +#define I915_FORMAT_MOD_4_TILED_BMG_CCS fourcc_mod_code(INTEL, 17)\n> +\n> /*\n> * IPU3 Bayer packing layout\n> *\n> @@ -780,7 +857,7 @@ extern \"C\" {\n> * the 6 most significant bits in the last byte unused. The format is little\n> * endian.\n> */\n> -#define IPU3_FORMAT_MOD_PACKED fourcc_mod_code(INTEL, 13)\n> +#define IPU3_FORMAT_MOD_PACKED fourcc_mod_code(INTEL, 18)\n> \n> /*\n> * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks\n> @@ -978,14 +1055,20 @@ extern \"C\" {\n> * 2 = Gob Height 8, Turing+ Page Kind mapping\n> * 3 = Reserved for future use.\n> *\n> - * 22:22 s Sector layout. On Tegra GPUs prior to Xavier, there is a further\n> - * bit remapping step that occurs at an even lower level than the\n> - * page kind and block linear swizzles. This causes the layout of\n> - * surfaces mapped in those SOC's GPUs to be incompatible with the\n> - * equivalent mapping on other GPUs in the same system.\n> - *\n> - * 0 = Tegra K1 - Tegra Parker/TX2 Layout.\n> - * 1 = Desktop GPU and Tegra Xavier+ Layout\n> + * 22:22 s Sector layout. There is a further bit remapping step that occurs\n> + * 26:27 at an even lower level than the page kind and block linear\n> + * swizzles. This causes the bit arrangement of surfaces in memory\n> + * to differ subtly, and prevents direct sharing of surfaces between\n> + * GPUs with different layouts.\n> + *\n> + * 0 = Tegra K1 - Tegra Parker/TX2 Layout\n> + * 1 = Pre-GB20x, GB20x 32+ bpp, GB10, Tegra Xavier-Orin Layout\n> + * 2 = GB20x(Blackwell 2)+ 8 bpp surface layout\n> + * 3 = GB20x(Blackwell 2)+ 16 bpp surface layout\n> + * 4 = Reserved for future use.\n> + * 5 = Reserved for future use.\n> + * 6 = Reserved for future use.\n> + * 7 = Reserved for future use.\n> *\n> * 25:23 c Lossless Framebuffer Compression type.\n> *\n> @@ -1000,7 +1083,7 @@ extern \"C\" {\n> * 6 = Reserved for future use\n> * 7 = Reserved for future use\n> *\n> - * 55:25 - Reserved for future use. Must be zero.\n> + * 55:28 - Reserved for future use. Must be zero.\n> */\n> #define DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(c, s, g, k, h) \\\n> \tfourcc_mod_code(NVIDIA, (0x10 | \\\n> @@ -1008,6 +1091,7 @@ extern \"C\" {\n> \t\t\t\t (((k) & 0xff) << 12) | \\\n> \t\t\t\t (((g) & 0x3) << 20) | \\\n> \t\t\t\t (((s) & 0x1) << 22) | \\\n> +\t\t\t\t (((s) & 0x6) << 25) | \\\n> \t\t\t\t (((c) & 0x7) << 23)))\n> \n> /* To grandfather in prior block linear format modifiers to the above layout,\n> @@ -1508,6 +1592,90 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier)\n> */\n> #define AMLOGIC_FBC_OPTION_MEM_SAVING\t\t(1ULL << 0)\n> \n> +/* MediaTek modifiers\n> + * Bits Parameter Notes\n> + * ----- ------------------------ ---------------------------------------------\n> + * 7: 0 TILE LAYOUT Values are MTK_FMT_MOD_TILE_*\n> + * 15: 8 COMPRESSION Values are MTK_FMT_MOD_COMPRESS_*\n> + * 23:16 10 BIT LAYOUT Values are MTK_FMT_MOD_10BIT_LAYOUT_*\n> + *\n> + */\n> +\n> +#define DRM_FORMAT_MOD_MTK(__flags)\t\tfourcc_mod_code(MTK, __flags)\n> +\n> +/*\n> + * MediaTek Tiled Modifier\n> + * The lowest 8 bits of the modifier is used to specify the tiling\n> + * layout. Only the 16L_32S tiling is used for now, but we define an\n> + * \"untiled\" version and leave room for future expansion.\n> + */\n> +#define MTK_FMT_MOD_TILE_MASK 0xf\n> +#define MTK_FMT_MOD_TILE_NONE 0x0\n> +#define MTK_FMT_MOD_TILE_16L32S 0x1\n> +\n> +/*\n> + * Bits 8-15 specify compression options\n> + */\n> +#define MTK_FMT_MOD_COMPRESS_MASK (0xf << 8)\n> +#define MTK_FMT_MOD_COMPRESS_NONE (0x0 << 8)\n> +#define MTK_FMT_MOD_COMPRESS_V1 (0x1 << 8)\n> +\n> +/*\n> + * Bits 16-23 specify how the bits of 10 bit formats are\n> + * stored out in memory\n> + */\n> +#define MTK_FMT_MOD_10BIT_LAYOUT_MASK (0xf << 16)\n> +#define MTK_FMT_MOD_10BIT_LAYOUT_PACKED (0x0 << 16)\n> +#define MTK_FMT_MOD_10BIT_LAYOUT_LSBTILED (0x1 << 16)\n> +#define MTK_FMT_MOD_10BIT_LAYOUT_LSBRASTER (0x2 << 16)\n> +\n> +/* alias for the most common tiling format */\n> +#define DRM_FORMAT_MOD_MTK_16L_32S_TILE DRM_FORMAT_MOD_MTK(MTK_FMT_MOD_TILE_16L32S)\n> +\n> +/*\n> + * Apple GPU-tiled layouts.\n> + *\n> + * Apple GPUs support nonlinear tilings with optional lossless compression.\n> + *\n> + * GPU-tiled images are divided into 16KiB tiles:\n> + *\n> + * Bytes per pixel Tile size\n> + * --------------- ---------\n> + * 1 128x128\n> + * 2 128x64\n> + * 4 64x64\n> + * 8 64x32\n> + * 16 32x32\n> + *\n> + * Tiles are raster-order. Pixels within a tile are interleaved (Morton order).\n> + *\n> + * Compressed images pad the body to 128-bytes and are immediately followed by a\n> + * metadata section. The metadata section rounds the image dimensions to\n> + * powers-of-two and contains 8 bytes for each 16x16 compression subtile.\n> + * Subtiles are interleaved (Morton order).\n> + *\n> + * All images are 128-byte aligned.\n> + *\n> + * These layouts fundamentally do not have meaningful strides. No matter how we\n> + * specify strides for these layouts, userspace unaware of Apple image layouts\n> + * will be unable to use correctly the specified stride for any purpose.\n> + * Userspace aware of the image layouts do not use strides. The most \"correct\"\n> + * convention would be setting the image stride to 0. Unfortunately, some\n> + * software assumes the stride is at least (width * bytes per pixel). We\n> + * therefore require that stride equals (width * bytes per pixel). Since the\n> + * stride is arbitrary here, we pick the simplest convention.\n> + *\n> + * Although containing two sections, compressed image layouts are treated in\n> + * software as a single plane. This is modelled after AFBC, a similar\n> + * scheme. Attempting to separate the sections to be \"explicit\" in DRM would\n> + * only generate more confusion, as software does not treat the image this way.\n> + *\n> + * For detailed information on the hardware image layouts, see\n> + * https://docs.mesa3d.org/drivers/asahi.html#image-layouts\n> + */\n> +#define DRM_FORMAT_MOD_APPLE_GPU_TILED fourcc_mod_code(APPLE, 1)\n> +#define DRM_FORMAT_MOD_APPLE_GPU_TILED_COMPRESSED fourcc_mod_code(APPLE, 2)\n> +\n> /*\n> * AMD modifiers\n> *\n> @@ -1571,6 +1739,7 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier)\n> * 64K_D_2D on GFX12 is identical to 64K_D on GFX11.\n> */\n> #define AMD_FMT_MOD_TILE_GFX9_64K_D 10\n> +#define AMD_FMT_MOD_TILE_GFX9_4K_D_X 22\n> #define AMD_FMT_MOD_TILE_GFX9_64K_S_X 25\n> #define AMD_FMT_MOD_TILE_GFX9_64K_D_X 26\n> #define AMD_FMT_MOD_TILE_GFX9_64K_R_X 27","headers":{"Return-Path":"","X-Original-To":"parsemail@patchwork.libcamera.org","Delivered-To":"parsemail@patchwork.libcamera.org","Received":["from lancelot.ideasonboard.com (lancelot.ideasonboard.com\n\t[92.243.16.209])\n\tby patchwork.libcamera.org (Postfix) with ESMTPS id EBF2EBD1F1\n\tfor ;\n\tThu, 11 Dec 2025 01:20:46 +0000 (UTC)","from lancelot.ideasonboard.com (localhost [IPv6:::1])\n\tby lancelot.ideasonboard.com (Postfix) with ESMTP id 13CB3614BD;\n\tThu, 11 Dec 2025 02:20:46 +0100 (CET)","from perceval.ideasonboard.com (perceval.ideasonboard.com\n\t[IPv6:2001:4b98:dc2:55:216:3eff:fef7:d647])\n\tby lancelot.ideasonboard.com (Postfix) with ESMTPS id E3D16606D5\n\tfor ;\n\tThu, 11 Dec 2025 02:20:43 +0100 (CET)","from pendragon.ideasonboard.com (fs96f9c361.tkyc007.ap.nuro.jp\n\t[150.249.195.97])\n\tby perceval.ideasonboard.com (Postfix) with UTF8SMTPSA id BA4C51352; \n\tThu, 11 Dec 2025 02:20:40 +0100 (CET)"],"Authentication-Results":"lancelot.ideasonboard.com; dkim=pass (1024-bit key;\n\tunprotected) header.d=ideasonboard.com header.i=@ideasonboard.com\n\theader.b=\"EdL6L/hv\"; dkim-atps=neutral","DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com;\n\ts=mail; t=1765416041;\n\tbh=CrTL2oXlrCP3P+ybpIHH/L2JWcCQtukED8eLPfOqjiU=;\n\th=Date:From:To:Cc:Subject:References:In-Reply-To:From;\n\tb=EdL6L/hvtl8PZycqjr5geo10jAsp1GvEoCJvuYEnSwcr6k8plZzY8QHZyWGhhyxTB\n\tFEZ0kl1TwGYJijucD0JorgnKGihowLlt7qbbz0TQPDxjJYPZ6CtKJYhPk2QSf1Mu+p\n\t2kF0anLsD1HA3OO9/j+eMu2+QB/a1TZCuq6evqC8=","Date":"Thu, 11 Dec 2025 10:20:23 +0900","From":"Laurent Pinchart ","To":"Jacopo Mondi ","Cc":"libcamera-devel@lists.libcamera.org, =?utf-8?b?QmFybmFiw6FzIFDFkWN6?=\n\t=?utf-8?q?e?= ","Subject":"Re: [PATCH v2 1/6] include: linux: drm_fourcc.h: Update to v6.18","Message-ID":"<20251211012023.GG28860@pendragon.ideasonboard.com>","References":"<20251210-headers-update-v6-18-v2-0-3f726742a4c8@ideasonboard.com>\n\t<20251210-headers-update-v6-18-v2-1-3f726742a4c8@ideasonboard.com>","MIME-Version":"1.0","Content-Type":"text/plain; charset=utf-8","Content-Disposition":"inline","Content-Transfer-Encoding":"8bit","In-Reply-To":"<20251210-headers-update-v6-18-v2-1-3f726742a4c8@ideasonboard.com>","X-BeenThere":"libcamera-devel@lists.libcamera.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Errors-To":"libcamera-devel-bounces@lists.libcamera.org","Sender":"\"libcamera-devel\" "}},{"id":37288,"web_url":"https://patchwork.libcamera.org/comment/37288/","msgid":"","date":"2025-12-11T08:43:31","subject":"Re: [PATCH v2 1/6] include: linux: drm_fourcc.h: Update to v6.18","submitter":{"id":143,"url":"https://patchwork.libcamera.org/api/people/143/","name":"Jacopo Mondi","email":"jacopo.mondi@ideasonboard.com"},"content":"On Thu, Dec 11, 2025 at 10:20:23AM +0900, Laurent Pinchart wrote:\n> On Wed, Dec 10, 2025 at 09:19:12AM +0100, Jacopo Mondi wrote:\n> > Update drm_fourcc.h to Linux kernel version v6.18.\n> >\n> > As the upstream drm_fourcc.h version doesn't include definitions\n> > for RAW Bayer formats, some of the symbols we defined\n> > downstream now conflict with new symbols defined in mainline.\n> >\n> > In particular:\n> >\n> > and\n> >\n>\n> Something seem to be missing here :-)\n>\n\nUps, dunno what happened. I'll resend\n\n> > In order not to break the library ABI, maintain the downstream symbols\n> > definitions as they are even if they conflict.\n> >\n> > Signed-off-by: Jacopo Mondi \n> > Acked-by: Barnabás Pőcze \n> > ---\n> > include/linux/drm_fourcc.h | 191 ++++++++++++++++++++++++++++++++++++++++++---\n> > 1 file changed, 180 insertions(+), 11 deletions(-)\n> >\n> > diff --git a/include/linux/drm_fourcc.h b/include/linux/drm_fourcc.h\n> > index db6798776663086c12d321d2ed708edc7ec77f71..e428c33346bae8a8747f6834c434dc0a03eef867 100644\n> > --- a/include/linux/drm_fourcc.h\n> > +++ b/include/linux/drm_fourcc.h\n> > @@ -222,7 +222,7 @@ extern \"C\" {\n> > #define DRM_FORMAT_ABGR16161616\tfourcc_code('A', 'B', '4', '8') /* [63:0] A:B:G:R 16:16:16:16 little endian */\n> >\n> > /*\n> > - * Floating point 64bpp RGB\n> > + * Half-Floating point - 16b/component\n> > * IEEE 754-2008 binary16 half-precision float\n> > * [15:0] sign:exponent:mantissa 1:5:10\n> > */\n> > @@ -232,6 +232,20 @@ extern \"C\" {\n> > #define DRM_FORMAT_ARGB16161616F fourcc_code('A', 'R', '4', 'H') /* [63:0] A:R:G:B 16:16:16:16 little endian */\n> > #define DRM_FORMAT_ABGR16161616F fourcc_code('A', 'B', '4', 'H') /* [63:0] A:B:G:R 16:16:16:16 little endian */\n> >\n> > +#define DRM_FORMAT_R16F fourcc_code('R', ' ', ' ', 'H') /* [15:0] R 16 little endian */\n> > +#define DRM_FORMAT_GR1616F fourcc_code('G', 'R', ' ', 'H') /* [31:0] G:R 16:16 little endian */\n> > +#define DRM_FORMAT_BGR161616F fourcc_code('B', 'G', 'R', 'H') /* [47:0] B:G:R 16:16:16 little endian */\n> > +\n> > +/*\n> > + * Floating point - 32b/component\n> > + * IEEE 754-2008 binary32 float\n> > + * [31:0] sign:exponent:mantissa 1:8:23\n> > + */\n> > +#define DRM_FORMAT_R32F fourcc_code('R', ' ', ' ', 'F') /* [31:0] R 32 little endian */\n> > +#define DRM_FORMAT_GR3232F fourcc_code('G', 'R', ' ', 'F') /* [63:0] R:G 32:32 little endian */\n> > +#define DRM_FORMAT_BGR323232F fourcc_code('B', 'G', 'R', 'F') /* [95:0] R:G:B 32:32:32 little endian */\n> > +#define DRM_FORMAT_ABGR32323232F fourcc_code('A', 'B', '8', 'F') /* [127:0] R:G:B:A 32:32:32:32 little endian */\n> > +\n> > /*\n> > * RGBA format with 10-bit components packed in 64-bit per pixel, with 6 bits\n> > * of unused padding per component:\n> > @@ -381,6 +395,42 @@ extern \"C\" {\n> > */\n> > #define DRM_FORMAT_Q401\t\tfourcc_code('Q', '4', '0', '1')\n> >\n> > +/*\n> > + * 3 plane YCbCr LSB aligned\n> > + * In order to use these formats in a similar fashion to MSB aligned ones\n> > + * implementation can multiply the values by 2^6=64. For that reason the padding\n> > + * must only contain zeros.\n> > + * index 0 = Y plane, [15:0] z:Y [6:10] little endian\n> > + * index 1 = Cr plane, [15:0] z:Cr [6:10] little endian\n> > + * index 2 = Cb plane, [15:0] z:Cb [6:10] little endian\n> > + */\n> > +#define DRM_FORMAT_S010\tfourcc_code('S', '0', '1', '0') /* 2x2 subsampled Cb (1) and Cr (2) planes 10 bits per channel */\n> > +#define DRM_FORMAT_S210\tfourcc_code('S', '2', '1', '0') /* 2x1 subsampled Cb (1) and Cr (2) planes 10 bits per channel */\n> > +#define DRM_FORMAT_S410\tfourcc_code('S', '4', '1', '0') /* non-subsampled Cb (1) and Cr (2) planes 10 bits per channel */\n> > +\n> > +/*\n> > + * 3 plane YCbCr LSB aligned\n> > + * In order to use these formats in a similar fashion to MSB aligned ones\n> > + * implementation can multiply the values by 2^4=16. For that reason the padding\n> > + * must only contain zeros.\n> > + * index 0 = Y plane, [15:0] z:Y [4:12] little endian\n> > + * index 1 = Cr plane, [15:0] z:Cr [4:12] little endian\n> > + * index 2 = Cb plane, [15:0] z:Cb [4:12] little endian\n> > + */\n> > +#define DRM_FORMAT_S012\tfourcc_code('S', '0', '1', '2') /* 2x2 subsampled Cb (1) and Cr (2) planes 12 bits per channel */\n> > +#define DRM_FORMAT_S212\tfourcc_code('S', '2', '1', '2') /* 2x1 subsampled Cb (1) and Cr (2) planes 12 bits per channel */\n> > +#define DRM_FORMAT_S412\tfourcc_code('S', '4', '1', '2') /* non-subsampled Cb (1) and Cr (2) planes 12 bits per channel */\n> > +\n> > +/*\n> > + * 3 plane YCbCr\n> > + * index 0 = Y plane, [15:0] Y little endian\n> > + * index 1 = Cr plane, [15:0] Cr little endian\n> > + * index 2 = Cb plane, [15:0] Cb little endian\n> > + */\n> > +#define DRM_FORMAT_S016\tfourcc_code('S', '0', '1', '6') /* 2x2 subsampled Cb (1) and Cr (2) planes 16 bits per channel */\n> > +#define DRM_FORMAT_S216\tfourcc_code('S', '2', '1', '6') /* 2x1 subsampled Cb (1) and Cr (2) planes 16 bits per channel */\n> > +#define DRM_FORMAT_S416\tfourcc_code('S', '4', '1', '6') /* non-subsampled Cb (1) and Cr (2) planes 16 bits per channel */\n> > +\n> > /*\n> > * 3 plane YCbCr\n> > * index 0: Y plane, [7:0] Y\n> > @@ -489,6 +539,8 @@ extern \"C\" {\n> > #define DRM_FORMAT_MOD_VENDOR_ARM 0x08\n> > #define DRM_FORMAT_MOD_VENDOR_ALLWINNER 0x09\n> > #define DRM_FORMAT_MOD_VENDOR_AMLOGIC 0x0a\n> > +#define DRM_FORMAT_MOD_VENDOR_MTK 0x0b\n> > +#define DRM_FORMAT_MOD_VENDOR_APPLE 0x0c\n> > #define DRM_FORMAT_MOD_VENDOR_MIPI 0x0b\n> > #define DRM_FORMAT_MOD_VENDOR_RPI 0x0c\n> >\n> > @@ -772,6 +824,31 @@ extern \"C\" {\n> > */\n> > #define I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC fourcc_mod_code(INTEL, 15)\n> >\n> > +/*\n> > + * Intel Color Control Surfaces (CCS) for graphics ver. 20 unified compression\n> > + * on integrated graphics\n> > + *\n> > + * The main surface is Tile 4 and at plane index 0. For semi-planar formats\n> > + * like NV12, the Y and UV planes are Tile 4 and are located at plane indices\n> > + * 0 and 1, respectively. The CCS for all planes are stored outside of the\n> > + * GEM object in a reserved memory area dedicated for the storage of the\n> > + * CCS data for all compressible GEM objects.\n> > + */\n> > +#define I915_FORMAT_MOD_4_TILED_LNL_CCS fourcc_mod_code(INTEL, 16)\n> > +\n> > +/*\n> > + * Intel Color Control Surfaces (CCS) for graphics ver. 20 unified compression\n> > + * on discrete graphics\n> > + *\n> > + * The main surface is Tile 4 and at plane index 0. For semi-planar formats\n> > + * like NV12, the Y and UV planes are Tile 4 and are located at plane indices\n> > + * 0 and 1, respectively. The CCS for all planes are stored outside of the\n> > + * GEM object in a reserved memory area dedicated for the storage of the\n> > + * CCS data for all compressible GEM objects. The GEM object must be stored in\n> > + * contiguous memory with a size aligned to 64KB\n> > + */\n> > +#define I915_FORMAT_MOD_4_TILED_BMG_CCS fourcc_mod_code(INTEL, 17)\n> > +\n> > /*\n> > * IPU3 Bayer packing layout\n> > *\n> > @@ -780,7 +857,7 @@ extern \"C\" {\n> > * the 6 most significant bits in the last byte unused. The format is little\n> > * endian.\n> > */\n> > -#define IPU3_FORMAT_MOD_PACKED fourcc_mod_code(INTEL, 13)\n> > +#define IPU3_FORMAT_MOD_PACKED fourcc_mod_code(INTEL, 18)\n> >\n> > /*\n> > * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks\n> > @@ -978,14 +1055,20 @@ extern \"C\" {\n> > * 2 = Gob Height 8, Turing+ Page Kind mapping\n> > * 3 = Reserved for future use.\n> > *\n> > - * 22:22 s Sector layout. On Tegra GPUs prior to Xavier, there is a further\n> > - * bit remapping step that occurs at an even lower level than the\n> > - * page kind and block linear swizzles. This causes the layout of\n> > - * surfaces mapped in those SOC's GPUs to be incompatible with the\n> > - * equivalent mapping on other GPUs in the same system.\n> > - *\n> > - * 0 = Tegra K1 - Tegra Parker/TX2 Layout.\n> > - * 1 = Desktop GPU and Tegra Xavier+ Layout\n> > + * 22:22 s Sector layout. There is a further bit remapping step that occurs\n> > + * 26:27 at an even lower level than the page kind and block linear\n> > + * swizzles. This causes the bit arrangement of surfaces in memory\n> > + * to differ subtly, and prevents direct sharing of surfaces between\n> > + * GPUs with different layouts.\n> > + *\n> > + * 0 = Tegra K1 - Tegra Parker/TX2 Layout\n> > + * 1 = Pre-GB20x, GB20x 32+ bpp, GB10, Tegra Xavier-Orin Layout\n> > + * 2 = GB20x(Blackwell 2)+ 8 bpp surface layout\n> > + * 3 = GB20x(Blackwell 2)+ 16 bpp surface layout\n> > + * 4 = Reserved for future use.\n> > + * 5 = Reserved for future use.\n> > + * 6 = Reserved for future use.\n> > + * 7 = Reserved for future use.\n> > *\n> > * 25:23 c Lossless Framebuffer Compression type.\n> > *\n> > @@ -1000,7 +1083,7 @@ extern \"C\" {\n> > * 6 = Reserved for future use\n> > * 7 = Reserved for future use\n> > *\n> > - * 55:25 - Reserved for future use. Must be zero.\n> > + * 55:28 - Reserved for future use. Must be zero.\n> > */\n> > #define DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(c, s, g, k, h) \\\n> > \tfourcc_mod_code(NVIDIA, (0x10 | \\\n> > @@ -1008,6 +1091,7 @@ extern \"C\" {\n> > \t\t\t\t (((k) & 0xff) << 12) | \\\n> > \t\t\t\t (((g) & 0x3) << 20) | \\\n> > \t\t\t\t (((s) & 0x1) << 22) | \\\n> > +\t\t\t\t (((s) & 0x6) << 25) | \\\n> > \t\t\t\t (((c) & 0x7) << 23)))\n> >\n> > /* To grandfather in prior block linear format modifiers to the above layout,\n> > @@ -1508,6 +1592,90 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier)\n> > */\n> > #define AMLOGIC_FBC_OPTION_MEM_SAVING\t\t(1ULL << 0)\n> >\n> > +/* MediaTek modifiers\n> > + * Bits Parameter Notes\n> > + * ----- ------------------------ ---------------------------------------------\n> > + * 7: 0 TILE LAYOUT Values are MTK_FMT_MOD_TILE_*\n> > + * 15: 8 COMPRESSION Values are MTK_FMT_MOD_COMPRESS_*\n> > + * 23:16 10 BIT LAYOUT Values are MTK_FMT_MOD_10BIT_LAYOUT_*\n> > + *\n> > + */\n> > +\n> > +#define DRM_FORMAT_MOD_MTK(__flags)\t\tfourcc_mod_code(MTK, __flags)\n> > +\n> > +/*\n> > + * MediaTek Tiled Modifier\n> > + * The lowest 8 bits of the modifier is used to specify the tiling\n> > + * layout. Only the 16L_32S tiling is used for now, but we define an\n> > + * \"untiled\" version and leave room for future expansion.\n> > + */\n> > +#define MTK_FMT_MOD_TILE_MASK 0xf\n> > +#define MTK_FMT_MOD_TILE_NONE 0x0\n> > +#define MTK_FMT_MOD_TILE_16L32S 0x1\n> > +\n> > +/*\n> > + * Bits 8-15 specify compression options\n> > + */\n> > +#define MTK_FMT_MOD_COMPRESS_MASK (0xf << 8)\n> > +#define MTK_FMT_MOD_COMPRESS_NONE (0x0 << 8)\n> > +#define MTK_FMT_MOD_COMPRESS_V1 (0x1 << 8)\n> > +\n> > +/*\n> > + * Bits 16-23 specify how the bits of 10 bit formats are\n> > + * stored out in memory\n> > + */\n> > +#define MTK_FMT_MOD_10BIT_LAYOUT_MASK (0xf << 16)\n> > +#define MTK_FMT_MOD_10BIT_LAYOUT_PACKED (0x0 << 16)\n> > +#define MTK_FMT_MOD_10BIT_LAYOUT_LSBTILED (0x1 << 16)\n> > +#define MTK_FMT_MOD_10BIT_LAYOUT_LSBRASTER (0x2 << 16)\n> > +\n> > +/* alias for the most common tiling format */\n> > +#define DRM_FORMAT_MOD_MTK_16L_32S_TILE DRM_FORMAT_MOD_MTK(MTK_FMT_MOD_TILE_16L32S)\n> > +\n> > +/*\n> > + * Apple GPU-tiled layouts.\n> > + *\n> > + * Apple GPUs support nonlinear tilings with optional lossless compression.\n> > + *\n> > + * GPU-tiled images are divided into 16KiB tiles:\n> > + *\n> > + * Bytes per pixel Tile size\n> > + * --------------- ---------\n> > + * 1 128x128\n> > + * 2 128x64\n> > + * 4 64x64\n> > + * 8 64x32\n> > + * 16 32x32\n> > + *\n> > + * Tiles are raster-order. Pixels within a tile are interleaved (Morton order).\n> > + *\n> > + * Compressed images pad the body to 128-bytes and are immediately followed by a\n> > + * metadata section. The metadata section rounds the image dimensions to\n> > + * powers-of-two and contains 8 bytes for each 16x16 compression subtile.\n> > + * Subtiles are interleaved (Morton order).\n> > + *\n> > + * All images are 128-byte aligned.\n> > + *\n> > + * These layouts fundamentally do not have meaningful strides. No matter how we\n> > + * specify strides for these layouts, userspace unaware of Apple image layouts\n> > + * will be unable to use correctly the specified stride for any purpose.\n> > + * Userspace aware of the image layouts do not use strides. The most \"correct\"\n> > + * convention would be setting the image stride to 0. Unfortunately, some\n> > + * software assumes the stride is at least (width * bytes per pixel). We\n> > + * therefore require that stride equals (width * bytes per pixel). Since the\n> > + * stride is arbitrary here, we pick the simplest convention.\n> > + *\n> > + * Although containing two sections, compressed image layouts are treated in\n> > + * software as a single plane. This is modelled after AFBC, a similar\n> > + * scheme. Attempting to separate the sections to be \"explicit\" in DRM would\n> > + * only generate more confusion, as software does not treat the image this way.\n> > + *\n> > + * For detailed information on the hardware image layouts, see\n> > + * https://docs.mesa3d.org/drivers/asahi.html#image-layouts\n> > + */\n> > +#define DRM_FORMAT_MOD_APPLE_GPU_TILED fourcc_mod_code(APPLE, 1)\n> > +#define DRM_FORMAT_MOD_APPLE_GPU_TILED_COMPRESSED fourcc_mod_code(APPLE, 2)\n> > +\n> > /*\n> > * AMD modifiers\n> > *\n> > @@ -1571,6 +1739,7 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier)\n> > * 64K_D_2D on GFX12 is identical to 64K_D on GFX11.\n> > */\n> > #define AMD_FMT_MOD_TILE_GFX9_64K_D 10\n> > +#define AMD_FMT_MOD_TILE_GFX9_4K_D_X 22\n> > #define AMD_FMT_MOD_TILE_GFX9_64K_S_X 25\n> > #define AMD_FMT_MOD_TILE_GFX9_64K_D_X 26\n> > #define AMD_FMT_MOD_TILE_GFX9_64K_R_X 27\n>\n> --\n> Regards,\n>\n> Laurent Pinchart","headers":{"Return-Path":"","X-Original-To":"parsemail@patchwork.libcamera.org","Delivered-To":"parsemail@patchwork.libcamera.org","Received":["from lancelot.ideasonboard.com (lancelot.ideasonboard.com\n\t[92.243.16.209])\n\tby patchwork.libcamera.org (Postfix) with ESMTPS id 0BD93BD1F1\n\tfor ;\n\tThu, 11 Dec 2025 08:43:36 +0000 (UTC)","from lancelot.ideasonboard.com (localhost [IPv6:::1])\n\tby lancelot.ideasonboard.com (Postfix) with ESMTP id 5572D61518;\n\tThu, 11 Dec 2025 09:43:35 +0100 (CET)","from perceval.ideasonboard.com (perceval.ideasonboard.com\n\t[IPv6:2001:4b98:dc2:55:216:3eff:fef7:d647])\n\tby lancelot.ideasonboard.com (Postfix) with ESMTPS id CF82C610A6\n\tfor ;\n\tThu, 11 Dec 2025 09:43:34 +0100 (CET)","from ideasonboard.com (93-46-82-201.ip106.fastwebnet.it\n\t[93.46.82.201])\n\tby perceval.ideasonboard.com (Postfix) with ESMTPSA id B49FA1352;\n\tThu, 11 Dec 2025 09:43:32 +0100 (CET)"],"Authentication-Results":"lancelot.ideasonboard.com; dkim=pass (1024-bit key;\n\tunprotected) header.d=ideasonboard.com header.i=@ideasonboard.com\n\theader.b=\"UbpQBR8j\"; dkim-atps=neutral","DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com;\n\ts=mail; t=1765442612;\n\tbh=o6JGRkP2zvyybJ32eb7QBN0ICWoj0TNgJhbpsBUYTdY=;\n\th=Date:From:To:Cc:Subject:References:In-Reply-To:From;\n\tb=UbpQBR8jcWPFcUswUbVB3cItan5fWOWwfl2o552bjdco13dpVONsSE85h20rawnvQ\n\tigm8f5xUJUL+SmJzQTxfiA9tgCXmJ6/63rYAbwq5PefSN8iXC01n/Kv7nCYL5pQHKc\n\tHplVnM8X/Xa8NmnTel6HX66FhXwxEV6kYbK5Ks00=","Date":"Thu, 11 Dec 2025 09:43:31 +0100","From":"Jacopo Mondi ","To":"Laurent Pinchart ","Cc":"Jacopo Mondi , \n\tlibcamera-devel@lists.libcamera.org, =?utf-8?b?QmFybmFiw6FzIFDFkWN6?=\n\t=?utf-8?q?e?= ","Subject":"Re: [PATCH v2 1/6] include: linux: drm_fourcc.h: Update to v6.18","Message-ID":"","References":"<20251210-headers-update-v6-18-v2-0-3f726742a4c8@ideasonboard.com>\n\t<20251210-headers-update-v6-18-v2-1-3f726742a4c8@ideasonboard.com>\n\t<20251211012023.GG28860@pendragon.ideasonboard.com>","MIME-Version":"1.0","Content-Type":"text/plain; charset=utf-8","Content-Disposition":"inline","Content-Transfer-Encoding":"8bit","In-Reply-To":"<20251211012023.GG28860@pendragon.ideasonboard.com>","X-BeenThere":"libcamera-devel@lists.libcamera.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Errors-To":"libcamera-devel-bounces@lists.libcamera.org","Sender":"\"libcamera-devel\" "}},{"id":37289,"web_url":"https://patchwork.libcamera.org/comment/37289/","msgid":"<4m7gzcdc5kau4npra4y76cvjzzedntz3ihsxoywbbyshcy6wy7@i6gjwsprpfrt>","date":"2025-12-11T09:02:58","subject":"Re: [PATCH v2 1/6] include: linux: drm_fourcc.h: Update to v6.18","submitter":{"id":143,"url":"https://patchwork.libcamera.org/api/people/143/","name":"Jacopo Mondi","email":"jacopo.mondi@ideasonboard.com"},"content":"On Thu, Dec 11, 2025 at 09:43:31AM +0100, Jacopo Mondi wrote:\n> On Thu, Dec 11, 2025 at 10:20:23AM +0900, Laurent Pinchart wrote:\n> > On Wed, Dec 10, 2025 at 09:19:12AM +0100, Jacopo Mondi wrote:\n> > > Update drm_fourcc.h to Linux kernel version v6.18.\n> > >\n> > > As the upstream drm_fourcc.h version doesn't include definitions\n> > > for RAW Bayer formats, some of the symbols we defined\n> > > downstream now conflict with new symbols defined in mainline.\n> > >\n> > > In particular:\n> > >\n> > > and\n> > >\n> >\n> > Something seem to be missing here :-)\n> >\n>\n> Ups, dunno what happened. I'll resend\n>\n\nUh I know what happened.\n\nI pasted the defines there\n\ndefines start with #\n\nthey're treated like comments by git and discarded\n\nI've fixed this and .. see below\n\n> > > In order not to break the library ABI, maintain the downstream symbols\n> > > definitions as they are even if they conflict.\n> > >\n> > > Signed-off-by: Jacopo Mondi \n> > > Acked-by: Barnabás Pőcze \n> > > ---\n> > > include/linux/drm_fourcc.h | 191 ++++++++++++++++++++++++++++++++++++++++++---\n> > > 1 file changed, 180 insertions(+), 11 deletions(-)\n> > >\n> > > diff --git a/include/linux/drm_fourcc.h b/include/linux/drm_fourcc.h\n> > > index db6798776663086c12d321d2ed708edc7ec77f71..e428c33346bae8a8747f6834c434dc0a03eef867 100644\n> > > --- a/include/linux/drm_fourcc.h\n> > > +++ b/include/linux/drm_fourcc.h\n> > > @@ -222,7 +222,7 @@ extern \"C\" {\n> > > #define DRM_FORMAT_ABGR16161616\tfourcc_code('A', 'B', '4', '8') /* [63:0] A:B:G:R 16:16:16:16 little endian */\n> > >\n> > > /*\n> > > - * Floating point 64bpp RGB\n> > > + * Half-Floating point - 16b/component\n> > > * IEEE 754-2008 binary16 half-precision float\n> > > * [15:0] sign:exponent:mantissa 1:5:10\n> > > */\n> > > @@ -232,6 +232,20 @@ extern \"C\" {\n> > > #define DRM_FORMAT_ARGB16161616F fourcc_code('A', 'R', '4', 'H') /* [63:0] A:R:G:B 16:16:16:16 little endian */\n> > > #define DRM_FORMAT_ABGR16161616F fourcc_code('A', 'B', '4', 'H') /* [63:0] A:B:G:R 16:16:16:16 little endian */\n> > >\n> > > +#define DRM_FORMAT_R16F fourcc_code('R', ' ', ' ', 'H') /* [15:0] R 16 little endian */\n> > > +#define DRM_FORMAT_GR1616F fourcc_code('G', 'R', ' ', 'H') /* [31:0] G:R 16:16 little endian */\n> > > +#define DRM_FORMAT_BGR161616F fourcc_code('B', 'G', 'R', 'H') /* [47:0] B:G:R 16:16:16 little endian */\n> > > +\n> > > +/*\n> > > + * Floating point - 32b/component\n> > > + * IEEE 754-2008 binary32 float\n> > > + * [31:0] sign:exponent:mantissa 1:8:23\n> > > + */\n> > > +#define DRM_FORMAT_R32F fourcc_code('R', ' ', ' ', 'F') /* [31:0] R 32 little endian */\n> > > +#define DRM_FORMAT_GR3232F fourcc_code('G', 'R', ' ', 'F') /* [63:0] R:G 32:32 little endian */\n> > > +#define DRM_FORMAT_BGR323232F fourcc_code('B', 'G', 'R', 'F') /* [95:0] R:G:B 32:32:32 little endian */\n> > > +#define DRM_FORMAT_ABGR32323232F fourcc_code('A', 'B', '8', 'F') /* [127:0] R:G:B:A 32:32:32:32 little endian */\n> > > +\n> > > /*\n> > > * RGBA format with 10-bit components packed in 64-bit per pixel, with 6 bits\n> > > * of unused padding per component:\n> > > @@ -381,6 +395,42 @@ extern \"C\" {\n> > > */\n> > > #define DRM_FORMAT_Q401\t\tfourcc_code('Q', '4', '0', '1')\n> > >\n> > > +/*\n> > > + * 3 plane YCbCr LSB aligned\n> > > + * In order to use these formats in a similar fashion to MSB aligned ones\n> > > + * implementation can multiply the values by 2^6=64. For that reason the padding\n> > > + * must only contain zeros.\n> > > + * index 0 = Y plane, [15:0] z:Y [6:10] little endian\n> > > + * index 1 = Cr plane, [15:0] z:Cr [6:10] little endian\n> > > + * index 2 = Cb plane, [15:0] z:Cb [6:10] little endian\n> > > + */\n> > > +#define DRM_FORMAT_S010\tfourcc_code('S', '0', '1', '0') /* 2x2 subsampled Cb (1) and Cr (2) planes 10 bits per channel */\n> > > +#define DRM_FORMAT_S210\tfourcc_code('S', '2', '1', '0') /* 2x1 subsampled Cb (1) and Cr (2) planes 10 bits per channel */\n> > > +#define DRM_FORMAT_S410\tfourcc_code('S', '4', '1', '0') /* non-subsampled Cb (1) and Cr (2) planes 10 bits per channel */\n> > > +\n> > > +/*\n> > > + * 3 plane YCbCr LSB aligned\n> > > + * In order to use these formats in a similar fashion to MSB aligned ones\n> > > + * implementation can multiply the values by 2^4=16. For that reason the padding\n> > > + * must only contain zeros.\n> > > + * index 0 = Y plane, [15:0] z:Y [4:12] little endian\n> > > + * index 1 = Cr plane, [15:0] z:Cr [4:12] little endian\n> > > + * index 2 = Cb plane, [15:0] z:Cb [4:12] little endian\n> > > + */\n> > > +#define DRM_FORMAT_S012\tfourcc_code('S', '0', '1', '2') /* 2x2 subsampled Cb (1) and Cr (2) planes 12 bits per channel */\n> > > +#define DRM_FORMAT_S212\tfourcc_code('S', '2', '1', '2') /* 2x1 subsampled Cb (1) and Cr (2) planes 12 bits per channel */\n> > > +#define DRM_FORMAT_S412\tfourcc_code('S', '4', '1', '2') /* non-subsampled Cb (1) and Cr (2) planes 12 bits per channel */\n> > > +\n> > > +/*\n> > > + * 3 plane YCbCr\n> > > + * index 0 = Y plane, [15:0] Y little endian\n> > > + * index 1 = Cr plane, [15:0] Cr little endian\n> > > + * index 2 = Cb plane, [15:0] Cb little endian\n> > > + */\n> > > +#define DRM_FORMAT_S016\tfourcc_code('S', '0', '1', '6') /* 2x2 subsampled Cb (1) and Cr (2) planes 16 bits per channel */\n> > > +#define DRM_FORMAT_S216\tfourcc_code('S', '2', '1', '6') /* 2x1 subsampled Cb (1) and Cr (2) planes 16 bits per channel */\n> > > +#define DRM_FORMAT_S416\tfourcc_code('S', '4', '1', '6') /* non-subsampled Cb (1) and Cr (2) planes 16 bits per channel */\n> > > +\n> > > /*\n> > > * 3 plane YCbCr\n> > > * index 0: Y plane, [7:0] Y\n> > > @@ -489,6 +539,8 @@ extern \"C\" {\n> > > #define DRM_FORMAT_MOD_VENDOR_ARM 0x08\n> > > #define DRM_FORMAT_MOD_VENDOR_ALLWINNER 0x09\n> > > #define DRM_FORMAT_MOD_VENDOR_AMLOGIC 0x0a\n> > > +#define DRM_FORMAT_MOD_VENDOR_MTK 0x0b\n> > > +#define DRM_FORMAT_MOD_VENDOR_APPLE 0x0c\n> > > #define DRM_FORMAT_MOD_VENDOR_MIPI 0x0b\n> > > #define DRM_FORMAT_MOD_VENDOR_RPI 0x0c\n> > >\n> > > @@ -772,6 +824,31 @@ extern \"C\" {\n> > > */\n> > > #define I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC fourcc_mod_code(INTEL, 15)\n> > >\n> > > +/*\n> > > + * Intel Color Control Surfaces (CCS) for graphics ver. 20 unified compression\n> > > + * on integrated graphics\n> > > + *\n> > > + * The main surface is Tile 4 and at plane index 0. For semi-planar formats\n> > > + * like NV12, the Y and UV planes are Tile 4 and are located at plane indices\n> > > + * 0 and 1, respectively. The CCS for all planes are stored outside of the\n> > > + * GEM object in a reserved memory area dedicated for the storage of the\n> > > + * CCS data for all compressible GEM objects.\n> > > + */\n> > > +#define I915_FORMAT_MOD_4_TILED_LNL_CCS fourcc_mod_code(INTEL, 16)\n> > > +\n> > > +/*\n> > > + * Intel Color Control Surfaces (CCS) for graphics ver. 20 unified compression\n> > > + * on discrete graphics\n> > > + *\n> > > + * The main surface is Tile 4 and at plane index 0. For semi-planar formats\n> > > + * like NV12, the Y and UV planes are Tile 4 and are located at plane indices\n> > > + * 0 and 1, respectively. The CCS for all planes are stored outside of the\n> > > + * GEM object in a reserved memory area dedicated for the storage of the\n> > > + * CCS data for all compressible GEM objects. The GEM object must be stored in\n> > > + * contiguous memory with a size aligned to 64KB\n> > > + */\n> > > +#define I915_FORMAT_MOD_4_TILED_BMG_CCS fourcc_mod_code(INTEL, 17)\n> > > +\n> > > /*\n> > > * IPU3 Bayer packing layout\n> > > *\n> > > @@ -780,7 +857,7 @@ extern \"C\" {\n> > > * the 6 most significant bits in the last byte unused. The format is little\n> > > * endian.\n> > > */\n> > > -#define IPU3_FORMAT_MOD_PACKED fourcc_mod_code(INTEL, 13)\n> > > +#define IPU3_FORMAT_MOD_PACKED fourcc_mod_code(INTEL, 18)\n> > >\n\nI've restored this as well, following the same logic as per the other\nconflicting symbols. I should have done it in this version already.\n\nThanks\n j\n\n> > > /*\n> > > * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks\n> > > @@ -978,14 +1055,20 @@ extern \"C\" {\n> > > * 2 = Gob Height 8, Turing+ Page Kind mapping\n> > > * 3 = Reserved for future use.\n> > > *\n> > > - * 22:22 s Sector layout. On Tegra GPUs prior to Xavier, there is a further\n> > > - * bit remapping step that occurs at an even lower level than the\n> > > - * page kind and block linear swizzles. This causes the layout of\n> > > - * surfaces mapped in those SOC's GPUs to be incompatible with the\n> > > - * equivalent mapping on other GPUs in the same system.\n> > > - *\n> > > - * 0 = Tegra K1 - Tegra Parker/TX2 Layout.\n> > > - * 1 = Desktop GPU and Tegra Xavier+ Layout\n> > > + * 22:22 s Sector layout. There is a further bit remapping step that occurs\n> > > + * 26:27 at an even lower level than the page kind and block linear\n> > > + * swizzles. This causes the bit arrangement of surfaces in memory\n> > > + * to differ subtly, and prevents direct sharing of surfaces between\n> > > + * GPUs with different layouts.\n> > > + *\n> > > + * 0 = Tegra K1 - Tegra Parker/TX2 Layout\n> > > + * 1 = Pre-GB20x, GB20x 32+ bpp, GB10, Tegra Xavier-Orin Layout\n> > > + * 2 = GB20x(Blackwell 2)+ 8 bpp surface layout\n> > > + * 3 = GB20x(Blackwell 2)+ 16 bpp surface layout\n> > > + * 4 = Reserved for future use.\n> > > + * 5 = Reserved for future use.\n> > > + * 6 = Reserved for future use.\n> > > + * 7 = Reserved for future use.\n> > > *\n> > > * 25:23 c Lossless Framebuffer Compression type.\n> > > *\n> > > @@ -1000,7 +1083,7 @@ extern \"C\" {\n> > > * 6 = Reserved for future use\n> > > * 7 = Reserved for future use\n> > > *\n> > > - * 55:25 - Reserved for future use. Must be zero.\n> > > + * 55:28 - Reserved for future use. Must be zero.\n> > > */\n> > > #define DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(c, s, g, k, h) \\\n> > > \tfourcc_mod_code(NVIDIA, (0x10 | \\\n> > > @@ -1008,6 +1091,7 @@ extern \"C\" {\n> > > \t\t\t\t (((k) & 0xff) << 12) | \\\n> > > \t\t\t\t (((g) & 0x3) << 20) | \\\n> > > \t\t\t\t (((s) & 0x1) << 22) | \\\n> > > +\t\t\t\t (((s) & 0x6) << 25) | \\\n> > > \t\t\t\t (((c) & 0x7) << 23)))\n> > >\n> > > /* To grandfather in prior block linear format modifiers to the above layout,\n> > > @@ -1508,6 +1592,90 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier)\n> > > */\n> > > #define AMLOGIC_FBC_OPTION_MEM_SAVING\t\t(1ULL << 0)\n> > >\n> > > +/* MediaTek modifiers\n> > > + * Bits Parameter Notes\n> > > + * ----- ------------------------ ---------------------------------------------\n> > > + * 7: 0 TILE LAYOUT Values are MTK_FMT_MOD_TILE_*\n> > > + * 15: 8 COMPRESSION Values are MTK_FMT_MOD_COMPRESS_*\n> > > + * 23:16 10 BIT LAYOUT Values are MTK_FMT_MOD_10BIT_LAYOUT_*\n> > > + *\n> > > + */\n> > > +\n> > > +#define DRM_FORMAT_MOD_MTK(__flags)\t\tfourcc_mod_code(MTK, __flags)\n> > > +\n> > > +/*\n> > > + * MediaTek Tiled Modifier\n> > > + * The lowest 8 bits of the modifier is used to specify the tiling\n> > > + * layout. Only the 16L_32S tiling is used for now, but we define an\n> > > + * \"untiled\" version and leave room for future expansion.\n> > > + */\n> > > +#define MTK_FMT_MOD_TILE_MASK 0xf\n> > > +#define MTK_FMT_MOD_TILE_NONE 0x0\n> > > +#define MTK_FMT_MOD_TILE_16L32S 0x1\n> > > +\n> > > +/*\n> > > + * Bits 8-15 specify compression options\n> > > + */\n> > > +#define MTK_FMT_MOD_COMPRESS_MASK (0xf << 8)\n> > > +#define MTK_FMT_MOD_COMPRESS_NONE (0x0 << 8)\n> > > +#define MTK_FMT_MOD_COMPRESS_V1 (0x1 << 8)\n> > > +\n> > > +/*\n> > > + * Bits 16-23 specify how the bits of 10 bit formats are\n> > > + * stored out in memory\n> > > + */\n> > > +#define MTK_FMT_MOD_10BIT_LAYOUT_MASK (0xf << 16)\n> > > +#define MTK_FMT_MOD_10BIT_LAYOUT_PACKED (0x0 << 16)\n> > > +#define MTK_FMT_MOD_10BIT_LAYOUT_LSBTILED (0x1 << 16)\n> > > +#define MTK_FMT_MOD_10BIT_LAYOUT_LSBRASTER (0x2 << 16)\n> > > +\n> > > +/* alias for the most common tiling format */\n> > > +#define DRM_FORMAT_MOD_MTK_16L_32S_TILE DRM_FORMAT_MOD_MTK(MTK_FMT_MOD_TILE_16L32S)\n> > > +\n> > > +/*\n> > > + * Apple GPU-tiled layouts.\n> > > + *\n> > > + * Apple GPUs support nonlinear tilings with optional lossless compression.\n> > > + *\n> > > + * GPU-tiled images are divided into 16KiB tiles:\n> > > + *\n> > > + * Bytes per pixel Tile size\n> > > + * --------------- ---------\n> > > + * 1 128x128\n> > > + * 2 128x64\n> > > + * 4 64x64\n> > > + * 8 64x32\n> > > + * 16 32x32\n> > > + *\n> > > + * Tiles are raster-order. Pixels within a tile are interleaved (Morton order).\n> > > + *\n> > > + * Compressed images pad the body to 128-bytes and are immediately followed by a\n> > > + * metadata section. The metadata section rounds the image dimensions to\n> > > + * powers-of-two and contains 8 bytes for each 16x16 compression subtile.\n> > > + * Subtiles are interleaved (Morton order).\n> > > + *\n> > > + * All images are 128-byte aligned.\n> > > + *\n> > > + * These layouts fundamentally do not have meaningful strides. No matter how we\n> > > + * specify strides for these layouts, userspace unaware of Apple image layouts\n> > > + * will be unable to use correctly the specified stride for any purpose.\n> > > + * Userspace aware of the image layouts do not use strides. The most \"correct\"\n> > > + * convention would be setting the image stride to 0. Unfortunately, some\n> > > + * software assumes the stride is at least (width * bytes per pixel). We\n> > > + * therefore require that stride equals (width * bytes per pixel). Since the\n> > > + * stride is arbitrary here, we pick the simplest convention.\n> > > + *\n> > > + * Although containing two sections, compressed image layouts are treated in\n> > > + * software as a single plane. This is modelled after AFBC, a similar\n> > > + * scheme. Attempting to separate the sections to be \"explicit\" in DRM would\n> > > + * only generate more confusion, as software does not treat the image this way.\n> > > + *\n> > > + * For detailed information on the hardware image layouts, see\n> > > + * https://docs.mesa3d.org/drivers/asahi.html#image-layouts\n> > > + */\n> > > +#define DRM_FORMAT_MOD_APPLE_GPU_TILED fourcc_mod_code(APPLE, 1)\n> > > +#define DRM_FORMAT_MOD_APPLE_GPU_TILED_COMPRESSED fourcc_mod_code(APPLE, 2)\n> > > +\n> > > /*\n> > > * AMD modifiers\n> > > *\n> > > @@ -1571,6 +1739,7 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier)\n> > > * 64K_D_2D on GFX12 is identical to 64K_D on GFX11.\n> > > */\n> > > #define AMD_FMT_MOD_TILE_GFX9_64K_D 10\n> > > +#define AMD_FMT_MOD_TILE_GFX9_4K_D_X 22\n> > > #define AMD_FMT_MOD_TILE_GFX9_64K_S_X 25\n> > > #define AMD_FMT_MOD_TILE_GFX9_64K_D_X 26\n> > > #define AMD_FMT_MOD_TILE_GFX9_64K_R_X 27\n> >\n> > --\n> > Regards,\n> >\n> > Laurent Pinchart","headers":{"Return-Path":"","X-Original-To":"parsemail@patchwork.libcamera.org","Delivered-To":"parsemail@patchwork.libcamera.org","Received":["from lancelot.ideasonboard.com (lancelot.ideasonboard.com\n\t[92.243.16.209])\n\tby patchwork.libcamera.org (Postfix) with ESMTPS id 307CBC3257\n\tfor ;\n\tThu, 11 Dec 2025 09:03:04 +0000 (UTC)","from lancelot.ideasonboard.com (localhost [IPv6:::1])\n\tby lancelot.ideasonboard.com (Postfix) with ESMTP id 4B8C461594;\n\tThu, 11 Dec 2025 10:03:03 +0100 (CET)","from perceval.ideasonboard.com (perceval.ideasonboard.com\n\t[213.167.242.64])\n\tby lancelot.ideasonboard.com (Postfix) with ESMTPS id DE0A3610A6\n\tfor ;\n\tThu, 11 Dec 2025 10:03:01 +0100 (CET)","from ideasonboard.com (93-46-82-201.ip106.fastwebnet.it\n\t[93.46.82.201])\n\tby perceval.ideasonboard.com (Postfix) with ESMTPSA id BAB75667;\n\tThu, 11 Dec 2025 10:02:59 +0100 (CET)"],"Authentication-Results":"lancelot.ideasonboard.com; dkim=pass (1024-bit key;\n\tunprotected) header.d=ideasonboard.com header.i=@ideasonboard.com\n\theader.b=\"aT68HUSj\"; dkim-atps=neutral","DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com;\n\ts=mail; t=1765443779;\n\tbh=QQse2szr58XrtOkxUnD0vElDcxVzVRWqL5HN/FscEDE=;\n\th=Date:From:To:Cc:Subject:References:In-Reply-To:From;\n\tb=aT68HUSjSDq+PRPULLQlYYo9od/RIoa7HDTOB1AiZxQv0HW5L6+VhJe2u5OzsUE06\n\tugO7s9hWau5uUwQgYuS2QK/2KOUIsLEU/m3vEJzxMbH6T2W0xNveW5fzXgqG9bBuDN\n\tznbWZg44lsa2elTplOBjVYpxhrpa6DNLlh65vtsY=","Date":"Thu, 11 Dec 2025 10:02:58 +0100","From":"Jacopo Mondi ","To":"Jacopo Mondi ","Cc":"Laurent Pinchart , \n\tlibcamera-devel@lists.libcamera.org, =?utf-8?b?QmFybmFiw6FzIFDFkWN6?=\n\t=?utf-8?q?e?= ","Subject":"Re: [PATCH v2 1/6] include: linux: drm_fourcc.h: Update to v6.18","Message-ID":"<4m7gzcdc5kau4npra4y76cvjzzedntz3ihsxoywbbyshcy6wy7@i6gjwsprpfrt>","References":"<20251210-headers-update-v6-18-v2-0-3f726742a4c8@ideasonboard.com>\n\t<20251210-headers-update-v6-18-v2-1-3f726742a4c8@ideasonboard.com>\n\t<20251211012023.GG28860@pendragon.ideasonboard.com>\n\t","MIME-Version":"1.0","Content-Type":"text/plain; charset=utf-8","Content-Disposition":"inline","Content-Transfer-Encoding":"8bit","In-Reply-To":"","X-BeenThere":"libcamera-devel@lists.libcamera.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Errors-To":"libcamera-devel-bounces@lists.libcamera.org","Sender":"\"libcamera-devel\" "}}]