{"id":2240,"url":"https://patchwork.libcamera.org/api/patches/2240/?format=json","web_url":"https://patchwork.libcamera.org/patch/2240/","project":{"id":1,"url":"https://patchwork.libcamera.org/api/projects/1/?format=json","name":"libcamera","link_name":"libcamera","list_id":"libcamera_core","list_email":"libcamera-devel@lists.libcamera.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20191027234312.35284-3-jacopo@jmondi.org>","date":"2019-10-27T23:43:04","name":"[libcamera-devel,02/10] include: linux: Import DRM/KMS headers from Linux v5.2","commit_ref":null,"pull_url":null,"state":"accepted","archived":false,"hash":"28f7f74c51f002cc90aa0ee1a982c09fa6f14949","submitter":{"id":3,"url":"https://patchwork.libcamera.org/api/people/3/?format=json","name":"Jacopo Mondi","email":"jacopo@jmondi.org"},"delegate":null,"mbox":"https://patchwork.libcamera.org/patch/2240/mbox/","series":[{"id":559,"url":"https://patchwork.libcamera.org/api/series/559/?format=json","web_url":"https://patchwork.libcamera.org/project/libcamera/list/?series=559","date":"2019-10-27T23:43:02","name":"libcamera: Use DRM_FORMAT_* fourcc codes","version":1,"mbox":"https://patchwork.libcamera.org/series/559/mbox/"}],"comments":"https://patchwork.libcamera.org/api/patches/2240/comments/","check":"pending","checks":"https://patchwork.libcamera.org/api/patches/2240/checks/","tags":{},"headers":{"Return-Path":"","Received":["from relay7-d.mail.gandi.net (relay7-d.mail.gandi.net\n\t[217.70.183.200])\n\tby lancelot.ideasonboard.com (Postfix) with ESMTPS id 8537A6017F\n\tfor ;\n\tMon, 28 Oct 2019 00:41:26 +0100 (CET)","from uno.localdomain (143.121.2.93.rev.sfr.net [93.2.121.143])\n\t(Authenticated sender: jacopo@jmondi.org)\n\tby relay7-d.mail.gandi.net (Postfix) with ESMTPSA id E0B2C20003;\n\tSun, 27 Oct 2019 23:41:25 +0000 (UTC)"],"X-Originating-IP":"93.2.121.143","From":"Jacopo Mondi ","To":"libcamera-devel@lists.libcamera.org","Date":"Mon, 28 Oct 2019 00:43:04 +0100","Message-Id":"<20191027234312.35284-3-jacopo@jmondi.org>","X-Mailer":"git-send-email 2.23.0","In-Reply-To":"<20191027234312.35284-1-jacopo@jmondi.org>","References":"<20191027234312.35284-1-jacopo@jmondi.org>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","Subject":"[libcamera-devel] [PATCH 02/10] include: linux: Import DRM/KMS\n\theaders from Linux v5.2","X-BeenThere":"libcamera-devel@lists.libcamera.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","X-List-Received-Date":"Sun, 27 Oct 2019 23:41:26 -0000"},"content":"Import DRM/KMS header files from Linux kernel v5.2.\n\nThe DRM headers are used to prepare to use the DRM defined fourcc\npixel formats in place of the currently used V4L2_PIX_FMT_ ones.\n\nSigned-off-by: Jacopo Mondi \n---\n include/linux/drm.h | 1042 ++++++++++++++++++++++++++++++++++++\n include/linux/drm_fourcc.h | 763 ++++++++++++++++++++++++++\n include/linux/drm_mode.h | 1032 +++++++++++++++++++++++++++++++++++\n 3 files changed, 2837 insertions(+)\n create mode 100644 include/linux/drm.h\n create mode 100644 include/linux/drm_fourcc.h\n create mode 100644 include/linux/drm_mode.h","diff":"diff --git a/include/linux/drm.h b/include/linux/drm.h\nnew file mode 100644\nindex 000000000000..438abde3621d\n--- /dev/null\n+++ b/include/linux/drm.h\n@@ -0,0 +1,1042 @@\n+/**\n+ * \\file drm.h\n+ * Header for the Direct Rendering Manager\n+ *\n+ * \\author Rickard E. (Rik) Faith \n+ *\n+ * \\par Acknowledgments:\n+ * Dec 1999, Richard Henderson , move to generic \\c cmpxchg.\n+ */\n+\n+/*\n+ * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.\n+ * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.\n+ * All rights reserved.\n+ *\n+ * Permission is hereby granted, free of charge, to any person obtaining a\n+ * copy of this software and associated documentation files (the \"Software\"),\n+ * to deal in the Software without restriction, including without limitation\n+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n+ * and/or sell copies of the Software, and to permit persons to whom the\n+ * Software is furnished to do so, subject to the following conditions:\n+ *\n+ * The above copyright notice and this permission notice (including the next\n+ * paragraph) shall be included in all copies or substantial portions of the\n+ * Software.\n+ *\n+ * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n+ * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR\n+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,\n+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n+ * OTHER DEALINGS IN THE SOFTWARE.\n+ */\n+\n+#ifndef _DRM_H_\n+#define _DRM_H_\n+\n+#if defined(__linux__)\n+\n+#include \n+#include \n+typedef unsigned int drm_handle_t;\n+\n+#else /* One of the BSDs */\n+\n+#include \n+#include \n+#include \n+typedef int8_t __s8;\n+typedef uint8_t __u8;\n+typedef int16_t __s16;\n+typedef uint16_t __u16;\n+typedef int32_t __s32;\n+typedef uint32_t __u32;\n+typedef int64_t __s64;\n+typedef uint64_t __u64;\n+typedef size_t __kernel_size_t;\n+typedef unsigned long drm_handle_t;\n+\n+#endif\n+\n+#if defined(__cplusplus)\n+extern \"C\" {\n+#endif\n+\n+#define DRM_NAME\t\"drm\"\t /**< Name in kernel, /dev, and /proc */\n+#define DRM_MIN_ORDER\t5\t /**< At least 2^5 bytes = 32 bytes */\n+#define DRM_MAX_ORDER\t22\t /**< Up to 2^22 bytes = 4MB */\n+#define DRM_RAM_PERCENT 10\t /**< How much system ram can we lock? */\n+\n+#define _DRM_LOCK_HELD\t0x80000000U /**< Hardware lock is held */\n+#define _DRM_LOCK_CONT\t0x40000000U /**< Hardware lock is contended */\n+#define _DRM_LOCK_IS_HELD(lock)\t ((lock) & _DRM_LOCK_HELD)\n+#define _DRM_LOCK_IS_CONT(lock)\t ((lock) & _DRM_LOCK_CONT)\n+#define _DRM_LOCKING_CONTEXT(lock) ((lock) & ~(_DRM_LOCK_HELD|_DRM_LOCK_CONT))\n+\n+typedef unsigned int drm_context_t;\n+typedef unsigned int drm_drawable_t;\n+typedef unsigned int drm_magic_t;\n+\n+/**\n+ * Cliprect.\n+ *\n+ * \\warning: If you change this structure, make sure you change\n+ * XF86DRIClipRectRec in the server as well\n+ *\n+ * \\note KW: Actually it's illegal to change either for\n+ * backwards-compatibility reasons.\n+ */\n+struct drm_clip_rect {\n+\tunsigned short x1;\n+\tunsigned short y1;\n+\tunsigned short x2;\n+\tunsigned short y2;\n+};\n+\n+/**\n+ * Drawable information.\n+ */\n+struct drm_drawable_info {\n+\tunsigned int num_rects;\n+\tstruct drm_clip_rect *rects;\n+};\n+\n+/**\n+ * Texture region,\n+ */\n+struct drm_tex_region {\n+\tunsigned char next;\n+\tunsigned char prev;\n+\tunsigned char in_use;\n+\tunsigned char padding;\n+\tunsigned int age;\n+};\n+\n+/**\n+ * Hardware lock.\n+ *\n+ * The lock structure is a simple cache-line aligned integer. To avoid\n+ * processor bus contention on a multiprocessor system, there should not be any\n+ * other data stored in the same cache line.\n+ */\n+struct drm_hw_lock {\n+\t__volatile__ unsigned int lock;\t\t/**< lock variable */\n+\tchar padding[60];\t\t\t/**< Pad to cache line */\n+};\n+\n+/**\n+ * DRM_IOCTL_VERSION ioctl argument type.\n+ *\n+ * \\sa drmGetVersion().\n+ */\n+struct drm_version {\n+\tint version_major;\t /**< Major version */\n+\tint version_minor;\t /**< Minor version */\n+\tint version_patchlevel;\t /**< Patch level */\n+\t__kernel_size_t name_len;\t /**< Length of name buffer */\n+\tchar *name;\t /**< Name of driver */\n+\t__kernel_size_t date_len;\t /**< Length of date buffer */\n+\tchar *date;\t /**< User-space buffer to hold date */\n+\t__kernel_size_t desc_len;\t /**< Length of desc buffer */\n+\tchar *desc;\t /**< User-space buffer to hold desc */\n+};\n+\n+/**\n+ * DRM_IOCTL_GET_UNIQUE ioctl argument type.\n+ *\n+ * \\sa drmGetBusid() and drmSetBusId().\n+ */\n+struct drm_unique {\n+\t__kernel_size_t unique_len;\t /**< Length of unique */\n+\tchar *unique;\t /**< Unique name for driver instantiation */\n+};\n+\n+struct drm_list {\n+\tint count;\t\t /**< Length of user-space structures */\n+\tstruct drm_version *version;\n+};\n+\n+struct drm_block {\n+\tint unused;\n+};\n+\n+/**\n+ * DRM_IOCTL_CONTROL ioctl argument type.\n+ *\n+ * \\sa drmCtlInstHandler() and drmCtlUninstHandler().\n+ */\n+struct drm_control {\n+\tenum {\n+\t\tDRM_ADD_COMMAND,\n+\t\tDRM_RM_COMMAND,\n+\t\tDRM_INST_HANDLER,\n+\t\tDRM_UNINST_HANDLER\n+\t} func;\n+\tint irq;\n+};\n+\n+/**\n+ * Type of memory to map.\n+ */\n+enum drm_map_type {\n+\t_DRM_FRAME_BUFFER = 0,\t /**< WC (no caching), no core dump */\n+\t_DRM_REGISTERS = 1,\t /**< no caching, no core dump */\n+\t_DRM_SHM = 2,\t\t /**< shared, cached */\n+\t_DRM_AGP = 3,\t\t /**< AGP/GART */\n+\t_DRM_SCATTER_GATHER = 4, /**< Scatter/gather memory for PCI DMA */\n+\t_DRM_CONSISTENT = 5\t /**< Consistent memory for PCI DMA */\n+};\n+\n+/**\n+ * Memory mapping flags.\n+ */\n+enum drm_map_flags {\n+\t_DRM_RESTRICTED = 0x01,\t /**< Cannot be mapped to user-virtual */\n+\t_DRM_READ_ONLY = 0x02,\n+\t_DRM_LOCKED = 0x04,\t /**< shared, cached, locked */\n+\t_DRM_KERNEL = 0x08,\t /**< kernel requires access */\n+\t_DRM_WRITE_COMBINING = 0x10, /**< use write-combining if available */\n+\t_DRM_CONTAINS_LOCK = 0x20, /**< SHM page that contains lock */\n+\t_DRM_REMOVABLE = 0x40,\t /**< Removable mapping */\n+\t_DRM_DRIVER = 0x80\t /**< Managed by driver */\n+};\n+\n+struct drm_ctx_priv_map {\n+\tunsigned int ctx_id;\t /**< Context requesting private mapping */\n+\tvoid *handle;\t\t /**< Handle of map */\n+};\n+\n+/**\n+ * DRM_IOCTL_GET_MAP, DRM_IOCTL_ADD_MAP and DRM_IOCTL_RM_MAP ioctls\n+ * argument type.\n+ *\n+ * \\sa drmAddMap().\n+ */\n+struct drm_map {\n+\tunsigned long offset;\t /**< Requested physical address (0 for SAREA)*/\n+\tunsigned long size;\t /**< Requested physical size (bytes) */\n+\tenum drm_map_type type;\t /**< Type of memory to map */\n+\tenum drm_map_flags flags;\t /**< Flags */\n+\tvoid *handle;\t\t /**< User-space: \"Handle\" to pass to mmap() */\n+\t\t\t\t /**< Kernel-space: kernel-virtual address */\n+\tint mtrr;\t\t /**< MTRR slot used */\n+\t/* Private data */\n+};\n+\n+/**\n+ * DRM_IOCTL_GET_CLIENT ioctl argument type.\n+ */\n+struct drm_client {\n+\tint idx;\t\t/**< Which client desired? */\n+\tint auth;\t\t/**< Is client authenticated? */\n+\tunsigned long pid;\t/**< Process ID */\n+\tunsigned long uid;\t/**< User ID */\n+\tunsigned long magic;\t/**< Magic */\n+\tunsigned long iocs;\t/**< Ioctl count */\n+};\n+\n+enum drm_stat_type {\n+\t_DRM_STAT_LOCK,\n+\t_DRM_STAT_OPENS,\n+\t_DRM_STAT_CLOSES,\n+\t_DRM_STAT_IOCTLS,\n+\t_DRM_STAT_LOCKS,\n+\t_DRM_STAT_UNLOCKS,\n+\t_DRM_STAT_VALUE,\t/**< Generic value */\n+\t_DRM_STAT_BYTE,\t\t/**< Generic byte counter (1024bytes/K) */\n+\t_DRM_STAT_COUNT,\t/**< Generic non-byte counter (1000/k) */\n+\n+\t_DRM_STAT_IRQ,\t\t/**< IRQ */\n+\t_DRM_STAT_PRIMARY,\t/**< Primary DMA bytes */\n+\t_DRM_STAT_SECONDARY,\t/**< Secondary DMA bytes */\n+\t_DRM_STAT_DMA,\t\t/**< DMA */\n+\t_DRM_STAT_SPECIAL,\t/**< Special DMA (e.g., priority or polled) */\n+\t_DRM_STAT_MISSED\t/**< Missed DMA opportunity */\n+\t /* Add to the *END* of the list */\n+};\n+\n+/**\n+ * DRM_IOCTL_GET_STATS ioctl argument type.\n+ */\n+struct drm_stats {\n+\tunsigned long count;\n+\tstruct {\n+\t\tunsigned long value;\n+\t\tenum drm_stat_type type;\n+\t} data[15];\n+};\n+\n+/**\n+ * Hardware locking flags.\n+ */\n+enum drm_lock_flags {\n+\t_DRM_LOCK_READY = 0x01,\t /**< Wait until hardware is ready for DMA */\n+\t_DRM_LOCK_QUIESCENT = 0x02, /**< Wait until hardware quiescent */\n+\t_DRM_LOCK_FLUSH = 0x04,\t /**< Flush this context's DMA queue first */\n+\t_DRM_LOCK_FLUSH_ALL = 0x08, /**< Flush all DMA queues first */\n+\t/* These *HALT* flags aren't supported yet\n+\t -- they will be used to support the\n+\t full-screen DGA-like mode. */\n+\t_DRM_HALT_ALL_QUEUES = 0x10, /**< Halt all current and future queues */\n+\t_DRM_HALT_CUR_QUEUES = 0x20 /**< Halt all current queues */\n+};\n+\n+/**\n+ * DRM_IOCTL_LOCK, DRM_IOCTL_UNLOCK and DRM_IOCTL_FINISH ioctl argument type.\n+ *\n+ * \\sa drmGetLock() and drmUnlock().\n+ */\n+struct drm_lock {\n+\tint context;\n+\tenum drm_lock_flags flags;\n+};\n+\n+/**\n+ * DMA flags\n+ *\n+ * \\warning\n+ * These values \\e must match xf86drm.h.\n+ *\n+ * \\sa drm_dma.\n+ */\n+enum drm_dma_flags {\n+\t/* Flags for DMA buffer dispatch */\n+\t_DRM_DMA_BLOCK = 0x01,\t /**<\n+\t\t\t\t * Block until buffer dispatched.\n+\t\t\t\t *\n+\t\t\t\t * \\note The buffer may not yet have\n+\t\t\t\t * been processed by the hardware --\n+\t\t\t\t * getting a hardware lock with the\n+\t\t\t\t * hardware quiescent will ensure\n+\t\t\t\t * that the buffer has been\n+\t\t\t\t * processed.\n+\t\t\t\t */\n+\t_DRM_DMA_WHILE_LOCKED = 0x02, /**< Dispatch while lock held */\n+\t_DRM_DMA_PRIORITY = 0x04, /**< High priority dispatch */\n+\n+\t/* Flags for DMA buffer request */\n+\t_DRM_DMA_WAIT = 0x10,\t /**< Wait for free buffers */\n+\t_DRM_DMA_SMALLER_OK = 0x20, /**< Smaller-than-requested buffers OK */\n+\t_DRM_DMA_LARGER_OK = 0x40 /**< Larger-than-requested buffers OK */\n+};\n+\n+/**\n+ * DRM_IOCTL_ADD_BUFS and DRM_IOCTL_MARK_BUFS ioctl argument type.\n+ *\n+ * \\sa drmAddBufs().\n+ */\n+struct drm_buf_desc {\n+\tint count;\t\t /**< Number of buffers of this size */\n+\tint size;\t\t /**< Size in bytes */\n+\tint low_mark;\t\t /**< Low water mark */\n+\tint high_mark;\t\t /**< High water mark */\n+\tenum {\n+\t\t_DRM_PAGE_ALIGN = 0x01,\t/**< Align on page boundaries for DMA */\n+\t\t_DRM_AGP_BUFFER = 0x02,\t/**< Buffer is in AGP space */\n+\t\t_DRM_SG_BUFFER = 0x04,\t/**< Scatter/gather memory buffer */\n+\t\t_DRM_FB_BUFFER = 0x08,\t/**< Buffer is in frame buffer */\n+\t\t_DRM_PCI_BUFFER_RO = 0x10 /**< Map PCI DMA buffer read-only */\n+\t} flags;\n+\tunsigned long agp_start; /**<\n+\t\t\t\t * Start address of where the AGP buffers are\n+\t\t\t\t * in the AGP aperture\n+\t\t\t\t */\n+};\n+\n+/**\n+ * DRM_IOCTL_INFO_BUFS ioctl argument type.\n+ */\n+struct drm_buf_info {\n+\tint count;\t\t/**< Entries in list */\n+\tstruct drm_buf_desc *list;\n+};\n+\n+/**\n+ * DRM_IOCTL_FREE_BUFS ioctl argument type.\n+ */\n+struct drm_buf_free {\n+\tint count;\n+\tint *list;\n+};\n+\n+/**\n+ * Buffer information\n+ *\n+ * \\sa drm_buf_map.\n+ */\n+struct drm_buf_pub {\n+\tint idx;\t\t /**< Index into the master buffer list */\n+\tint total;\t\t /**< Buffer size */\n+\tint used;\t\t /**< Amount of buffer in use (for DMA) */\n+\tvoid *address;\t /**< Address of buffer */\n+};\n+\n+/**\n+ * DRM_IOCTL_MAP_BUFS ioctl argument type.\n+ */\n+struct drm_buf_map {\n+\tint count;\t\t/**< Length of the buffer list */\n+#ifdef __cplusplus\n+\tvoid *virt;\n+#else\n+\tvoid *virtual;\t\t/**< Mmap'd area in user-virtual */\n+#endif\n+\tstruct drm_buf_pub *list;\t/**< Buffer information */\n+};\n+\n+/**\n+ * DRM_IOCTL_DMA ioctl argument type.\n+ *\n+ * Indices here refer to the offset into the buffer list in drm_buf_get.\n+ *\n+ * \\sa drmDMA().\n+ */\n+struct drm_dma {\n+\tint context;\t\t\t /**< Context handle */\n+\tint send_count;\t\t\t /**< Number of buffers to send */\n+\tint *send_indices;\t /**< List of handles to buffers */\n+\tint *send_sizes;\t\t /**< Lengths of data to send */\n+\tenum drm_dma_flags flags;\t /**< Flags */\n+\tint request_count;\t\t /**< Number of buffers requested */\n+\tint request_size;\t\t /**< Desired size for buffers */\n+\tint *request_indices;\t /**< Buffer information */\n+\tint *request_sizes;\n+\tint granted_count;\t\t /**< Number of buffers granted */\n+};\n+\n+enum drm_ctx_flags {\n+\t_DRM_CONTEXT_PRESERVED = 0x01,\n+\t_DRM_CONTEXT_2DONLY = 0x02\n+};\n+\n+/**\n+ * DRM_IOCTL_ADD_CTX ioctl argument type.\n+ *\n+ * \\sa drmCreateContext() and drmDestroyContext().\n+ */\n+struct drm_ctx {\n+\tdrm_context_t handle;\n+\tenum drm_ctx_flags flags;\n+};\n+\n+/**\n+ * DRM_IOCTL_RES_CTX ioctl argument type.\n+ */\n+struct drm_ctx_res {\n+\tint count;\n+\tstruct drm_ctx *contexts;\n+};\n+\n+/**\n+ * DRM_IOCTL_ADD_DRAW and DRM_IOCTL_RM_DRAW ioctl argument type.\n+ */\n+struct drm_draw {\n+\tdrm_drawable_t handle;\n+};\n+\n+/**\n+ * DRM_IOCTL_UPDATE_DRAW ioctl argument type.\n+ */\n+typedef enum {\n+\tDRM_DRAWABLE_CLIPRECTS\n+} drm_drawable_info_type_t;\n+\n+struct drm_update_draw {\n+\tdrm_drawable_t handle;\n+\tunsigned int type;\n+\tunsigned int num;\n+\tunsigned long long data;\n+};\n+\n+/**\n+ * DRM_IOCTL_GET_MAGIC and DRM_IOCTL_AUTH_MAGIC ioctl argument type.\n+ */\n+struct drm_auth {\n+\tdrm_magic_t magic;\n+};\n+\n+/**\n+ * DRM_IOCTL_IRQ_BUSID ioctl argument type.\n+ *\n+ * \\sa drmGetInterruptFromBusID().\n+ */\n+struct drm_irq_busid {\n+\tint irq;\t/**< IRQ number */\n+\tint busnum;\t/**< bus number */\n+\tint devnum;\t/**< device number */\n+\tint funcnum;\t/**< function number */\n+};\n+\n+enum drm_vblank_seq_type {\n+\t_DRM_VBLANK_ABSOLUTE = 0x0,\t/**< Wait for specific vblank sequence number */\n+\t_DRM_VBLANK_RELATIVE = 0x1,\t/**< Wait for given number of vblanks */\n+\t/* bits 1-6 are reserved for high crtcs */\n+\t_DRM_VBLANK_HIGH_CRTC_MASK = 0x0000003e,\n+\t_DRM_VBLANK_EVENT = 0x4000000, /**< Send event instead of blocking */\n+\t_DRM_VBLANK_FLIP = 0x8000000, /**< Scheduled buffer swap should flip */\n+\t_DRM_VBLANK_NEXTONMISS = 0x10000000,\t/**< If missed, wait for next vblank */\n+\t_DRM_VBLANK_SECONDARY = 0x20000000,\t/**< Secondary display controller */\n+\t_DRM_VBLANK_SIGNAL = 0x40000000\t/**< Send signal instead of blocking, unsupported */\n+};\n+#define _DRM_VBLANK_HIGH_CRTC_SHIFT 1\n+\n+#define _DRM_VBLANK_TYPES_MASK (_DRM_VBLANK_ABSOLUTE | _DRM_VBLANK_RELATIVE)\n+#define _DRM_VBLANK_FLAGS_MASK (_DRM_VBLANK_EVENT | _DRM_VBLANK_SIGNAL | \\\n+\t\t\t\t_DRM_VBLANK_SECONDARY | _DRM_VBLANK_NEXTONMISS)\n+\n+struct drm_wait_vblank_request {\n+\tenum drm_vblank_seq_type type;\n+\tunsigned int sequence;\n+\tunsigned long signal;\n+};\n+\n+struct drm_wait_vblank_reply {\n+\tenum drm_vblank_seq_type type;\n+\tunsigned int sequence;\n+\tlong tval_sec;\n+\tlong tval_usec;\n+};\n+\n+/**\n+ * DRM_IOCTL_WAIT_VBLANK ioctl argument type.\n+ *\n+ * \\sa drmWaitVBlank().\n+ */\n+union drm_wait_vblank {\n+\tstruct drm_wait_vblank_request request;\n+\tstruct drm_wait_vblank_reply reply;\n+};\n+\n+#define _DRM_PRE_MODESET 1\n+#define _DRM_POST_MODESET 2\n+\n+/**\n+ * DRM_IOCTL_MODESET_CTL ioctl argument type\n+ *\n+ * \\sa drmModesetCtl().\n+ */\n+struct drm_modeset_ctl {\n+\t__u32 crtc;\n+\t__u32 cmd;\n+};\n+\n+/**\n+ * DRM_IOCTL_AGP_ENABLE ioctl argument type.\n+ *\n+ * \\sa drmAgpEnable().\n+ */\n+struct drm_agp_mode {\n+\tunsigned long mode;\t/**< AGP mode */\n+};\n+\n+/**\n+ * DRM_IOCTL_AGP_ALLOC and DRM_IOCTL_AGP_FREE ioctls argument type.\n+ *\n+ * \\sa drmAgpAlloc() and drmAgpFree().\n+ */\n+struct drm_agp_buffer {\n+\tunsigned long size;\t/**< In bytes -- will round to page boundary */\n+\tunsigned long handle;\t/**< Used for binding / unbinding */\n+\tunsigned long type;\t/**< Type of memory to allocate */\n+\tunsigned long physical;\t/**< Physical used by i810 */\n+};\n+\n+/**\n+ * DRM_IOCTL_AGP_BIND and DRM_IOCTL_AGP_UNBIND ioctls argument type.\n+ *\n+ * \\sa drmAgpBind() and drmAgpUnbind().\n+ */\n+struct drm_agp_binding {\n+\tunsigned long handle;\t/**< From drm_agp_buffer */\n+\tunsigned long offset;\t/**< In bytes -- will round to page boundary */\n+};\n+\n+/**\n+ * DRM_IOCTL_AGP_INFO ioctl argument type.\n+ *\n+ * \\sa drmAgpVersionMajor(), drmAgpVersionMinor(), drmAgpGetMode(),\n+ * drmAgpBase(), drmAgpSize(), drmAgpMemoryUsed(), drmAgpMemoryAvail(),\n+ * drmAgpVendorId() and drmAgpDeviceId().\n+ */\n+struct drm_agp_info {\n+\tint agp_version_major;\n+\tint agp_version_minor;\n+\tunsigned long mode;\n+\tunsigned long aperture_base;\t/* physical address */\n+\tunsigned long aperture_size;\t/* bytes */\n+\tunsigned long memory_allowed;\t/* bytes */\n+\tunsigned long memory_used;\n+\n+\t/* PCI information */\n+\tunsigned short id_vendor;\n+\tunsigned short id_device;\n+};\n+\n+/**\n+ * DRM_IOCTL_SG_ALLOC ioctl argument type.\n+ */\n+struct drm_scatter_gather {\n+\tunsigned long size;\t/**< In bytes -- will round to page boundary */\n+\tunsigned long handle;\t/**< Used for mapping / unmapping */\n+};\n+\n+/**\n+ * DRM_IOCTL_SET_VERSION ioctl argument type.\n+ */\n+struct drm_set_version {\n+\tint drm_di_major;\n+\tint drm_di_minor;\n+\tint drm_dd_major;\n+\tint drm_dd_minor;\n+};\n+\n+/** DRM_IOCTL_GEM_CLOSE ioctl argument type */\n+struct drm_gem_close {\n+\t/** Handle of the object to be closed. */\n+\t__u32 handle;\n+\t__u32 pad;\n+};\n+\n+/** DRM_IOCTL_GEM_FLINK ioctl argument type */\n+struct drm_gem_flink {\n+\t/** Handle for the object being named */\n+\t__u32 handle;\n+\n+\t/** Returned global name */\n+\t__u32 name;\n+};\n+\n+/** DRM_IOCTL_GEM_OPEN ioctl argument type */\n+struct drm_gem_open {\n+\t/** Name of object being opened */\n+\t__u32 name;\n+\n+\t/** Returned handle for the object */\n+\t__u32 handle;\n+\n+\t/** Returned size of the object */\n+\t__u64 size;\n+};\n+\n+#define DRM_CAP_DUMB_BUFFER\t\t0x1\n+#define DRM_CAP_VBLANK_HIGH_CRTC\t0x2\n+#define DRM_CAP_DUMB_PREFERRED_DEPTH\t0x3\n+#define DRM_CAP_DUMB_PREFER_SHADOW\t0x4\n+#define DRM_CAP_PRIME\t\t\t0x5\n+#define DRM_PRIME_CAP_IMPORT\t\t0x1\n+#define DRM_PRIME_CAP_EXPORT\t\t0x2\n+#define DRM_CAP_TIMESTAMP_MONOTONIC\t0x6\n+#define DRM_CAP_ASYNC_PAGE_FLIP\t\t0x7\n+/*\n+ * The CURSOR_WIDTH and CURSOR_HEIGHT capabilities return a valid widthxheight\n+ * combination for the hardware cursor. The intention is that a hardware\n+ * agnostic userspace can query a cursor plane size to use.\n+ *\n+ * Note that the cross-driver contract is to merely return a valid size;\n+ * drivers are free to attach another meaning on top, eg. i915 returns the\n+ * maximum plane size.\n+ */\n+#define DRM_CAP_CURSOR_WIDTH\t\t0x8\n+#define DRM_CAP_CURSOR_HEIGHT\t\t0x9\n+#define DRM_CAP_ADDFB2_MODIFIERS\t0x10\n+#define DRM_CAP_PAGE_FLIP_TARGET\t0x11\n+#define DRM_CAP_CRTC_IN_VBLANK_EVENT\t0x12\n+#define DRM_CAP_SYNCOBJ\t\t0x13\n+#define DRM_CAP_SYNCOBJ_TIMELINE\t0x14\n+\n+/** DRM_IOCTL_GET_CAP ioctl argument type */\n+struct drm_get_cap {\n+\t__u64 capability;\n+\t__u64 value;\n+};\n+\n+/**\n+ * DRM_CLIENT_CAP_STEREO_3D\n+ *\n+ * if set to 1, the DRM core will expose the stereo 3D capabilities of the\n+ * monitor by advertising the supported 3D layouts in the flags of struct\n+ * drm_mode_modeinfo.\n+ */\n+#define DRM_CLIENT_CAP_STEREO_3D\t1\n+\n+/**\n+ * DRM_CLIENT_CAP_UNIVERSAL_PLANES\n+ *\n+ * If set to 1, the DRM core will expose all planes (overlay, primary, and\n+ * cursor) to userspace.\n+ */\n+#define DRM_CLIENT_CAP_UNIVERSAL_PLANES 2\n+\n+/**\n+ * DRM_CLIENT_CAP_ATOMIC\n+ *\n+ * If set to 1, the DRM core will expose atomic properties to userspace\n+ */\n+#define DRM_CLIENT_CAP_ATOMIC\t3\n+\n+/**\n+ * DRM_CLIENT_CAP_ASPECT_RATIO\n+ *\n+ * If set to 1, the DRM core will provide aspect ratio information in modes.\n+ */\n+#define DRM_CLIENT_CAP_ASPECT_RATIO 4\n+\n+/**\n+ * DRM_CLIENT_CAP_WRITEBACK_CONNECTORS\n+ *\n+ * If set to 1, the DRM core will expose special connectors to be used for\n+ * writing back to memory the scene setup in the commit. Depends on client\n+ * also supporting DRM_CLIENT_CAP_ATOMIC\n+ */\n+#define DRM_CLIENT_CAP_WRITEBACK_CONNECTORS\t5\n+\n+/** DRM_IOCTL_SET_CLIENT_CAP ioctl argument type */\n+struct drm_set_client_cap {\n+\t__u64 capability;\n+\t__u64 value;\n+};\n+\n+#define DRM_RDWR O_RDWR\n+#define DRM_CLOEXEC O_CLOEXEC\n+struct drm_prime_handle {\n+\t__u32 handle;\n+\n+\t/** Flags.. only applicable for handle->fd */\n+\t__u32 flags;\n+\n+\t/** Returned dmabuf file descriptor */\n+\t__s32 fd;\n+};\n+\n+struct drm_syncobj_create {\n+\t__u32 handle;\n+#define DRM_SYNCOBJ_CREATE_SIGNALED (1 << 0)\n+\t__u32 flags;\n+};\n+\n+struct drm_syncobj_destroy {\n+\t__u32 handle;\n+\t__u32 pad;\n+};\n+\n+#define DRM_SYNCOBJ_FD_TO_HANDLE_FLAGS_IMPORT_SYNC_FILE (1 << 0)\n+#define DRM_SYNCOBJ_HANDLE_TO_FD_FLAGS_EXPORT_SYNC_FILE (1 << 0)\n+struct drm_syncobj_handle {\n+\t__u32 handle;\n+\t__u32 flags;\n+\n+\t__s32 fd;\n+\t__u32 pad;\n+};\n+\n+struct drm_syncobj_transfer {\n+\t__u32 src_handle;\n+\t__u32 dst_handle;\n+\t__u64 src_point;\n+\t__u64 dst_point;\n+\t__u32 flags;\n+\t__u32 pad;\n+};\n+\n+#define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL (1 << 0)\n+#define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT (1 << 1)\n+#define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_AVAILABLE (1 << 2) /* wait for time point to become available */\n+struct drm_syncobj_wait {\n+\t__u64 handles;\n+\t/* absolute timeout */\n+\t__s64 timeout_nsec;\n+\t__u32 count_handles;\n+\t__u32 flags;\n+\t__u32 first_signaled; /* only valid when not waiting all */\n+\t__u32 pad;\n+};\n+\n+struct drm_syncobj_timeline_wait {\n+\t__u64 handles;\n+\t/* wait on specific timeline point for every handles*/\n+\t__u64 points;\n+\t/* absolute timeout */\n+\t__s64 timeout_nsec;\n+\t__u32 count_handles;\n+\t__u32 flags;\n+\t__u32 first_signaled; /* only valid when not waiting all */\n+\t__u32 pad;\n+};\n+\n+\n+struct drm_syncobj_array {\n+\t__u64 handles;\n+\t__u32 count_handles;\n+\t__u32 pad;\n+};\n+\n+struct drm_syncobj_timeline_array {\n+\t__u64 handles;\n+\t__u64 points;\n+\t__u32 count_handles;\n+\t__u32 pad;\n+};\n+\n+\n+/* Query current scanout sequence number */\n+struct drm_crtc_get_sequence {\n+\t__u32 crtc_id;\t\t/* requested crtc_id */\n+\t__u32 active;\t\t/* return: crtc output is active */\n+\t__u64 sequence;\t\t/* return: most recent vblank sequence */\n+\t__s64 sequence_ns;\t/* return: most recent time of first pixel out */\n+};\n+\n+/* Queue event to be delivered at specified sequence. Time stamp marks\n+ * when the first pixel of the refresh cycle leaves the display engine\n+ * for the display\n+ */\n+#define DRM_CRTC_SEQUENCE_RELATIVE\t\t0x00000001\t/* sequence is relative to current */\n+#define DRM_CRTC_SEQUENCE_NEXT_ON_MISS\t\t0x00000002\t/* Use next sequence if we've missed */\n+\n+struct drm_crtc_queue_sequence {\n+\t__u32 crtc_id;\n+\t__u32 flags;\n+\t__u64 sequence;\t\t/* on input, target sequence. on output, actual sequence */\n+\t__u64 user_data;\t/* user data passed to event */\n+};\n+\n+#if defined(__cplusplus)\n+}\n+#endif\n+\n+#include \"drm_mode.h\"\n+\n+#if defined(__cplusplus)\n+extern \"C\" {\n+#endif\n+\n+#define DRM_IOCTL_BASE\t\t\t'd'\n+#define DRM_IO(nr)\t\t\t_IO(DRM_IOCTL_BASE,nr)\n+#define DRM_IOR(nr,type)\t\t_IOR(DRM_IOCTL_BASE,nr,type)\n+#define DRM_IOW(nr,type)\t\t_IOW(DRM_IOCTL_BASE,nr,type)\n+#define DRM_IOWR(nr,type)\t\t_IOWR(DRM_IOCTL_BASE,nr,type)\n+\n+#define DRM_IOCTL_VERSION\t\tDRM_IOWR(0x00, struct drm_version)\n+#define DRM_IOCTL_GET_UNIQUE\t\tDRM_IOWR(0x01, struct drm_unique)\n+#define DRM_IOCTL_GET_MAGIC\t\tDRM_IOR( 0x02, struct drm_auth)\n+#define DRM_IOCTL_IRQ_BUSID\t\tDRM_IOWR(0x03, struct drm_irq_busid)\n+#define DRM_IOCTL_GET_MAP DRM_IOWR(0x04, struct drm_map)\n+#define DRM_IOCTL_GET_CLIENT DRM_IOWR(0x05, struct drm_client)\n+#define DRM_IOCTL_GET_STATS DRM_IOR( 0x06, struct drm_stats)\n+#define DRM_IOCTL_SET_VERSION\t\tDRM_IOWR(0x07, struct drm_set_version)\n+#define DRM_IOCTL_MODESET_CTL DRM_IOW(0x08, struct drm_modeset_ctl)\n+#define DRM_IOCTL_GEM_CLOSE\t\tDRM_IOW (0x09, struct drm_gem_close)\n+#define DRM_IOCTL_GEM_FLINK\t\tDRM_IOWR(0x0a, struct drm_gem_flink)\n+#define DRM_IOCTL_GEM_OPEN\t\tDRM_IOWR(0x0b, struct drm_gem_open)\n+#define DRM_IOCTL_GET_CAP\t\tDRM_IOWR(0x0c, struct drm_get_cap)\n+#define DRM_IOCTL_SET_CLIENT_CAP\tDRM_IOW( 0x0d, struct drm_set_client_cap)\n+\n+#define DRM_IOCTL_SET_UNIQUE\t\tDRM_IOW( 0x10, struct drm_unique)\n+#define DRM_IOCTL_AUTH_MAGIC\t\tDRM_IOW( 0x11, struct drm_auth)\n+#define DRM_IOCTL_BLOCK\t\t\tDRM_IOWR(0x12, struct drm_block)\n+#define DRM_IOCTL_UNBLOCK\t\tDRM_IOWR(0x13, struct drm_block)\n+#define DRM_IOCTL_CONTROL\t\tDRM_IOW( 0x14, struct drm_control)\n+#define DRM_IOCTL_ADD_MAP\t\tDRM_IOWR(0x15, struct drm_map)\n+#define DRM_IOCTL_ADD_BUFS\t\tDRM_IOWR(0x16, struct drm_buf_desc)\n+#define DRM_IOCTL_MARK_BUFS\t\tDRM_IOW( 0x17, struct drm_buf_desc)\n+#define DRM_IOCTL_INFO_BUFS\t\tDRM_IOWR(0x18, struct drm_buf_info)\n+#define DRM_IOCTL_MAP_BUFS\t\tDRM_IOWR(0x19, struct drm_buf_map)\n+#define DRM_IOCTL_FREE_BUFS\t\tDRM_IOW( 0x1a, struct drm_buf_free)\n+\n+#define DRM_IOCTL_RM_MAP\t\tDRM_IOW( 0x1b, struct drm_map)\n+\n+#define DRM_IOCTL_SET_SAREA_CTX\t\tDRM_IOW( 0x1c, struct drm_ctx_priv_map)\n+#define DRM_IOCTL_GET_SAREA_CTX \tDRM_IOWR(0x1d, struct drm_ctx_priv_map)\n+\n+#define DRM_IOCTL_SET_MASTER DRM_IO(0x1e)\n+#define DRM_IOCTL_DROP_MASTER DRM_IO(0x1f)\n+\n+#define DRM_IOCTL_ADD_CTX\t\tDRM_IOWR(0x20, struct drm_ctx)\n+#define DRM_IOCTL_RM_CTX\t\tDRM_IOWR(0x21, struct drm_ctx)\n+#define DRM_IOCTL_MOD_CTX\t\tDRM_IOW( 0x22, struct drm_ctx)\n+#define DRM_IOCTL_GET_CTX\t\tDRM_IOWR(0x23, struct drm_ctx)\n+#define DRM_IOCTL_SWITCH_CTX\t\tDRM_IOW( 0x24, struct drm_ctx)\n+#define DRM_IOCTL_NEW_CTX\t\tDRM_IOW( 0x25, struct drm_ctx)\n+#define DRM_IOCTL_RES_CTX\t\tDRM_IOWR(0x26, struct drm_ctx_res)\n+#define DRM_IOCTL_ADD_DRAW\t\tDRM_IOWR(0x27, struct drm_draw)\n+#define DRM_IOCTL_RM_DRAW\t\tDRM_IOWR(0x28, struct drm_draw)\n+#define DRM_IOCTL_DMA\t\t\tDRM_IOWR(0x29, struct drm_dma)\n+#define DRM_IOCTL_LOCK\t\t\tDRM_IOW( 0x2a, struct drm_lock)\n+#define DRM_IOCTL_UNLOCK\t\tDRM_IOW( 0x2b, struct drm_lock)\n+#define DRM_IOCTL_FINISH\t\tDRM_IOW( 0x2c, struct drm_lock)\n+\n+#define DRM_IOCTL_PRIME_HANDLE_TO_FD DRM_IOWR(0x2d, struct drm_prime_handle)\n+#define DRM_IOCTL_PRIME_FD_TO_HANDLE DRM_IOWR(0x2e, struct drm_prime_handle)\n+\n+#define DRM_IOCTL_AGP_ACQUIRE\t\tDRM_IO( 0x30)\n+#define DRM_IOCTL_AGP_RELEASE\t\tDRM_IO( 0x31)\n+#define DRM_IOCTL_AGP_ENABLE\t\tDRM_IOW( 0x32, struct drm_agp_mode)\n+#define DRM_IOCTL_AGP_INFO\t\tDRM_IOR( 0x33, struct drm_agp_info)\n+#define DRM_IOCTL_AGP_ALLOC\t\tDRM_IOWR(0x34, struct drm_agp_buffer)\n+#define DRM_IOCTL_AGP_FREE\t\tDRM_IOW( 0x35, struct drm_agp_buffer)\n+#define DRM_IOCTL_AGP_BIND\t\tDRM_IOW( 0x36, struct drm_agp_binding)\n+#define DRM_IOCTL_AGP_UNBIND\t\tDRM_IOW( 0x37, struct drm_agp_binding)\n+\n+#define DRM_IOCTL_SG_ALLOC\t\tDRM_IOWR(0x38, struct drm_scatter_gather)\n+#define DRM_IOCTL_SG_FREE\t\tDRM_IOW( 0x39, struct drm_scatter_gather)\n+\n+#define DRM_IOCTL_WAIT_VBLANK\t\tDRM_IOWR(0x3a, union drm_wait_vblank)\n+\n+#define DRM_IOCTL_CRTC_GET_SEQUENCE\tDRM_IOWR(0x3b, struct drm_crtc_get_sequence)\n+#define DRM_IOCTL_CRTC_QUEUE_SEQUENCE\tDRM_IOWR(0x3c, struct drm_crtc_queue_sequence)\n+\n+#define DRM_IOCTL_UPDATE_DRAW\t\tDRM_IOW(0x3f, struct drm_update_draw)\n+\n+#define DRM_IOCTL_MODE_GETRESOURCES\tDRM_IOWR(0xA0, struct drm_mode_card_res)\n+#define DRM_IOCTL_MODE_GETCRTC\t\tDRM_IOWR(0xA1, struct drm_mode_crtc)\n+#define DRM_IOCTL_MODE_SETCRTC\t\tDRM_IOWR(0xA2, struct drm_mode_crtc)\n+#define DRM_IOCTL_MODE_CURSOR\t\tDRM_IOWR(0xA3, struct drm_mode_cursor)\n+#define DRM_IOCTL_MODE_GETGAMMA\t\tDRM_IOWR(0xA4, struct drm_mode_crtc_lut)\n+#define DRM_IOCTL_MODE_SETGAMMA\t\tDRM_IOWR(0xA5, struct drm_mode_crtc_lut)\n+#define DRM_IOCTL_MODE_GETENCODER\tDRM_IOWR(0xA6, struct drm_mode_get_encoder)\n+#define DRM_IOCTL_MODE_GETCONNECTOR\tDRM_IOWR(0xA7, struct drm_mode_get_connector)\n+#define DRM_IOCTL_MODE_ATTACHMODE\tDRM_IOWR(0xA8, struct drm_mode_mode_cmd) /* deprecated (never worked) */\n+#define DRM_IOCTL_MODE_DETACHMODE\tDRM_IOWR(0xA9, struct drm_mode_mode_cmd) /* deprecated (never worked) */\n+\n+#define DRM_IOCTL_MODE_GETPROPERTY\tDRM_IOWR(0xAA, struct drm_mode_get_property)\n+#define DRM_IOCTL_MODE_SETPROPERTY\tDRM_IOWR(0xAB, struct drm_mode_connector_set_property)\n+#define DRM_IOCTL_MODE_GETPROPBLOB\tDRM_IOWR(0xAC, struct drm_mode_get_blob)\n+#define DRM_IOCTL_MODE_GETFB\t\tDRM_IOWR(0xAD, struct drm_mode_fb_cmd)\n+#define DRM_IOCTL_MODE_ADDFB\t\tDRM_IOWR(0xAE, struct drm_mode_fb_cmd)\n+#define DRM_IOCTL_MODE_RMFB\t\tDRM_IOWR(0xAF, unsigned int)\n+#define DRM_IOCTL_MODE_PAGE_FLIP\tDRM_IOWR(0xB0, struct drm_mode_crtc_page_flip)\n+#define DRM_IOCTL_MODE_DIRTYFB\t\tDRM_IOWR(0xB1, struct drm_mode_fb_dirty_cmd)\n+\n+#define DRM_IOCTL_MODE_CREATE_DUMB DRM_IOWR(0xB2, struct drm_mode_create_dumb)\n+#define DRM_IOCTL_MODE_MAP_DUMB DRM_IOWR(0xB3, struct drm_mode_map_dumb)\n+#define DRM_IOCTL_MODE_DESTROY_DUMB DRM_IOWR(0xB4, struct drm_mode_destroy_dumb)\n+#define DRM_IOCTL_MODE_GETPLANERESOURCES DRM_IOWR(0xB5, struct drm_mode_get_plane_res)\n+#define DRM_IOCTL_MODE_GETPLANE\tDRM_IOWR(0xB6, struct drm_mode_get_plane)\n+#define DRM_IOCTL_MODE_SETPLANE\tDRM_IOWR(0xB7, struct drm_mode_set_plane)\n+#define DRM_IOCTL_MODE_ADDFB2\t\tDRM_IOWR(0xB8, struct drm_mode_fb_cmd2)\n+#define DRM_IOCTL_MODE_OBJ_GETPROPERTIES\tDRM_IOWR(0xB9, struct drm_mode_obj_get_properties)\n+#define DRM_IOCTL_MODE_OBJ_SETPROPERTY\tDRM_IOWR(0xBA, struct drm_mode_obj_set_property)\n+#define DRM_IOCTL_MODE_CURSOR2\t\tDRM_IOWR(0xBB, struct drm_mode_cursor2)\n+#define DRM_IOCTL_MODE_ATOMIC\t\tDRM_IOWR(0xBC, struct drm_mode_atomic)\n+#define DRM_IOCTL_MODE_CREATEPROPBLOB\tDRM_IOWR(0xBD, struct drm_mode_create_blob)\n+#define DRM_IOCTL_MODE_DESTROYPROPBLOB\tDRM_IOWR(0xBE, struct drm_mode_destroy_blob)\n+\n+#define DRM_IOCTL_SYNCOBJ_CREATE\tDRM_IOWR(0xBF, struct drm_syncobj_create)\n+#define DRM_IOCTL_SYNCOBJ_DESTROY\tDRM_IOWR(0xC0, struct drm_syncobj_destroy)\n+#define DRM_IOCTL_SYNCOBJ_HANDLE_TO_FD\tDRM_IOWR(0xC1, struct drm_syncobj_handle)\n+#define DRM_IOCTL_SYNCOBJ_FD_TO_HANDLE\tDRM_IOWR(0xC2, struct drm_syncobj_handle)\n+#define DRM_IOCTL_SYNCOBJ_WAIT\t\tDRM_IOWR(0xC3, struct drm_syncobj_wait)\n+#define DRM_IOCTL_SYNCOBJ_RESET\t\tDRM_IOWR(0xC4, struct drm_syncobj_array)\n+#define DRM_IOCTL_SYNCOBJ_SIGNAL\tDRM_IOWR(0xC5, struct drm_syncobj_array)\n+\n+#define DRM_IOCTL_MODE_CREATE_LEASE\tDRM_IOWR(0xC6, struct drm_mode_create_lease)\n+#define DRM_IOCTL_MODE_LIST_LESSEES\tDRM_IOWR(0xC7, struct drm_mode_list_lessees)\n+#define DRM_IOCTL_MODE_GET_LEASE\tDRM_IOWR(0xC8, struct drm_mode_get_lease)\n+#define DRM_IOCTL_MODE_REVOKE_LEASE\tDRM_IOWR(0xC9, struct drm_mode_revoke_lease)\n+\n+#define DRM_IOCTL_SYNCOBJ_TIMELINE_WAIT\tDRM_IOWR(0xCA, struct drm_syncobj_timeline_wait)\n+#define DRM_IOCTL_SYNCOBJ_QUERY\t\tDRM_IOWR(0xCB, struct drm_syncobj_timeline_array)\n+#define DRM_IOCTL_SYNCOBJ_TRANSFER\tDRM_IOWR(0xCC, struct drm_syncobj_transfer)\n+#define DRM_IOCTL_SYNCOBJ_TIMELINE_SIGNAL\tDRM_IOWR(0xCD, struct drm_syncobj_timeline_array)\n+\n+/**\n+ * Device specific ioctls should only be in their respective headers\n+ * The device specific ioctl range is from 0x40 to 0x9f.\n+ * Generic IOCTLS restart at 0xA0.\n+ *\n+ * \\sa drmCommandNone(), drmCommandRead(), drmCommandWrite(), and\n+ * drmCommandReadWrite().\n+ */\n+#define DRM_COMMAND_BASE 0x40\n+#define DRM_COMMAND_END\t\t\t0xA0\n+\n+/**\n+ * Header for events written back to userspace on the drm fd. The\n+ * type defines the type of event, the length specifies the total\n+ * length of the event (including the header), and user_data is\n+ * typically a 64 bit value passed with the ioctl that triggered the\n+ * event. A read on the drm fd will always only return complete\n+ * events, that is, if for example the read buffer is 100 bytes, and\n+ * there are two 64 byte events pending, only one will be returned.\n+ *\n+ * Event types 0 - 0x7fffffff are generic drm events, 0x80000000 and\n+ * up are chipset specific.\n+ */\n+struct drm_event {\n+\t__u32 type;\n+\t__u32 length;\n+};\n+\n+#define DRM_EVENT_VBLANK 0x01\n+#define DRM_EVENT_FLIP_COMPLETE 0x02\n+#define DRM_EVENT_CRTC_SEQUENCE\t0x03\n+\n+struct drm_event_vblank {\n+\tstruct drm_event base;\n+\t__u64 user_data;\n+\t__u32 tv_sec;\n+\t__u32 tv_usec;\n+\t__u32 sequence;\n+\t__u32 crtc_id; /* 0 on older kernels that do not support this */\n+};\n+\n+/* Event delivered at sequence. Time stamp marks when the first pixel\n+ * of the refresh cycle leaves the display engine for the display\n+ */\n+struct drm_event_crtc_sequence {\n+\tstruct drm_event\tbase;\n+\t__u64\t\t\tuser_data;\n+\t__s64\t\t\ttime_ns;\n+\t__u64\t\t\tsequence;\n+};\n+\n+/* typedef area */\n+typedef struct drm_clip_rect drm_clip_rect_t;\n+typedef struct drm_drawable_info drm_drawable_info_t;\n+typedef struct drm_tex_region drm_tex_region_t;\n+typedef struct drm_hw_lock drm_hw_lock_t;\n+typedef struct drm_version drm_version_t;\n+typedef struct drm_unique drm_unique_t;\n+typedef struct drm_list drm_list_t;\n+typedef struct drm_block drm_block_t;\n+typedef struct drm_control drm_control_t;\n+typedef enum drm_map_type drm_map_type_t;\n+typedef enum drm_map_flags drm_map_flags_t;\n+typedef struct drm_ctx_priv_map drm_ctx_priv_map_t;\n+typedef struct drm_map drm_map_t;\n+typedef struct drm_client drm_client_t;\n+typedef enum drm_stat_type drm_stat_type_t;\n+typedef struct drm_stats drm_stats_t;\n+typedef enum drm_lock_flags drm_lock_flags_t;\n+typedef struct drm_lock drm_lock_t;\n+typedef enum drm_dma_flags drm_dma_flags_t;\n+typedef struct drm_buf_desc drm_buf_desc_t;\n+typedef struct drm_buf_info drm_buf_info_t;\n+typedef struct drm_buf_free drm_buf_free_t;\n+typedef struct drm_buf_pub drm_buf_pub_t;\n+typedef struct drm_buf_map drm_buf_map_t;\n+typedef struct drm_dma drm_dma_t;\n+typedef union drm_wait_vblank drm_wait_vblank_t;\n+typedef struct drm_agp_mode drm_agp_mode_t;\n+typedef enum drm_ctx_flags drm_ctx_flags_t;\n+typedef struct drm_ctx drm_ctx_t;\n+typedef struct drm_ctx_res drm_ctx_res_t;\n+typedef struct drm_draw drm_draw_t;\n+typedef struct drm_update_draw drm_update_draw_t;\n+typedef struct drm_auth drm_auth_t;\n+typedef struct drm_irq_busid drm_irq_busid_t;\n+typedef enum drm_vblank_seq_type drm_vblank_seq_type_t;\n+\n+typedef struct drm_agp_buffer drm_agp_buffer_t;\n+typedef struct drm_agp_binding drm_agp_binding_t;\n+typedef struct drm_agp_info drm_agp_info_t;\n+typedef struct drm_scatter_gather drm_scatter_gather_t;\n+typedef struct drm_set_version drm_set_version_t;\n+\n+#if defined(__cplusplus)\n+}\n+#endif\n+\n+#endif\ndiff --git a/include/linux/drm_fourcc.h b/include/linux/drm_fourcc.h\nnew file mode 100644\nindex 000000000000..3feeaa3f987a\n--- /dev/null\n+++ b/include/linux/drm_fourcc.h\n@@ -0,0 +1,763 @@\n+/*\n+ * Copyright 2011 Intel Corporation\n+ *\n+ * Permission is hereby granted, free of charge, to any person obtaining a\n+ * copy of this software and associated documentation files (the \"Software\"),\n+ * to deal in the Software without restriction, including without limitation\n+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n+ * and/or sell copies of the Software, and to permit persons to whom the\n+ * Software is furnished to do so, subject to the following conditions:\n+ *\n+ * The above copyright notice and this permission notice (including the next\n+ * paragraph) shall be included in all copies or substantial portions of the\n+ * Software.\n+ *\n+ * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n+ * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR\n+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,\n+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n+ * OTHER DEALINGS IN THE SOFTWARE.\n+ */\n+\n+#ifndef DRM_FOURCC_H\n+#define DRM_FOURCC_H\n+\n+#include \"drm.h\"\n+\n+#if defined(__cplusplus)\n+extern \"C\" {\n+#endif\n+\n+/**\n+ * DOC: overview\n+ *\n+ * In the DRM subsystem, framebuffer pixel formats are described using the\n+ * fourcc codes defined in `include/uapi/drm/drm_fourcc.h`. In addition to the\n+ * fourcc code, a Format Modifier may optionally be provided, in order to\n+ * further describe the buffer's format - for example tiling or compression.\n+ *\n+ * Format Modifiers\n+ * ----------------\n+ *\n+ * Format modifiers are used in conjunction with a fourcc code, forming a\n+ * unique fourcc:modifier pair. This format:modifier pair must fully define the\n+ * format and data layout of the buffer, and should be the only way to describe\n+ * that particular buffer.\n+ *\n+ * Having multiple fourcc:modifier pairs which describe the same layout should\n+ * be avoided, as such aliases run the risk of different drivers exposing\n+ * different names for the same data format, forcing userspace to understand\n+ * that they are aliases.\n+ *\n+ * Format modifiers may change any property of the buffer, including the number\n+ * of planes and/or the required allocation size. Format modifiers are\n+ * vendor-namespaced, and as such the relationship between a fourcc code and a\n+ * modifier is specific to the modifer being used. For example, some modifiers\n+ * may preserve meaning - such as number of planes - from the fourcc code,\n+ * whereas others may not.\n+ *\n+ * Vendors should document their modifier usage in as much detail as\n+ * possible, to ensure maximum compatibility across devices, drivers and\n+ * applications.\n+ *\n+ * The authoritative list of format modifier codes is found in\n+ * `include/uapi/drm/drm_fourcc.h`\n+ */\n+\n+#define fourcc_code(a, b, c, d) ((__u32)(a) | ((__u32)(b) << 8) | \\\n+\t\t\t\t ((__u32)(c) << 16) | ((__u32)(d) << 24))\n+\n+#define DRM_FORMAT_BIG_ENDIAN (1<<31) /* format is big endian instead of little endian */\n+\n+/* Reserve 0 for the invalid format specifier */\n+#define DRM_FORMAT_INVALID\t0\n+\n+/* color index */\n+#define DRM_FORMAT_C8\t\tfourcc_code('C', '8', ' ', ' ') /* [7:0] C */\n+\n+/* 8 bpp Red */\n+#define DRM_FORMAT_R8\t\tfourcc_code('R', '8', ' ', ' ') /* [7:0] R */\n+\n+/* 16 bpp Red */\n+#define DRM_FORMAT_R16\t\tfourcc_code('R', '1', '6', ' ') /* [15:0] R little endian */\n+\n+/* 16 bpp RG */\n+#define DRM_FORMAT_RG88\t\tfourcc_code('R', 'G', '8', '8') /* [15:0] R:G 8:8 little endian */\n+#define DRM_FORMAT_GR88\t\tfourcc_code('G', 'R', '8', '8') /* [15:0] G:R 8:8 little endian */\n+\n+/* 32 bpp RG */\n+#define DRM_FORMAT_RG1616\tfourcc_code('R', 'G', '3', '2') /* [31:0] R:G 16:16 little endian */\n+#define DRM_FORMAT_GR1616\tfourcc_code('G', 'R', '3', '2') /* [31:0] G:R 16:16 little endian */\n+\n+/* 8 bpp RGB */\n+#define DRM_FORMAT_RGB332\tfourcc_code('R', 'G', 'B', '8') /* [7:0] R:G:B 3:3:2 */\n+#define DRM_FORMAT_BGR233\tfourcc_code('B', 'G', 'R', '8') /* [7:0] B:G:R 2:3:3 */\n+\n+/* 16 bpp RGB */\n+#define DRM_FORMAT_XRGB4444\tfourcc_code('X', 'R', '1', '2') /* [15:0] x:R:G:B 4:4:4:4 little endian */\n+#define DRM_FORMAT_XBGR4444\tfourcc_code('X', 'B', '1', '2') /* [15:0] x:B:G:R 4:4:4:4 little endian */\n+#define DRM_FORMAT_RGBX4444\tfourcc_code('R', 'X', '1', '2') /* [15:0] R:G:B:x 4:4:4:4 little endian */\n+#define DRM_FORMAT_BGRX4444\tfourcc_code('B', 'X', '1', '2') /* [15:0] B:G:R:x 4:4:4:4 little endian */\n+\n+#define DRM_FORMAT_ARGB4444\tfourcc_code('A', 'R', '1', '2') /* [15:0] A:R:G:B 4:4:4:4 little endian */\n+#define DRM_FORMAT_ABGR4444\tfourcc_code('A', 'B', '1', '2') /* [15:0] A:B:G:R 4:4:4:4 little endian */\n+#define DRM_FORMAT_RGBA4444\tfourcc_code('R', 'A', '1', '2') /* [15:0] R:G:B:A 4:4:4:4 little endian */\n+#define DRM_FORMAT_BGRA4444\tfourcc_code('B', 'A', '1', '2') /* [15:0] B:G:R:A 4:4:4:4 little endian */\n+\n+#define DRM_FORMAT_XRGB1555\tfourcc_code('X', 'R', '1', '5') /* [15:0] x:R:G:B 1:5:5:5 little endian */\n+#define DRM_FORMAT_XBGR1555\tfourcc_code('X', 'B', '1', '5') /* [15:0] x:B:G:R 1:5:5:5 little endian */\n+#define DRM_FORMAT_RGBX5551\tfourcc_code('R', 'X', '1', '5') /* [15:0] R:G:B:x 5:5:5:1 little endian */\n+#define DRM_FORMAT_BGRX5551\tfourcc_code('B', 'X', '1', '5') /* [15:0] B:G:R:x 5:5:5:1 little endian */\n+\n+#define DRM_FORMAT_ARGB1555\tfourcc_code('A', 'R', '1', '5') /* [15:0] A:R:G:B 1:5:5:5 little endian */\n+#define DRM_FORMAT_ABGR1555\tfourcc_code('A', 'B', '1', '5') /* [15:0] A:B:G:R 1:5:5:5 little endian */\n+#define DRM_FORMAT_RGBA5551\tfourcc_code('R', 'A', '1', '5') /* [15:0] R:G:B:A 5:5:5:1 little endian */\n+#define DRM_FORMAT_BGRA5551\tfourcc_code('B', 'A', '1', '5') /* [15:0] B:G:R:A 5:5:5:1 little endian */\n+\n+#define DRM_FORMAT_RGB565\tfourcc_code('R', 'G', '1', '6') /* [15:0] R:G:B 5:6:5 little endian */\n+#define DRM_FORMAT_BGR565\tfourcc_code('B', 'G', '1', '6') /* [15:0] B:G:R 5:6:5 little endian */\n+\n+/* 24 bpp RGB */\n+#define DRM_FORMAT_RGB888\tfourcc_code('R', 'G', '2', '4') /* [23:0] R:G:B little endian */\n+#define DRM_FORMAT_BGR888\tfourcc_code('B', 'G', '2', '4') /* [23:0] B:G:R little endian */\n+\n+/* 32 bpp RGB */\n+#define DRM_FORMAT_XRGB8888\tfourcc_code('X', 'R', '2', '4') /* [31:0] x:R:G:B 8:8:8:8 little endian */\n+#define DRM_FORMAT_XBGR8888\tfourcc_code('X', 'B', '2', '4') /* [31:0] x:B:G:R 8:8:8:8 little endian */\n+#define DRM_FORMAT_RGBX8888\tfourcc_code('R', 'X', '2', '4') /* [31:0] R:G:B:x 8:8:8:8 little endian */\n+#define DRM_FORMAT_BGRX8888\tfourcc_code('B', 'X', '2', '4') /* [31:0] B:G:R:x 8:8:8:8 little endian */\n+\n+#define DRM_FORMAT_ARGB8888\tfourcc_code('A', 'R', '2', '4') /* [31:0] A:R:G:B 8:8:8:8 little endian */\n+#define DRM_FORMAT_ABGR8888\tfourcc_code('A', 'B', '2', '4') /* [31:0] A:B:G:R 8:8:8:8 little endian */\n+#define DRM_FORMAT_RGBA8888\tfourcc_code('R', 'A', '2', '4') /* [31:0] R:G:B:A 8:8:8:8 little endian */\n+#define DRM_FORMAT_BGRA8888\tfourcc_code('B', 'A', '2', '4') /* [31:0] B:G:R:A 8:8:8:8 little endian */\n+\n+#define DRM_FORMAT_XRGB2101010\tfourcc_code('X', 'R', '3', '0') /* [31:0] x:R:G:B 2:10:10:10 little endian */\n+#define DRM_FORMAT_XBGR2101010\tfourcc_code('X', 'B', '3', '0') /* [31:0] x:B:G:R 2:10:10:10 little endian */\n+#define DRM_FORMAT_RGBX1010102\tfourcc_code('R', 'X', '3', '0') /* [31:0] R:G:B:x 10:10:10:2 little endian */\n+#define DRM_FORMAT_BGRX1010102\tfourcc_code('B', 'X', '3', '0') /* [31:0] B:G:R:x 10:10:10:2 little endian */\n+\n+#define DRM_FORMAT_ARGB2101010\tfourcc_code('A', 'R', '3', '0') /* [31:0] A:R:G:B 2:10:10:10 little endian */\n+#define DRM_FORMAT_ABGR2101010\tfourcc_code('A', 'B', '3', '0') /* [31:0] A:B:G:R 2:10:10:10 little endian */\n+#define DRM_FORMAT_RGBA1010102\tfourcc_code('R', 'A', '3', '0') /* [31:0] R:G:B:A 10:10:10:2 little endian */\n+#define DRM_FORMAT_BGRA1010102\tfourcc_code('B', 'A', '3', '0') /* [31:0] B:G:R:A 10:10:10:2 little endian */\n+\n+/*\n+ * Floating point 64bpp RGB\n+ * IEEE 754-2008 binary16 half-precision float\n+ * [15:0] sign:exponent:mantissa 1:5:10\n+ */\n+#define DRM_FORMAT_XRGB16161616F fourcc_code('X', 'R', '4', 'H') /* [63:0] x:R:G:B 16:16:16:16 little endian */\n+#define DRM_FORMAT_XBGR16161616F fourcc_code('X', 'B', '4', 'H') /* [63:0] x:B:G:R 16:16:16:16 little endian */\n+\n+#define DRM_FORMAT_ARGB16161616F fourcc_code('A', 'R', '4', 'H') /* [63:0] A:R:G:B 16:16:16:16 little endian */\n+#define DRM_FORMAT_ABGR16161616F fourcc_code('A', 'B', '4', 'H') /* [63:0] A:B:G:R 16:16:16:16 little endian */\n+\n+/* packed YCbCr */\n+#define DRM_FORMAT_YUYV\t\tfourcc_code('Y', 'U', 'Y', 'V') /* [31:0] Cr0:Y1:Cb0:Y0 8:8:8:8 little endian */\n+#define DRM_FORMAT_YVYU\t\tfourcc_code('Y', 'V', 'Y', 'U') /* [31:0] Cb0:Y1:Cr0:Y0 8:8:8:8 little endian */\n+#define DRM_FORMAT_UYVY\t\tfourcc_code('U', 'Y', 'V', 'Y') /* [31:0] Y1:Cr0:Y0:Cb0 8:8:8:8 little endian */\n+#define DRM_FORMAT_VYUY\t\tfourcc_code('V', 'Y', 'U', 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */\n+\n+#define DRM_FORMAT_AYUV\t\tfourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */\n+#define DRM_FORMAT_XYUV8888\tfourcc_code('X', 'Y', 'U', 'V') /* [31:0] X:Y:Cb:Cr 8:8:8:8 little endian */\n+#define DRM_FORMAT_VUY888\tfourcc_code('V', 'U', '2', '4') /* [23:0] Cr:Cb:Y 8:8:8 little endian */\n+#define DRM_FORMAT_VUY101010\tfourcc_code('V', 'U', '3', '0') /* Y followed by U then V, 10:10:10. Non-linear modifier only */\n+\n+/*\n+ * packed Y2xx indicate for each component, xx valid data occupy msb\n+ * 16-xx padding occupy lsb\n+ */\n+#define DRM_FORMAT_Y210 fourcc_code('Y', '2', '1', '0') /* [63:0] Cr0:0:Y1:0:Cb0:0:Y0:0 10:6:10:6:10:6:10:6 little endian per 2 Y pixels */\n+#define DRM_FORMAT_Y212 fourcc_code('Y', '2', '1', '2') /* [63:0] Cr0:0:Y1:0:Cb0:0:Y0:0 12:4:12:4:12:4:12:4 little endian per 2 Y pixels */\n+#define DRM_FORMAT_Y216 fourcc_code('Y', '2', '1', '6') /* [63:0] Cr0:Y1:Cb0:Y0 16:16:16:16 little endian per 2 Y pixels */\n+\n+/*\n+ * packed Y4xx indicate for each component, xx valid data occupy msb\n+ * 16-xx padding occupy lsb except Y410\n+ */\n+#define DRM_FORMAT_Y410 fourcc_code('Y', '4', '1', '0') /* [31:0] A:Cr:Y:Cb 2:10:10:10 little endian */\n+#define DRM_FORMAT_Y412 fourcc_code('Y', '4', '1', '2') /* [63:0] A:0:Cr:0:Y:0:Cb:0 12:4:12:4:12:4:12:4 little endian */\n+#define DRM_FORMAT_Y416 fourcc_code('Y', '4', '1', '6') /* [63:0] A:Cr:Y:Cb 16:16:16:16 little endian */\n+\n+#define DRM_FORMAT_XVYU2101010\tfourcc_code('X', 'V', '3', '0') /* [31:0] X:Cr:Y:Cb 2:10:10:10 little endian */\n+#define DRM_FORMAT_XVYU12_16161616\tfourcc_code('X', 'V', '3', '6') /* [63:0] X:0:Cr:0:Y:0:Cb:0 12:4:12:4:12:4:12:4 little endian */\n+#define DRM_FORMAT_XVYU16161616\tfourcc_code('X', 'V', '4', '8') /* [63:0] X:Cr:Y:Cb 16:16:16:16 little endian */\n+\n+/*\n+ * packed YCbCr420 2x2 tiled formats\n+ * first 64 bits will contain Y,Cb,Cr components for a 2x2 tile\n+ */\n+/* [63:0] A3:A2:Y3:0:Cr0:0:Y2:0:A1:A0:Y1:0:Cb0:0:Y0:0 1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little endian */\n+#define DRM_FORMAT_Y0L0\t\tfourcc_code('Y', '0', 'L', '0')\n+/* [63:0] X3:X2:Y3:0:Cr0:0:Y2:0:X1:X0:Y1:0:Cb0:0:Y0:0 1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little endian */\n+#define DRM_FORMAT_X0L0\t\tfourcc_code('X', '0', 'L', '0')\n+\n+/* [63:0] A3:A2:Y3:Cr0:Y2:A1:A0:Y1:Cb0:Y0 1:1:10:10:10:1:1:10:10:10 little endian */\n+#define DRM_FORMAT_Y0L2\t\tfourcc_code('Y', '0', 'L', '2')\n+/* [63:0] X3:X2:Y3:Cr0:Y2:X1:X0:Y1:Cb0:Y0 1:1:10:10:10:1:1:10:10:10 little endian */\n+#define DRM_FORMAT_X0L2\t\tfourcc_code('X', '0', 'L', '2')\n+\n+/*\n+ * 1-plane YUV 4:2:0\n+ * In these formats, the component ordering is specified (Y, followed by U\n+ * then V), but the exact Linear layout is undefined.\n+ * These formats can only be used with a non-Linear modifier.\n+ */\n+#define DRM_FORMAT_YUV420_8BIT\tfourcc_code('Y', 'U', '0', '8')\n+#define DRM_FORMAT_YUV420_10BIT\tfourcc_code('Y', 'U', '1', '0')\n+\n+/*\n+ * 2 plane RGB + A\n+ * index 0 = RGB plane, same format as the corresponding non _A8 format has\n+ * index 1 = A plane, [7:0] A\n+ */\n+#define DRM_FORMAT_XRGB8888_A8\tfourcc_code('X', 'R', 'A', '8')\n+#define DRM_FORMAT_XBGR8888_A8\tfourcc_code('X', 'B', 'A', '8')\n+#define DRM_FORMAT_RGBX8888_A8\tfourcc_code('R', 'X', 'A', '8')\n+#define DRM_FORMAT_BGRX8888_A8\tfourcc_code('B', 'X', 'A', '8')\n+#define DRM_FORMAT_RGB888_A8\tfourcc_code('R', '8', 'A', '8')\n+#define DRM_FORMAT_BGR888_A8\tfourcc_code('B', '8', 'A', '8')\n+#define DRM_FORMAT_RGB565_A8\tfourcc_code('R', '5', 'A', '8')\n+#define DRM_FORMAT_BGR565_A8\tfourcc_code('B', '5', 'A', '8')\n+\n+/*\n+ * 2 plane YCbCr\n+ * index 0 = Y plane, [7:0] Y\n+ * index 1 = Cr:Cb plane, [15:0] Cr:Cb little endian\n+ * or\n+ * index 1 = Cb:Cr plane, [15:0] Cb:Cr little endian\n+ */\n+#define DRM_FORMAT_NV12\t\tfourcc_code('N', 'V', '1', '2') /* 2x2 subsampled Cr:Cb plane */\n+#define DRM_FORMAT_NV21\t\tfourcc_code('N', 'V', '2', '1') /* 2x2 subsampled Cb:Cr plane */\n+#define DRM_FORMAT_NV16\t\tfourcc_code('N', 'V', '1', '6') /* 2x1 subsampled Cr:Cb plane */\n+#define DRM_FORMAT_NV61\t\tfourcc_code('N', 'V', '6', '1') /* 2x1 subsampled Cb:Cr plane */\n+#define DRM_FORMAT_NV24\t\tfourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */\n+#define DRM_FORMAT_NV42\t\tfourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */\n+\n+/*\n+ * 2 plane YCbCr MSB aligned\n+ * index 0 = Y plane, [15:0] Y:x [10:6] little endian\n+ * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian\n+ */\n+#define DRM_FORMAT_P210\t\tfourcc_code('P', '2', '1', '0') /* 2x1 subsampled Cr:Cb plane, 10 bit per channel */\n+\n+/*\n+ * 2 plane YCbCr MSB aligned\n+ * index 0 = Y plane, [15:0] Y:x [10:6] little endian\n+ * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian\n+ */\n+#define DRM_FORMAT_P010\t\tfourcc_code('P', '0', '1', '0') /* 2x2 subsampled Cr:Cb plane 10 bits per channel */\n+\n+/*\n+ * 2 plane YCbCr MSB aligned\n+ * index 0 = Y plane, [15:0] Y:x [12:4] little endian\n+ * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [12:4:12:4] little endian\n+ */\n+#define DRM_FORMAT_P012\t\tfourcc_code('P', '0', '1', '2') /* 2x2 subsampled Cr:Cb plane 12 bits per channel */\n+\n+/*\n+ * 2 plane YCbCr MSB aligned\n+ * index 0 = Y plane, [15:0] Y little endian\n+ * index 1 = Cr:Cb plane, [31:0] Cr:Cb [16:16] little endian\n+ */\n+#define DRM_FORMAT_P016\t\tfourcc_code('P', '0', '1', '6') /* 2x2 subsampled Cr:Cb plane 16 bits per channel */\n+\n+/*\n+ * 3 plane YCbCr\n+ * index 0: Y plane, [7:0] Y\n+ * index 1: Cb plane, [7:0] Cb\n+ * index 2: Cr plane, [7:0] Cr\n+ * or\n+ * index 1: Cr plane, [7:0] Cr\n+ * index 2: Cb plane, [7:0] Cb\n+ */\n+#define DRM_FORMAT_YUV410\tfourcc_code('Y', 'U', 'V', '9') /* 4x4 subsampled Cb (1) and Cr (2) planes */\n+#define DRM_FORMAT_YVU410\tfourcc_code('Y', 'V', 'U', '9') /* 4x4 subsampled Cr (1) and Cb (2) planes */\n+#define DRM_FORMAT_YUV411\tfourcc_code('Y', 'U', '1', '1') /* 4x1 subsampled Cb (1) and Cr (2) planes */\n+#define DRM_FORMAT_YVU411\tfourcc_code('Y', 'V', '1', '1') /* 4x1 subsampled Cr (1) and Cb (2) planes */\n+#define DRM_FORMAT_YUV420\tfourcc_code('Y', 'U', '1', '2') /* 2x2 subsampled Cb (1) and Cr (2) planes */\n+#define DRM_FORMAT_YVU420\tfourcc_code('Y', 'V', '1', '2') /* 2x2 subsampled Cr (1) and Cb (2) planes */\n+#define DRM_FORMAT_YUV422\tfourcc_code('Y', 'U', '1', '6') /* 2x1 subsampled Cb (1) and Cr (2) planes */\n+#define DRM_FORMAT_YVU422\tfourcc_code('Y', 'V', '1', '6') /* 2x1 subsampled Cr (1) and Cb (2) planes */\n+#define DRM_FORMAT_YUV444\tfourcc_code('Y', 'U', '2', '4') /* non-subsampled Cb (1) and Cr (2) planes */\n+#define DRM_FORMAT_YVU444\tfourcc_code('Y', 'V', '2', '4') /* non-subsampled Cr (1) and Cb (2) planes */\n+\n+\n+/*\n+ * Format Modifiers:\n+ *\n+ * Format modifiers describe, typically, a re-ordering or modification\n+ * of the data in a plane of an FB. This can be used to express tiled/\n+ * swizzled formats, or compression, or a combination of the two.\n+ *\n+ * The upper 8 bits of the format modifier are a vendor-id as assigned\n+ * below. The lower 56 bits are assigned as vendor sees fit.\n+ */\n+\n+/* Vendor Ids: */\n+#define DRM_FORMAT_MOD_NONE 0\n+#define DRM_FORMAT_MOD_VENDOR_NONE 0\n+#define DRM_FORMAT_MOD_VENDOR_INTEL 0x01\n+#define DRM_FORMAT_MOD_VENDOR_AMD 0x02\n+#define DRM_FORMAT_MOD_VENDOR_NVIDIA 0x03\n+#define DRM_FORMAT_MOD_VENDOR_SAMSUNG 0x04\n+#define DRM_FORMAT_MOD_VENDOR_QCOM 0x05\n+#define DRM_FORMAT_MOD_VENDOR_VIVANTE 0x06\n+#define DRM_FORMAT_MOD_VENDOR_BROADCOM 0x07\n+#define DRM_FORMAT_MOD_VENDOR_ARM 0x08\n+#define DRM_FORMAT_MOD_VENDOR_ALLWINNER 0x09\n+\n+/* add more to the end as needed */\n+\n+#define DRM_FORMAT_RESERVED\t ((1ULL << 56) - 1)\n+\n+#define fourcc_mod_code(vendor, val) \\\n+\t((((__u64)DRM_FORMAT_MOD_VENDOR_## vendor) << 56) | ((val) & 0x00ffffffffffffffULL))\n+\n+/*\n+ * Format Modifier tokens:\n+ *\n+ * When adding a new token please document the layout with a code comment,\n+ * similar to the fourcc codes above. drm_fourcc.h is considered the\n+ * authoritative source for all of these.\n+ */\n+\n+/*\n+ * Invalid Modifier\n+ *\n+ * This modifier can be used as a sentinel to terminate the format modifiers\n+ * list, or to initialize a variable with an invalid modifier. It might also be\n+ * used to report an error back to userspace for certain APIs.\n+ */\n+#define DRM_FORMAT_MOD_INVALID\tfourcc_mod_code(NONE, DRM_FORMAT_RESERVED)\n+\n+/*\n+ * Linear Layout\n+ *\n+ * Just plain linear layout. Note that this is different from no specifying any\n+ * modifier (e.g. not setting DRM_MODE_FB_MODIFIERS in the DRM_ADDFB2 ioctl),\n+ * which tells the driver to also take driver-internal information into account\n+ * and so might actually result in a tiled framebuffer.\n+ */\n+#define DRM_FORMAT_MOD_LINEAR\tfourcc_mod_code(NONE, 0)\n+\n+/* Intel framebuffer modifiers */\n+\n+/*\n+ * Intel X-tiling layout\n+ *\n+ * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)\n+ * in row-major layout. Within the tile bytes are laid out row-major, with\n+ * a platform-dependent stride. On top of that the memory can apply\n+ * platform-depending swizzling of some higher address bits into bit6.\n+ *\n+ * This format is highly platforms specific and not useful for cross-driver\n+ * sharing. It exists since on a given platform it does uniquely identify the\n+ * layout in a simple way for i915-specific userspace.\n+ */\n+#define I915_FORMAT_MOD_X_TILED\tfourcc_mod_code(INTEL, 1)\n+\n+/*\n+ * Intel Y-tiling layout\n+ *\n+ * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)\n+ * in row-major layout. Within the tile bytes are laid out in OWORD (16 bytes)\n+ * chunks column-major, with a platform-dependent height. On top of that the\n+ * memory can apply platform-depending swizzling of some higher address bits\n+ * into bit6.\n+ *\n+ * This format is highly platforms specific and not useful for cross-driver\n+ * sharing. It exists since on a given platform it does uniquely identify the\n+ * layout in a simple way for i915-specific userspace.\n+ */\n+#define I915_FORMAT_MOD_Y_TILED\tfourcc_mod_code(INTEL, 2)\n+\n+/*\n+ * Intel Yf-tiling layout\n+ *\n+ * This is a tiled layout using 4Kb tiles in row-major layout.\n+ * Within the tile pixels are laid out in 16 256 byte units / sub-tiles which\n+ * are arranged in four groups (two wide, two high) with column-major layout.\n+ * Each group therefore consits out of four 256 byte units, which are also laid\n+ * out as 2x2 column-major.\n+ * 256 byte units are made out of four 64 byte blocks of pixels, producing\n+ * either a square block or a 2:1 unit.\n+ * 64 byte blocks of pixels contain four pixel rows of 16 bytes, where the width\n+ * in pixel depends on the pixel depth.\n+ */\n+#define I915_FORMAT_MOD_Yf_TILED fourcc_mod_code(INTEL, 3)\n+\n+/*\n+ * Intel color control surface (CCS) for render compression\n+ *\n+ * The framebuffer format must be one of the 8:8:8:8 RGB formats.\n+ * The main surface will be plane index 0 and must be Y/Yf-tiled,\n+ * the CCS will be plane index 1.\n+ *\n+ * Each CCS tile matches a 1024x512 pixel area of the main surface.\n+ * To match certain aspects of the 3D hardware the CCS is\n+ * considered to be made up of normal 128Bx32 Y tiles, Thus\n+ * the CCS pitch must be specified in multiples of 128 bytes.\n+ *\n+ * In reality the CCS tile appears to be a 64Bx64 Y tile, composed\n+ * of QWORD (8 bytes) chunks instead of OWORD (16 bytes) chunks.\n+ * But that fact is not relevant unless the memory is accessed\n+ * directly.\n+ */\n+#define I915_FORMAT_MOD_Y_TILED_CCS\tfourcc_mod_code(INTEL, 4)\n+#define I915_FORMAT_MOD_Yf_TILED_CCS\tfourcc_mod_code(INTEL, 5)\n+\n+/*\n+ * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks\n+ *\n+ * Macroblocks are laid in a Z-shape, and each pixel data is following the\n+ * standard NV12 style.\n+ * As for NV12, an image is the result of two frame buffers: one for Y,\n+ * one for the interleaved Cb/Cr components (1/2 the height of the Y buffer).\n+ * Alignment requirements are (for each buffer):\n+ * - multiple of 128 pixels for the width\n+ * - multiple of 32 pixels for the height\n+ *\n+ * For more information: see https://linuxtv.org/downloads/v4l-dvb-apis/re32.html\n+ */\n+#define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE\tfourcc_mod_code(SAMSUNG, 1)\n+\n+/*\n+ * Tiled, 16 (pixels) x 16 (lines) - sized macroblocks\n+ *\n+ * This is a simple tiled layout using tiles of 16x16 pixels in a row-major\n+ * layout. For YCbCr formats Cb/Cr components are taken in such a way that\n+ * they correspond to their 16x16 luma block.\n+ */\n+#define DRM_FORMAT_MOD_SAMSUNG_16_16_TILE\tfourcc_mod_code(SAMSUNG, 2)\n+\n+/*\n+ * Qualcomm Compressed Format\n+ *\n+ * Refers to a compressed variant of the base format that is compressed.\n+ * Implementation may be platform and base-format specific.\n+ *\n+ * Each macrotile consists of m x n (mostly 4 x 4) tiles.\n+ * Pixel data pitch/stride is aligned with macrotile width.\n+ * Pixel data height is aligned with macrotile height.\n+ * Entire pixel data buffer is aligned with 4k(bytes).\n+ */\n+#define DRM_FORMAT_MOD_QCOM_COMPRESSED\tfourcc_mod_code(QCOM, 1)\n+\n+/* Vivante framebuffer modifiers */\n+\n+/*\n+ * Vivante 4x4 tiling layout\n+ *\n+ * This is a simple tiled layout using tiles of 4x4 pixels in a row-major\n+ * layout.\n+ */\n+#define DRM_FORMAT_MOD_VIVANTE_TILED\t\tfourcc_mod_code(VIVANTE, 1)\n+\n+/*\n+ * Vivante 64x64 super-tiling layout\n+ *\n+ * This is a tiled layout using 64x64 pixel super-tiles, where each super-tile\n+ * contains 8x4 groups of 2x4 tiles of 4x4 pixels (like above) each, all in row-\n+ * major layout.\n+ *\n+ * For more information: see\n+ * https://github.com/etnaviv/etna_viv/blob/master/doc/hardware.md#texture-tiling\n+ */\n+#define DRM_FORMAT_MOD_VIVANTE_SUPER_TILED\tfourcc_mod_code(VIVANTE, 2)\n+\n+/*\n+ * Vivante 4x4 tiling layout for dual-pipe\n+ *\n+ * Same as the 4x4 tiling layout, except every second 4x4 pixel tile starts at a\n+ * different base address. Offsets from the base addresses are therefore halved\n+ * compared to the non-split tiled layout.\n+ */\n+#define DRM_FORMAT_MOD_VIVANTE_SPLIT_TILED\tfourcc_mod_code(VIVANTE, 3)\n+\n+/*\n+ * Vivante 64x64 super-tiling layout for dual-pipe\n+ *\n+ * Same as the 64x64 super-tiling layout, except every second 4x4 pixel tile\n+ * starts at a different base address. Offsets from the base addresses are\n+ * therefore halved compared to the non-split super-tiled layout.\n+ */\n+#define DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED fourcc_mod_code(VIVANTE, 4)\n+\n+/* NVIDIA frame buffer modifiers */\n+\n+/*\n+ * Tegra Tiled Layout, used by Tegra 2, 3 and 4.\n+ *\n+ * Pixels are arranged in simple tiles of 16 x 16 bytes.\n+ */\n+#define DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED fourcc_mod_code(NVIDIA, 1)\n+\n+/*\n+ * 16Bx2 Block Linear layout, used by desktop GPUs, and Tegra K1 and later\n+ *\n+ * Pixels are arranged in 64x8 Groups Of Bytes (GOBs). GOBs are then stacked\n+ * vertically by a power of 2 (1 to 32 GOBs) to form a block.\n+ *\n+ * Within a GOB, data is ordered as 16B x 2 lines sectors laid in Z-shape.\n+ *\n+ * Parameter 'v' is the log2 encoding of the number of GOBs stacked vertically.\n+ * Valid values are:\n+ *\n+ * 0 == ONE_GOB\n+ * 1 == TWO_GOBS\n+ * 2 == FOUR_GOBS\n+ * 3 == EIGHT_GOBS\n+ * 4 == SIXTEEN_GOBS\n+ * 5 == THIRTYTWO_GOBS\n+ *\n+ * Chapter 20 \"Pixel Memory Formats\" of the Tegra X1 TRM describes this format\n+ * in full detail.\n+ */\n+#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(v) \\\n+\tfourcc_mod_code(NVIDIA, 0x10 | ((v) & 0xf))\n+\n+#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_ONE_GOB \\\n+\tfourcc_mod_code(NVIDIA, 0x10)\n+#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_TWO_GOB \\\n+\tfourcc_mod_code(NVIDIA, 0x11)\n+#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_FOUR_GOB \\\n+\tfourcc_mod_code(NVIDIA, 0x12)\n+#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_EIGHT_GOB \\\n+\tfourcc_mod_code(NVIDIA, 0x13)\n+#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_SIXTEEN_GOB \\\n+\tfourcc_mod_code(NVIDIA, 0x14)\n+#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_THIRTYTWO_GOB \\\n+\tfourcc_mod_code(NVIDIA, 0x15)\n+\n+/*\n+ * Some Broadcom modifiers take parameters, for example the number of\n+ * vertical lines in the image. Reserve the lower 32 bits for modifier\n+ * type, and the next 24 bits for parameters. Top 8 bits are the\n+ * vendor code.\n+ */\n+#define __fourcc_mod_broadcom_param_shift 8\n+#define __fourcc_mod_broadcom_param_bits 48\n+#define fourcc_mod_broadcom_code(val, params) \\\n+\tfourcc_mod_code(BROADCOM, ((((__u64)params) << __fourcc_mod_broadcom_param_shift) | val))\n+#define fourcc_mod_broadcom_param(m) \\\n+\t((int)(((m) >> __fourcc_mod_broadcom_param_shift) &\t\\\n+\t ((1ULL << __fourcc_mod_broadcom_param_bits) - 1)))\n+#define fourcc_mod_broadcom_mod(m) \\\n+\t((m) & ~(((1ULL << __fourcc_mod_broadcom_param_bits) - 1) <<\t\\\n+\t\t __fourcc_mod_broadcom_param_shift))\n+\n+/*\n+ * Broadcom VC4 \"T\" format\n+ *\n+ * This is the primary layout that the V3D GPU can texture from (it\n+ * can't do linear). The T format has:\n+ *\n+ * - 64b utiles of pixels in a raster-order grid according to cpp. It's 4x4\n+ * pixels at 32 bit depth.\n+ *\n+ * - 1k subtiles made of a 4x4 raster-order grid of 64b utiles (so usually\n+ * 16x16 pixels).\n+ *\n+ * - 4k tiles made of a 2x2 grid of 1k subtiles (so usually 32x32 pixels). On\n+ * even 4k tile rows, they're arranged as (BL, TL, TR, BR), and on odd rows\n+ * they're (TR, BR, BL, TL), where bottom left is start of memory.\n+ *\n+ * - an image made of 4k tiles in rows either left-to-right (even rows of 4k\n+ * tiles) or right-to-left (odd rows of 4k tiles).\n+ */\n+#define DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED fourcc_mod_code(BROADCOM, 1)\n+\n+/*\n+ * Broadcom SAND format\n+ *\n+ * This is the native format that the H.264 codec block uses. For VC4\n+ * HVS, it is only valid for H.264 (NV12/21) and RGBA modes.\n+ *\n+ * The image can be considered to be split into columns, and the\n+ * columns are placed consecutively into memory. The width of those\n+ * columns can be either 32, 64, 128, or 256 pixels, but in practice\n+ * only 128 pixel columns are used.\n+ *\n+ * The pitch between the start of each column is set to optimally\n+ * switch between SDRAM banks. This is passed as the number of lines\n+ * of column width in the modifier (we can't use the stride value due\n+ * to various core checks that look at it , so you should set the\n+ * stride to width*cpp).\n+ *\n+ * Note that the column height for this format modifier is the same\n+ * for all of the planes, assuming that each column contains both Y\n+ * and UV. Some SAND-using hardware stores UV in a separate tiled\n+ * image from Y to reduce the column height, which is not supported\n+ * with these modifiers.\n+ */\n+\n+#define DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(v) \\\n+\tfourcc_mod_broadcom_code(2, v)\n+#define DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(v) \\\n+\tfourcc_mod_broadcom_code(3, v)\n+#define DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(v) \\\n+\tfourcc_mod_broadcom_code(4, v)\n+#define DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(v) \\\n+\tfourcc_mod_broadcom_code(5, v)\n+\n+#define DRM_FORMAT_MOD_BROADCOM_SAND32 \\\n+\tDRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(0)\n+#define DRM_FORMAT_MOD_BROADCOM_SAND64 \\\n+\tDRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(0)\n+#define DRM_FORMAT_MOD_BROADCOM_SAND128 \\\n+\tDRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(0)\n+#define DRM_FORMAT_MOD_BROADCOM_SAND256 \\\n+\tDRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(0)\n+\n+/* Broadcom UIF format\n+ *\n+ * This is the common format for the current Broadcom multimedia\n+ * blocks, including V3D 3.x and newer, newer video codecs, and\n+ * displays.\n+ *\n+ * The image consists of utiles (64b blocks), UIF blocks (2x2 utiles),\n+ * and macroblocks (4x4 UIF blocks). Those 4x4 UIF block groups are\n+ * stored in columns, with padding between the columns to ensure that\n+ * moving from one column to the next doesn't hit the same SDRAM page\n+ * bank.\n+ *\n+ * To calculate the padding, it is assumed that each hardware block\n+ * and the software driving it knows the platform's SDRAM page size,\n+ * number of banks, and XOR address, and that it's identical between\n+ * all blocks using the format. This tiling modifier will use XOR as\n+ * necessary to reduce the padding. If a hardware block can't do XOR,\n+ * the assumption is that a no-XOR tiling modifier will be created.\n+ */\n+#define DRM_FORMAT_MOD_BROADCOM_UIF fourcc_mod_code(BROADCOM, 6)\n+\n+/*\n+ * Arm Framebuffer Compression (AFBC) modifiers\n+ *\n+ * AFBC is a proprietary lossless image compression protocol and format.\n+ * It provides fine-grained random access and minimizes the amount of data\n+ * transferred between IP blocks.\n+ *\n+ * AFBC has several features which may be supported and/or used, which are\n+ * represented using bits in the modifier. Not all combinations are valid,\n+ * and different devices or use-cases may support different combinations.\n+ *\n+ * Further information on the use of AFBC modifiers can be found in\n+ * Documentation/gpu/afbc.rst\n+ */\n+#define DRM_FORMAT_MOD_ARM_AFBC(__afbc_mode)\tfourcc_mod_code(ARM, __afbc_mode)\n+\n+/*\n+ * AFBC superblock size\n+ *\n+ * Indicates the superblock size(s) used for the AFBC buffer. The buffer\n+ * size (in pixels) must be aligned to a multiple of the superblock size.\n+ * Four lowest significant bits(LSBs) are reserved for block size.\n+ *\n+ * Where one superblock size is specified, it applies to all planes of the\n+ * buffer (e.g. 16x16, 32x8). When multiple superblock sizes are specified,\n+ * the first applies to the Luma plane and the second applies to the Chroma\n+ * plane(s). e.g. (32x8_64x4 means 32x8 Luma, with 64x4 Chroma).\n+ * Multiple superblock sizes are only valid for multi-plane YCbCr formats.\n+ */\n+#define AFBC_FORMAT_MOD_BLOCK_SIZE_MASK 0xf\n+#define AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 (1ULL)\n+#define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8 (2ULL)\n+#define AFBC_FORMAT_MOD_BLOCK_SIZE_64x4 (3ULL)\n+#define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8_64x4 (4ULL)\n+\n+/*\n+ * AFBC lossless colorspace transform\n+ *\n+ * Indicates that the buffer makes use of the AFBC lossless colorspace\n+ * transform.\n+ */\n+#define AFBC_FORMAT_MOD_YTR (1ULL << 4)\n+\n+/*\n+ * AFBC block-split\n+ *\n+ * Indicates that the payload of each superblock is split. The second\n+ * half of the payload is positioned at a predefined offset from the start\n+ * of the superblock payload.\n+ */\n+#define AFBC_FORMAT_MOD_SPLIT (1ULL << 5)\n+\n+/*\n+ * AFBC sparse layout\n+ *\n+ * This flag indicates that the payload of each superblock must be stored at a\n+ * predefined position relative to the other superblocks in the same AFBC\n+ * buffer. This order is the same order used by the header buffer. In this mode\n+ * each superblock is given the same amount of space as an uncompressed\n+ * superblock of the particular format would require, rounding up to the next\n+ * multiple of 128 bytes in size.\n+ */\n+#define AFBC_FORMAT_MOD_SPARSE (1ULL << 6)\n+\n+/*\n+ * AFBC copy-block restrict\n+ *\n+ * Buffers with this flag must obey the copy-block restriction. The restriction\n+ * is such that there are no copy-blocks referring across the border of 8x8\n+ * blocks. For the subsampled data the 8x8 limitation is also subsampled.\n+ */\n+#define AFBC_FORMAT_MOD_CBR (1ULL << 7)\n+\n+/*\n+ * AFBC tiled layout\n+ *\n+ * The tiled layout groups superblocks in 8x8 or 4x4 tiles, where all\n+ * superblocks inside a tile are stored together in memory. 8x8 tiles are used\n+ * for pixel formats up to and including 32 bpp while 4x4 tiles are used for\n+ * larger bpp formats. The order between the tiles is scan line.\n+ * When the tiled layout is used, the buffer size (in pixels) must be aligned\n+ * to the tile size.\n+ */\n+#define AFBC_FORMAT_MOD_TILED (1ULL << 8)\n+\n+/*\n+ * AFBC solid color blocks\n+ *\n+ * Indicates that the buffer makes use of solid-color blocks, whereby bandwidth\n+ * can be reduced if a whole superblock is a single color.\n+ */\n+#define AFBC_FORMAT_MOD_SC (1ULL << 9)\n+\n+/*\n+ * AFBC double-buffer\n+ *\n+ * Indicates that the buffer is allocated in a layout safe for front-buffer\n+ * rendering.\n+ */\n+#define AFBC_FORMAT_MOD_DB (1ULL << 10)\n+\n+/*\n+ * AFBC buffer content hints\n+ *\n+ * Indicates that the buffer includes per-superblock content hints.\n+ */\n+#define AFBC_FORMAT_MOD_BCH (1ULL << 11)\n+\n+/*\n+ * Allwinner tiled modifier\n+ *\n+ * This tiling mode is implemented by the VPU found on all Allwinner platforms,\n+ * codenamed sunxi. It is associated with a YUV format that uses either 2 or 3\n+ * planes.\n+ *\n+ * With this tiling, the luminance samples are disposed in tiles representing\n+ * 32x32 pixels and the chrominance samples in tiles representing 32x64 pixels.\n+ * The pixel order in each tile is linear and the tiles are disposed linearly,\n+ * both in row-major order.\n+ */\n+#define DRM_FORMAT_MOD_ALLWINNER_TILED fourcc_mod_code(ALLWINNER, 1)\n+\n+#if defined(__cplusplus)\n+}\n+#endif\n+\n+#endif /* DRM_FOURCC_H */\ndiff --git a/include/linux/drm_mode.h b/include/linux/drm_mode.h\nnew file mode 100644\nindex 000000000000..735c8cfdaaa1\n--- /dev/null\n+++ b/include/linux/drm_mode.h\n@@ -0,0 +1,1032 @@\n+/*\n+ * Copyright (c) 2007 Dave Airlie \n+ * Copyright (c) 2007 Jakob Bornecrantz \n+ * Copyright (c) 2008 Red Hat Inc.\n+ * Copyright (c) 2007-2008 Tungsten Graphics, Inc., Cedar Park, TX., USA\n+ * Copyright (c) 2007-2008 Intel Corporation\n+ *\n+ * Permission is hereby granted, free of charge, to any person obtaining a\n+ * copy of this software and associated documentation files (the \"Software\"),\n+ * to deal in the Software without restriction, including without limitation\n+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,\n+ * and/or sell copies of the Software, and to permit persons to whom the\n+ * Software is furnished to do so, subject to the following conditions:\n+ *\n+ * The above copyright notice and this permission notice shall be included in\n+ * all copies or substantial portions of the Software.\n+ *\n+ * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS\n+ * IN THE SOFTWARE.\n+ */\n+\n+#ifndef _DRM_MODE_H\n+#define _DRM_MODE_H\n+\n+#include \"drm.h\"\n+\n+#if defined(__cplusplus)\n+extern \"C\" {\n+#endif\n+\n+/**\n+ * DOC: overview\n+ *\n+ * DRM exposes many UAPI and structure definition to have a consistent\n+ * and standardized interface with user.\n+ * Userspace can refer to these structure definitions and UAPI formats\n+ * to communicate to driver\n+ */\n+\n+#define DRM_CONNECTOR_NAME_LEN\t32\n+#define DRM_DISPLAY_MODE_LEN\t32\n+#define DRM_PROP_NAME_LEN\t32\n+\n+#define DRM_MODE_TYPE_BUILTIN\t(1<<0) /* deprecated */\n+#define DRM_MODE_TYPE_CLOCK_C\t((1<<1) | DRM_MODE_TYPE_BUILTIN) /* deprecated */\n+#define DRM_MODE_TYPE_CRTC_C\t((1<<2) | DRM_MODE_TYPE_BUILTIN) /* deprecated */\n+#define DRM_MODE_TYPE_PREFERRED\t(1<<3)\n+#define DRM_MODE_TYPE_DEFAULT\t(1<<4) /* deprecated */\n+#define DRM_MODE_TYPE_USERDEF\t(1<<5)\n+#define DRM_MODE_TYPE_DRIVER\t(1<<6)\n+\n+#define DRM_MODE_TYPE_ALL\t(DRM_MODE_TYPE_PREFERRED |\t\\\n+\t\t\t\t DRM_MODE_TYPE_USERDEF |\t\\\n+\t\t\t\t DRM_MODE_TYPE_DRIVER)\n+\n+/* Video mode flags */\n+/* bit compatible with the xrandr RR_ definitions (bits 0-13)\n+ *\n+ * ABI warning: Existing userspace really expects\n+ * the mode flags to match the xrandr definitions. Any\n+ * changes that don't match the xrandr definitions will\n+ * likely need a new client cap or some other mechanism\n+ * to avoid breaking existing userspace. This includes\n+ * allocating new flags in the previously unused bits!\n+ */\n+#define DRM_MODE_FLAG_PHSYNC\t\t\t(1<<0)\n+#define DRM_MODE_FLAG_NHSYNC\t\t\t(1<<1)\n+#define DRM_MODE_FLAG_PVSYNC\t\t\t(1<<2)\n+#define DRM_MODE_FLAG_NVSYNC\t\t\t(1<<3)\n+#define DRM_MODE_FLAG_INTERLACE\t\t\t(1<<4)\n+#define DRM_MODE_FLAG_DBLSCAN\t\t\t(1<<5)\n+#define DRM_MODE_FLAG_CSYNC\t\t\t(1<<6)\n+#define DRM_MODE_FLAG_PCSYNC\t\t\t(1<<7)\n+#define DRM_MODE_FLAG_NCSYNC\t\t\t(1<<8)\n+#define DRM_MODE_FLAG_HSKEW\t\t\t(1<<9) /* hskew provided */\n+#define DRM_MODE_FLAG_BCAST\t\t\t(1<<10) /* deprecated */\n+#define DRM_MODE_FLAG_PIXMUX\t\t\t(1<<11) /* deprecated */\n+#define DRM_MODE_FLAG_DBLCLK\t\t\t(1<<12)\n+#define DRM_MODE_FLAG_CLKDIV2\t\t\t(1<<13)\n+ /*\n+ * When adding a new stereo mode don't forget to adjust DRM_MODE_FLAGS_3D_MAX\n+ * (define not exposed to user space).\n+ */\n+#define DRM_MODE_FLAG_3D_MASK\t\t\t(0x1f<<14)\n+#define DRM_MODE_FLAG_3D_NONE\t\t(0<<14)\n+#define DRM_MODE_FLAG_3D_FRAME_PACKING\t\t(1<<14)\n+#define DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE\t(2<<14)\n+#define DRM_MODE_FLAG_3D_LINE_ALTERNATIVE\t(3<<14)\n+#define DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL\t(4<<14)\n+#define DRM_MODE_FLAG_3D_L_DEPTH\t\t(5<<14)\n+#define DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH\t(6<<14)\n+#define DRM_MODE_FLAG_3D_TOP_AND_BOTTOM\t(7<<14)\n+#define DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF\t(8<<14)\n+\n+/* Picture aspect ratio options */\n+#define DRM_MODE_PICTURE_ASPECT_NONE\t\t0\n+#define DRM_MODE_PICTURE_ASPECT_4_3\t\t1\n+#define DRM_MODE_PICTURE_ASPECT_16_9\t\t2\n+#define DRM_MODE_PICTURE_ASPECT_64_27\t\t3\n+#define DRM_MODE_PICTURE_ASPECT_256_135\t\t4\n+\n+/* Content type options */\n+#define DRM_MODE_CONTENT_TYPE_NO_DATA\t\t0\n+#define DRM_MODE_CONTENT_TYPE_GRAPHICS\t\t1\n+#define DRM_MODE_CONTENT_TYPE_PHOTO\t\t2\n+#define DRM_MODE_CONTENT_TYPE_CINEMA\t\t3\n+#define DRM_MODE_CONTENT_TYPE_GAME\t\t4\n+\n+/* Aspect ratio flag bitmask (4 bits 22:19) */\n+#define DRM_MODE_FLAG_PIC_AR_MASK\t\t(0x0F<<19)\n+#define DRM_MODE_FLAG_PIC_AR_NONE \\\n+\t\t\t(DRM_MODE_PICTURE_ASPECT_NONE<<19)\n+#define DRM_MODE_FLAG_PIC_AR_4_3 \\\n+\t\t\t(DRM_MODE_PICTURE_ASPECT_4_3<<19)\n+#define DRM_MODE_FLAG_PIC_AR_16_9 \\\n+\t\t\t(DRM_MODE_PICTURE_ASPECT_16_9<<19)\n+#define DRM_MODE_FLAG_PIC_AR_64_27 \\\n+\t\t\t(DRM_MODE_PICTURE_ASPECT_64_27<<19)\n+#define DRM_MODE_FLAG_PIC_AR_256_135 \\\n+\t\t\t(DRM_MODE_PICTURE_ASPECT_256_135<<19)\n+\n+#define DRM_MODE_FLAG_ALL\t(DRM_MODE_FLAG_PHSYNC |\t\t\\\n+\t\t\t\t DRM_MODE_FLAG_NHSYNC |\t\t\\\n+\t\t\t\t DRM_MODE_FLAG_PVSYNC |\t\t\\\n+\t\t\t\t DRM_MODE_FLAG_NVSYNC |\t\t\\\n+\t\t\t\t DRM_MODE_FLAG_INTERLACE |\t\\\n+\t\t\t\t DRM_MODE_FLAG_DBLSCAN |\t\\\n+\t\t\t\t DRM_MODE_FLAG_CSYNC |\t\t\\\n+\t\t\t\t DRM_MODE_FLAG_PCSYNC |\t\t\\\n+\t\t\t\t DRM_MODE_FLAG_NCSYNC |\t\t\\\n+\t\t\t\t DRM_MODE_FLAG_HSKEW |\t\t\\\n+\t\t\t\t DRM_MODE_FLAG_DBLCLK |\t\t\\\n+\t\t\t\t DRM_MODE_FLAG_CLKDIV2 |\t\\\n+\t\t\t\t DRM_MODE_FLAG_3D_MASK)\n+\n+/* DPMS flags */\n+/* bit compatible with the xorg definitions. */\n+#define DRM_MODE_DPMS_ON\t0\n+#define DRM_MODE_DPMS_STANDBY\t1\n+#define DRM_MODE_DPMS_SUSPEND\t2\n+#define DRM_MODE_DPMS_OFF\t3\n+\n+/* Scaling mode options */\n+#define DRM_MODE_SCALE_NONE\t\t0 /* Unmodified timing (display or\n+\t\t\t\t\t software can still scale) */\n+#define DRM_MODE_SCALE_FULLSCREEN\t1 /* Full screen, ignore aspect */\n+#define DRM_MODE_SCALE_CENTER\t\t2 /* Centered, no scaling */\n+#define DRM_MODE_SCALE_ASPECT\t\t3 /* Full screen, preserve aspect */\n+\n+/* Dithering mode options */\n+#define DRM_MODE_DITHERING_OFF\t0\n+#define DRM_MODE_DITHERING_ON\t1\n+#define DRM_MODE_DITHERING_AUTO 2\n+\n+/* Dirty info options */\n+#define DRM_MODE_DIRTY_OFF 0\n+#define DRM_MODE_DIRTY_ON 1\n+#define DRM_MODE_DIRTY_ANNOTATE 2\n+\n+/* Link Status options */\n+#define DRM_MODE_LINK_STATUS_GOOD\t0\n+#define DRM_MODE_LINK_STATUS_BAD\t1\n+\n+/*\n+ * DRM_MODE_ROTATE_\n+ *\n+ * Signals that a drm plane is been rotated degrees in counter\n+ * clockwise direction.\n+ *\n+ * This define is provided as a convenience, looking up the property id\n+ * using the name->prop id lookup is the preferred method.\n+ */\n+#define DRM_MODE_ROTATE_0 (1<<0)\n+#define DRM_MODE_ROTATE_90 (1<<1)\n+#define DRM_MODE_ROTATE_180 (1<<2)\n+#define DRM_MODE_ROTATE_270 (1<<3)\n+\n+/*\n+ * DRM_MODE_ROTATE_MASK\n+ *\n+ * Bitmask used to look for drm plane rotations.\n+ */\n+#define DRM_MODE_ROTATE_MASK (\\\n+\t\tDRM_MODE_ROTATE_0 | \\\n+\t\tDRM_MODE_ROTATE_90 | \\\n+\t\tDRM_MODE_ROTATE_180 | \\\n+\t\tDRM_MODE_ROTATE_270)\n+\n+/*\n+ * DRM_MODE_REFLECT_\n+ *\n+ * Signals that the contents of a drm plane is reflected along the axis,\n+ * in the same way as mirroring.\n+ * See kerneldoc chapter \"Plane Composition Properties\" for more details.\n+ *\n+ * This define is provided as a convenience, looking up the property id\n+ * using the name->prop id lookup is the preferred method.\n+ */\n+#define DRM_MODE_REFLECT_X (1<<4)\n+#define DRM_MODE_REFLECT_Y (1<<5)\n+\n+/*\n+ * DRM_MODE_REFLECT_MASK\n+ *\n+ * Bitmask used to look for drm plane reflections.\n+ */\n+#define DRM_MODE_REFLECT_MASK (\\\n+\t\tDRM_MODE_REFLECT_X | \\\n+\t\tDRM_MODE_REFLECT_Y)\n+\n+/* Content Protection Flags */\n+#define DRM_MODE_CONTENT_PROTECTION_UNDESIRED\t0\n+#define DRM_MODE_CONTENT_PROTECTION_DESIRED 1\n+#define DRM_MODE_CONTENT_PROTECTION_ENABLED 2\n+\n+struct drm_mode_modeinfo {\n+\t__u32 clock;\n+\t__u16 hdisplay;\n+\t__u16 hsync_start;\n+\t__u16 hsync_end;\n+\t__u16 htotal;\n+\t__u16 hskew;\n+\t__u16 vdisplay;\n+\t__u16 vsync_start;\n+\t__u16 vsync_end;\n+\t__u16 vtotal;\n+\t__u16 vscan;\n+\n+\t__u32 vrefresh;\n+\n+\t__u32 flags;\n+\t__u32 type;\n+\tchar name[DRM_DISPLAY_MODE_LEN];\n+};\n+\n+struct drm_mode_card_res {\n+\t__u64 fb_id_ptr;\n+\t__u64 crtc_id_ptr;\n+\t__u64 connector_id_ptr;\n+\t__u64 encoder_id_ptr;\n+\t__u32 count_fbs;\n+\t__u32 count_crtcs;\n+\t__u32 count_connectors;\n+\t__u32 count_encoders;\n+\t__u32 min_width;\n+\t__u32 max_width;\n+\t__u32 min_height;\n+\t__u32 max_height;\n+};\n+\n+struct drm_mode_crtc {\n+\t__u64 set_connectors_ptr;\n+\t__u32 count_connectors;\n+\n+\t__u32 crtc_id; /**< Id */\n+\t__u32 fb_id; /**< Id of framebuffer */\n+\n+\t__u32 x; /**< x Position on the framebuffer */\n+\t__u32 y; /**< y Position on the framebuffer */\n+\n+\t__u32 gamma_size;\n+\t__u32 mode_valid;\n+\tstruct drm_mode_modeinfo mode;\n+};\n+\n+#define DRM_MODE_PRESENT_TOP_FIELD\t(1<<0)\n+#define DRM_MODE_PRESENT_BOTTOM_FIELD\t(1<<1)\n+\n+/* Planes blend with or override other bits on the CRTC */\n+struct drm_mode_set_plane {\n+\t__u32 plane_id;\n+\t__u32 crtc_id;\n+\t__u32 fb_id; /* fb object contains surface format type */\n+\t__u32 flags; /* see above flags */\n+\n+\t/* Signed dest location allows it to be partially off screen */\n+\t__s32 crtc_x;\n+\t__s32 crtc_y;\n+\t__u32 crtc_w;\n+\t__u32 crtc_h;\n+\n+\t/* Source values are 16.16 fixed point */\n+\t__u32 src_x;\n+\t__u32 src_y;\n+\t__u32 src_h;\n+\t__u32 src_w;\n+};\n+\n+struct drm_mode_get_plane {\n+\t__u32 plane_id;\n+\n+\t__u32 crtc_id;\n+\t__u32 fb_id;\n+\n+\t__u32 possible_crtcs;\n+\t__u32 gamma_size;\n+\n+\t__u32 count_format_types;\n+\t__u64 format_type_ptr;\n+};\n+\n+struct drm_mode_get_plane_res {\n+\t__u64 plane_id_ptr;\n+\t__u32 count_planes;\n+};\n+\n+#define DRM_MODE_ENCODER_NONE\t0\n+#define DRM_MODE_ENCODER_DAC\t1\n+#define DRM_MODE_ENCODER_TMDS\t2\n+#define DRM_MODE_ENCODER_LVDS\t3\n+#define DRM_MODE_ENCODER_TVDAC\t4\n+#define DRM_MODE_ENCODER_VIRTUAL 5\n+#define DRM_MODE_ENCODER_DSI\t6\n+#define DRM_MODE_ENCODER_DPMST\t7\n+#define DRM_MODE_ENCODER_DPI\t8\n+\n+struct drm_mode_get_encoder {\n+\t__u32 encoder_id;\n+\t__u32 encoder_type;\n+\n+\t__u32 crtc_id; /**< Id of crtc */\n+\n+\t__u32 possible_crtcs;\n+\t__u32 possible_clones;\n+};\n+\n+/* This is for connectors with multiple signal types. */\n+/* Try to match DRM_MODE_CONNECTOR_X as closely as possible. */\n+enum drm_mode_subconnector {\n+\tDRM_MODE_SUBCONNECTOR_Automatic = 0,\n+\tDRM_MODE_SUBCONNECTOR_Unknown = 0,\n+\tDRM_MODE_SUBCONNECTOR_DVID = 3,\n+\tDRM_MODE_SUBCONNECTOR_DVIA = 4,\n+\tDRM_MODE_SUBCONNECTOR_Composite = 5,\n+\tDRM_MODE_SUBCONNECTOR_SVIDEO = 6,\n+\tDRM_MODE_SUBCONNECTOR_Component = 8,\n+\tDRM_MODE_SUBCONNECTOR_SCART = 9,\n+};\n+\n+#define DRM_MODE_CONNECTOR_Unknown\t0\n+#define DRM_MODE_CONNECTOR_VGA\t\t1\n+#define DRM_MODE_CONNECTOR_DVII\t\t2\n+#define DRM_MODE_CONNECTOR_DVID\t\t3\n+#define DRM_MODE_CONNECTOR_DVIA\t\t4\n+#define DRM_MODE_CONNECTOR_Composite\t5\n+#define DRM_MODE_CONNECTOR_SVIDEO\t6\n+#define DRM_MODE_CONNECTOR_LVDS\t\t7\n+#define DRM_MODE_CONNECTOR_Component\t8\n+#define DRM_MODE_CONNECTOR_9PinDIN\t9\n+#define DRM_MODE_CONNECTOR_DisplayPort\t10\n+#define DRM_MODE_CONNECTOR_HDMIA\t11\n+#define DRM_MODE_CONNECTOR_HDMIB\t12\n+#define DRM_MODE_CONNECTOR_TV\t\t13\n+#define DRM_MODE_CONNECTOR_eDP\t\t14\n+#define DRM_MODE_CONNECTOR_VIRTUAL 15\n+#define DRM_MODE_CONNECTOR_DSI\t\t16\n+#define DRM_MODE_CONNECTOR_DPI\t\t17\n+#define DRM_MODE_CONNECTOR_WRITEBACK\t18\n+#define DRM_MODE_CONNECTOR_SPI\t\t19\n+\n+struct drm_mode_get_connector {\n+\n+\t__u64 encoders_ptr;\n+\t__u64 modes_ptr;\n+\t__u64 props_ptr;\n+\t__u64 prop_values_ptr;\n+\n+\t__u32 count_modes;\n+\t__u32 count_props;\n+\t__u32 count_encoders;\n+\n+\t__u32 encoder_id; /**< Current Encoder */\n+\t__u32 connector_id; /**< Id */\n+\t__u32 connector_type;\n+\t__u32 connector_type_id;\n+\n+\t__u32 connection;\n+\t__u32 mm_width; /**< width in millimeters */\n+\t__u32 mm_height; /**< height in millimeters */\n+\t__u32 subpixel;\n+\n+\t__u32 pad;\n+};\n+\n+#define DRM_MODE_PROP_PENDING\t(1<<0) /* deprecated, do not use */\n+#define DRM_MODE_PROP_RANGE\t(1<<1)\n+#define DRM_MODE_PROP_IMMUTABLE\t(1<<2)\n+#define DRM_MODE_PROP_ENUM\t(1<<3) /* enumerated type with text strings */\n+#define DRM_MODE_PROP_BLOB\t(1<<4)\n+#define DRM_MODE_PROP_BITMASK\t(1<<5) /* bitmask of enumerated types */\n+\n+/* non-extended types: legacy bitmask, one bit per type: */\n+#define DRM_MODE_PROP_LEGACY_TYPE ( \\\n+\t\tDRM_MODE_PROP_RANGE | \\\n+\t\tDRM_MODE_PROP_ENUM | \\\n+\t\tDRM_MODE_PROP_BLOB | \\\n+\t\tDRM_MODE_PROP_BITMASK)\n+\n+/* extended-types: rather than continue to consume a bit per type,\n+ * grab a chunk of the bits to use as integer type id.\n+ */\n+#define DRM_MODE_PROP_EXTENDED_TYPE\t0x0000ffc0\n+#define DRM_MODE_PROP_TYPE(n)\t\t((n) << 6)\n+#define DRM_MODE_PROP_OBJECT\t\tDRM_MODE_PROP_TYPE(1)\n+#define DRM_MODE_PROP_SIGNED_RANGE\tDRM_MODE_PROP_TYPE(2)\n+\n+/* the PROP_ATOMIC flag is used to hide properties from userspace that\n+ * is not aware of atomic properties. This is mostly to work around\n+ * older userspace (DDX drivers) that read/write each prop they find,\n+ * witout being aware that this could be triggering a lengthy modeset.\n+ */\n+#define DRM_MODE_PROP_ATOMIC 0x80000000\n+\n+struct drm_mode_property_enum {\n+\t__u64 value;\n+\tchar name[DRM_PROP_NAME_LEN];\n+};\n+\n+struct drm_mode_get_property {\n+\t__u64 values_ptr; /* values and blob lengths */\n+\t__u64 enum_blob_ptr; /* enum and blob id ptrs */\n+\n+\t__u32 prop_id;\n+\t__u32 flags;\n+\tchar name[DRM_PROP_NAME_LEN];\n+\n+\t__u32 count_values;\n+\t/* This is only used to count enum values, not blobs. The _blobs is\n+\t * simply because of a historical reason, i.e. backwards compat. */\n+\t__u32 count_enum_blobs;\n+};\n+\n+struct drm_mode_connector_set_property {\n+\t__u64 value;\n+\t__u32 prop_id;\n+\t__u32 connector_id;\n+};\n+\n+#define DRM_MODE_OBJECT_CRTC 0xcccccccc\n+#define DRM_MODE_OBJECT_CONNECTOR 0xc0c0c0c0\n+#define DRM_MODE_OBJECT_ENCODER 0xe0e0e0e0\n+#define DRM_MODE_OBJECT_MODE 0xdededede\n+#define DRM_MODE_OBJECT_PROPERTY 0xb0b0b0b0\n+#define DRM_MODE_OBJECT_FB 0xfbfbfbfb\n+#define DRM_MODE_OBJECT_BLOB 0xbbbbbbbb\n+#define DRM_MODE_OBJECT_PLANE 0xeeeeeeee\n+#define DRM_MODE_OBJECT_ANY 0\n+\n+struct drm_mode_obj_get_properties {\n+\t__u64 props_ptr;\n+\t__u64 prop_values_ptr;\n+\t__u32 count_props;\n+\t__u32 obj_id;\n+\t__u32 obj_type;\n+};\n+\n+struct drm_mode_obj_set_property {\n+\t__u64 value;\n+\t__u32 prop_id;\n+\t__u32 obj_id;\n+\t__u32 obj_type;\n+};\n+\n+struct drm_mode_get_blob {\n+\t__u32 blob_id;\n+\t__u32 length;\n+\t__u64 data;\n+};\n+\n+struct drm_mode_fb_cmd {\n+\t__u32 fb_id;\n+\t__u32 width;\n+\t__u32 height;\n+\t__u32 pitch;\n+\t__u32 bpp;\n+\t__u32 depth;\n+\t/* driver specific handle */\n+\t__u32 handle;\n+};\n+\n+#define DRM_MODE_FB_INTERLACED\t(1<<0) /* for interlaced framebuffers */\n+#define DRM_MODE_FB_MODIFIERS\t(1<<1) /* enables ->modifer[] */\n+\n+struct drm_mode_fb_cmd2 {\n+\t__u32 fb_id;\n+\t__u32 width;\n+\t__u32 height;\n+\t__u32 pixel_format; /* fourcc code from drm_fourcc.h */\n+\t__u32 flags; /* see above flags */\n+\n+\t/*\n+\t * In case of planar formats, this ioctl allows up to 4\n+\t * buffer objects with offsets and pitches per plane.\n+\t * The pitch and offset order is dictated by the fourcc,\n+\t * e.g. NV12 (http://fourcc.org/yuv.php#NV12) is described as:\n+\t *\n+\t * YUV 4:2:0 image with a plane of 8 bit Y samples\n+\t * followed by an interleaved U/V plane containing\n+\t * 8 bit 2x2 subsampled colour difference samples.\n+\t *\n+\t * So it would consist of Y as offsets[0] and UV as\n+\t * offsets[1]. Note that offsets[0] will generally\n+\t * be 0 (but this is not required).\n+\t *\n+\t * To accommodate tiled, compressed, etc formats, a\n+\t * modifier can be specified. The default value of zero\n+\t * indicates \"native\" format as specified by the fourcc.\n+\t * Vendor specific modifier token. Note that even though\n+\t * it looks like we have a modifier per-plane, we in fact\n+\t * do not. The modifier for each plane must be identical.\n+\t * Thus all combinations of different data layouts for\n+\t * multi plane formats must be enumerated as separate\n+\t * modifiers.\n+\t */\n+\t__u32 handles[4];\n+\t__u32 pitches[4]; /* pitch for each plane */\n+\t__u32 offsets[4]; /* offset of each plane */\n+\t__u64 modifier[4]; /* ie, tiling, compress */\n+};\n+\n+#define DRM_MODE_FB_DIRTY_ANNOTATE_COPY 0x01\n+#define DRM_MODE_FB_DIRTY_ANNOTATE_FILL 0x02\n+#define DRM_MODE_FB_DIRTY_FLAGS 0x03\n+\n+#define DRM_MODE_FB_DIRTY_MAX_CLIPS 256\n+\n+/*\n+ * Mark a region of a framebuffer as dirty.\n+ *\n+ * Some hardware does not automatically update display contents\n+ * as a hardware or software draw to a framebuffer. This ioctl\n+ * allows userspace to tell the kernel and the hardware what\n+ * regions of the framebuffer have changed.\n+ *\n+ * The kernel or hardware is free to update more then just the\n+ * region specified by the clip rects. The kernel or hardware\n+ * may also delay and/or coalesce several calls to dirty into a\n+ * single update.\n+ *\n+ * Userspace may annotate the updates, the annotates are a\n+ * promise made by the caller that the change is either a copy\n+ * of pixels or a fill of a single color in the region specified.\n+ *\n+ * If the DRM_MODE_FB_DIRTY_ANNOTATE_COPY flag is given then\n+ * the number of updated regions are half of num_clips given,\n+ * where the clip rects are paired in src and dst. The width and\n+ * height of each one of the pairs must match.\n+ *\n+ * If the DRM_MODE_FB_DIRTY_ANNOTATE_FILL flag is given the caller\n+ * promises that the region specified of the clip rects is filled\n+ * completely with a single color as given in the color argument.\n+ */\n+\n+struct drm_mode_fb_dirty_cmd {\n+\t__u32 fb_id;\n+\t__u32 flags;\n+\t__u32 color;\n+\t__u32 num_clips;\n+\t__u64 clips_ptr;\n+};\n+\n+struct drm_mode_mode_cmd {\n+\t__u32 connector_id;\n+\tstruct drm_mode_modeinfo mode;\n+};\n+\n+#define DRM_MODE_CURSOR_BO\t0x01\n+#define DRM_MODE_CURSOR_MOVE\t0x02\n+#define DRM_MODE_CURSOR_FLAGS\t0x03\n+\n+/*\n+ * depending on the value in flags different members are used.\n+ *\n+ * CURSOR_BO uses\n+ * crtc_id\n+ * width\n+ * height\n+ * handle - if 0 turns the cursor off\n+ *\n+ * CURSOR_MOVE uses\n+ * crtc_id\n+ * x\n+ * y\n+ */\n+struct drm_mode_cursor {\n+\t__u32 flags;\n+\t__u32 crtc_id;\n+\t__s32 x;\n+\t__s32 y;\n+\t__u32 width;\n+\t__u32 height;\n+\t/* driver specific handle */\n+\t__u32 handle;\n+};\n+\n+struct drm_mode_cursor2 {\n+\t__u32 flags;\n+\t__u32 crtc_id;\n+\t__s32 x;\n+\t__s32 y;\n+\t__u32 width;\n+\t__u32 height;\n+\t/* driver specific handle */\n+\t__u32 handle;\n+\t__s32 hot_x;\n+\t__s32 hot_y;\n+};\n+\n+struct drm_mode_crtc_lut {\n+\t__u32 crtc_id;\n+\t__u32 gamma_size;\n+\n+\t/* pointers to arrays */\n+\t__u64 red;\n+\t__u64 green;\n+\t__u64 blue;\n+};\n+\n+struct drm_color_ctm {\n+\t/*\n+\t * Conversion matrix in S31.32 sign-magnitude\n+\t * (not two's complement!) format.\n+\t */\n+\t__u64 matrix[9];\n+};\n+\n+struct drm_color_lut {\n+\t/*\n+\t * Values are mapped linearly to 0.0 - 1.0 range, with 0x0 == 0.0 and\n+\t * 0xffff == 1.0.\n+\t */\n+\t__u16 red;\n+\t__u16 green;\n+\t__u16 blue;\n+\t__u16 reserved;\n+};\n+\n+/**\n+ * struct hdr_metadata_infoframe - HDR Metadata Infoframe Data.\n+ *\n+ * HDR Metadata Infoframe as per CTA 861.G spec. This is expected\n+ * to match exactly with the spec.\n+ *\n+ * Userspace is expected to pass the metadata information as per\n+ * the format described in this structure.\n+ */\n+struct hdr_metadata_infoframe {\n+\t/**\n+\t * @eotf: Electro-Optical Transfer Function (EOTF)\n+\t * used in the stream.\n+\t */\n+\t__u8 eotf;\n+\t/**\n+\t * @metadata_type: Static_Metadata_Descriptor_ID.\n+\t */\n+\t__u8 metadata_type;\n+\t/**\n+\t * @display_primaries: Color Primaries of the Data.\n+\t * These are coded as unsigned 16-bit values in units of\n+\t * 0.00002, where 0x0000 represents zero and 0xC350\n+\t * represents 1.0000.\n+\t * @display_primaries.x: X cordinate of color primary.\n+\t * @display_primaries.y: Y cordinate of color primary.\n+\t */\n+\tstruct {\n+\t\t__u16 x, y;\n+\t\t} display_primaries[3];\n+\t/**\n+\t * @white_point: White Point of Colorspace Data.\n+\t * These are coded as unsigned 16-bit values in units of\n+\t * 0.00002, where 0x0000 represents zero and 0xC350\n+\t * represents 1.0000.\n+\t * @white_point.x: X cordinate of whitepoint of color primary.\n+\t * @white_point.y: Y cordinate of whitepoint of color primary.\n+\t */\n+\tstruct {\n+\t\t__u16 x, y;\n+\t\t} white_point;\n+\t/**\n+\t * @max_display_mastering_luminance: Max Mastering Display Luminance.\n+\t * This value is coded as an unsigned 16-bit value in units of 1 cd/m2,\n+\t * where 0x0001 represents 1 cd/m2 and 0xFFFF represents 65535 cd/m2.\n+\t */\n+\t__u16 max_display_mastering_luminance;\n+\t/**\n+\t * @min_display_mastering_luminance: Min Mastering Display Luminance.\n+\t * This value is coded as an unsigned 16-bit value in units of\n+\t * 0.0001 cd/m2, where 0x0001 represents 0.0001 cd/m2 and 0xFFFF\n+\t * represents 6.5535 cd/m2.\n+\t */\n+\t__u16 min_display_mastering_luminance;\n+\t/**\n+\t * @max_cll: Max Content Light Level.\n+\t * This value is coded as an unsigned 16-bit value in units of 1 cd/m2,\n+\t * where 0x0001 represents 1 cd/m2 and 0xFFFF represents 65535 cd/m2.\n+\t */\n+\t__u16 max_cll;\n+\t/**\n+\t * @max_fall: Max Frame Average Light Level.\n+\t * This value is coded as an unsigned 16-bit value in units of 1 cd/m2,\n+\t * where 0x0001 represents 1 cd/m2 and 0xFFFF represents 65535 cd/m2.\n+\t */\n+\t__u16 max_fall;\n+};\n+\n+/**\n+ * struct hdr_output_metadata - HDR output metadata\n+ *\n+ * Metadata Information to be passed from userspace\n+ */\n+struct hdr_output_metadata {\n+\t/**\n+\t * @metadata_type: Static_Metadata_Descriptor_ID.\n+\t */\n+\t__u32 metadata_type;\n+\t/**\n+\t * @hdmi_metadata_type1: HDR Metadata Infoframe.\n+\t */\n+\tunion {\n+\t\tstruct hdr_metadata_infoframe hdmi_metadata_type1;\n+\t};\n+};\n+\n+#define DRM_MODE_PAGE_FLIP_EVENT 0x01\n+#define DRM_MODE_PAGE_FLIP_ASYNC 0x02\n+#define DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE 0x4\n+#define DRM_MODE_PAGE_FLIP_TARGET_RELATIVE 0x8\n+#define DRM_MODE_PAGE_FLIP_TARGET (DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE | \\\n+\t\t\t\t DRM_MODE_PAGE_FLIP_TARGET_RELATIVE)\n+#define DRM_MODE_PAGE_FLIP_FLAGS (DRM_MODE_PAGE_FLIP_EVENT | \\\n+\t\t\t\t DRM_MODE_PAGE_FLIP_ASYNC | \\\n+\t\t\t\t DRM_MODE_PAGE_FLIP_TARGET)\n+\n+/*\n+ * Request a page flip on the specified crtc.\n+ *\n+ * This ioctl will ask KMS to schedule a page flip for the specified\n+ * crtc. Once any pending rendering targeting the specified fb (as of\n+ * ioctl time) has completed, the crtc will be reprogrammed to display\n+ * that fb after the next vertical refresh. The ioctl returns\n+ * immediately, but subsequent rendering to the current fb will block\n+ * in the execbuffer ioctl until the page flip happens. If a page\n+ * flip is already pending as the ioctl is called, EBUSY will be\n+ * returned.\n+ *\n+ * Flag DRM_MODE_PAGE_FLIP_EVENT requests that drm sends back a vblank\n+ * event (see drm.h: struct drm_event_vblank) when the page flip is\n+ * done. The user_data field passed in with this ioctl will be\n+ * returned as the user_data field in the vblank event struct.\n+ *\n+ * Flag DRM_MODE_PAGE_FLIP_ASYNC requests that the flip happen\n+ * 'as soon as possible', meaning that it not delay waiting for vblank.\n+ * This may cause tearing on the screen.\n+ *\n+ * The reserved field must be zero.\n+ */\n+\n+struct drm_mode_crtc_page_flip {\n+\t__u32 crtc_id;\n+\t__u32 fb_id;\n+\t__u32 flags;\n+\t__u32 reserved;\n+\t__u64 user_data;\n+};\n+\n+/*\n+ * Request a page flip on the specified crtc.\n+ *\n+ * Same as struct drm_mode_crtc_page_flip, but supports new flags and\n+ * re-purposes the reserved field:\n+ *\n+ * The sequence field must be zero unless either of the\n+ * DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE/RELATIVE flags is specified. When\n+ * the ABSOLUTE flag is specified, the sequence field denotes the absolute\n+ * vblank sequence when the flip should take effect. When the RELATIVE\n+ * flag is specified, the sequence field denotes the relative (to the\n+ * current one when the ioctl is called) vblank sequence when the flip\n+ * should take effect. NOTE: DRM_IOCTL_WAIT_VBLANK must still be used to\n+ * make sure the vblank sequence before the target one has passed before\n+ * calling this ioctl. The purpose of the\n+ * DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE/RELATIVE flags is merely to clarify\n+ * the target for when code dealing with a page flip runs during a\n+ * vertical blank period.\n+ */\n+\n+struct drm_mode_crtc_page_flip_target {\n+\t__u32 crtc_id;\n+\t__u32 fb_id;\n+\t__u32 flags;\n+\t__u32 sequence;\n+\t__u64 user_data;\n+};\n+\n+/* create a dumb scanout buffer */\n+struct drm_mode_create_dumb {\n+\t__u32 height;\n+\t__u32 width;\n+\t__u32 bpp;\n+\t__u32 flags;\n+\t/* handle, pitch, size will be returned */\n+\t__u32 handle;\n+\t__u32 pitch;\n+\t__u64 size;\n+};\n+\n+/* set up for mmap of a dumb scanout buffer */\n+struct drm_mode_map_dumb {\n+\t/** Handle for the object being mapped. */\n+\t__u32 handle;\n+\t__u32 pad;\n+\t/**\n+\t * Fake offset to use for subsequent mmap call\n+\t *\n+\t * This is a fixed-size type for 32/64 compatibility.\n+\t */\n+\t__u64 offset;\n+};\n+\n+struct drm_mode_destroy_dumb {\n+\t__u32 handle;\n+};\n+\n+/* page-flip flags are valid, plus: */\n+#define DRM_MODE_ATOMIC_TEST_ONLY 0x0100\n+#define DRM_MODE_ATOMIC_NONBLOCK 0x0200\n+#define DRM_MODE_ATOMIC_ALLOW_MODESET 0x0400\n+\n+#define DRM_MODE_ATOMIC_FLAGS (\\\n+\t\tDRM_MODE_PAGE_FLIP_EVENT |\\\n+\t\tDRM_MODE_PAGE_FLIP_ASYNC |\\\n+\t\tDRM_MODE_ATOMIC_TEST_ONLY |\\\n+\t\tDRM_MODE_ATOMIC_NONBLOCK |\\\n+\t\tDRM_MODE_ATOMIC_ALLOW_MODESET)\n+\n+struct drm_mode_atomic {\n+\t__u32 flags;\n+\t__u32 count_objs;\n+\t__u64 objs_ptr;\n+\t__u64 count_props_ptr;\n+\t__u64 props_ptr;\n+\t__u64 prop_values_ptr;\n+\t__u64 reserved;\n+\t__u64 user_data;\n+};\n+\n+struct drm_format_modifier_blob {\n+#define FORMAT_BLOB_CURRENT 1\n+\t/* Version of this blob format */\n+\t__u32 version;\n+\n+\t/* Flags */\n+\t__u32 flags;\n+\n+\t/* Number of fourcc formats supported */\n+\t__u32 count_formats;\n+\n+\t/* Where in this blob the formats exist (in bytes) */\n+\t__u32 formats_offset;\n+\n+\t/* Number of drm_format_modifiers */\n+\t__u32 count_modifiers;\n+\n+\t/* Where in this blob the modifiers exist (in bytes) */\n+\t__u32 modifiers_offset;\n+\n+\t/* __u32 formats[] */\n+\t/* struct drm_format_modifier modifiers[] */\n+};\n+\n+struct drm_format_modifier {\n+\t/* Bitmask of formats in get_plane format list this info applies to. The\n+\t * offset allows a sliding window of which 64 formats (bits).\n+\t *\n+\t * Some examples:\n+\t * In today's world with < 65 formats, and formats 0, and 2 are\n+\t * supported\n+\t * 0x0000000000000005\n+\t *\t\t ^-offset = 0, formats = 5\n+\t *\n+\t * If the number formats grew to 128, and formats 98-102 are\n+\t * supported with the modifier:\n+\t *\n+\t * 0x0000007c00000000 0000000000000000\n+\t *\t\t ^\n+\t *\t\t |__offset = 64, formats = 0x7c00000000\n+\t *\n+\t */\n+\t__u64 formats;\n+\t__u32 offset;\n+\t__u32 pad;\n+\n+\t/* The modifier that applies to the >get_plane format list bitmask. */\n+\t__u64 modifier;\n+};\n+\n+/**\n+ * struct drm_mode_create_blob - Create New block property\n+ * @data: Pointer to data to copy.\n+ * @length: Length of data to copy.\n+ * @blob_id: new property ID.\n+ * Create a new 'blob' data property, copying length bytes from data pointer,\n+ * and returning new blob ID.\n+ */\n+struct drm_mode_create_blob {\n+\t/** Pointer to data to copy. */\n+\t__u64 data;\n+\t/** Length of data to copy. */\n+\t__u32 length;\n+\t/** Return: new property ID. */\n+\t__u32 blob_id;\n+};\n+\n+/**\n+ * struct drm_mode_destroy_blob - Destroy user blob\n+ * @blob_id: blob_id to destroy\n+ * Destroy a user-created blob property.\n+ */\n+struct drm_mode_destroy_blob {\n+\t__u32 blob_id;\n+};\n+\n+/**\n+ * struct drm_mode_create_lease - Create lease\n+ * @object_ids: Pointer to array of object ids.\n+ * @object_count: Number of object ids.\n+ * @flags: flags for new FD.\n+ * @lessee_id: unique identifier for lessee.\n+ * @fd: file descriptor to new drm_master file.\n+ * Lease mode resources, creating another drm_master.\n+ */\n+struct drm_mode_create_lease {\n+\t/** Pointer to array of object ids (__u32) */\n+\t__u64 object_ids;\n+\t/** Number of object ids */\n+\t__u32 object_count;\n+\t/** flags for new FD (O_CLOEXEC, etc) */\n+\t__u32 flags;\n+\n+\t/** Return: unique identifier for lessee. */\n+\t__u32 lessee_id;\n+\t/** Return: file descriptor to new drm_master file */\n+\t__u32 fd;\n+};\n+\n+/**\n+ * struct drm_mode_list_lessees - List lessees\n+ * @count_lessees: Number of lessees.\n+ * @pad: pad.\n+ * @lessees_ptr: Pointer to lessess.\n+ * List lesses from a drm_master\n+ */\n+struct drm_mode_list_lessees {\n+\t/** Number of lessees.\n+\t * On input, provides length of the array.\n+\t * On output, provides total number. No\n+\t * more than the input number will be written\n+\t * back, so two calls can be used to get\n+\t * the size and then the data.\n+\t */\n+\t__u32 count_lessees;\n+\t__u32 pad;\n+\n+\t/** Pointer to lessees.\n+\t * pointer to __u64 array of lessee ids\n+\t */\n+\t__u64 lessees_ptr;\n+};\n+\n+/**\n+ * struct drm_mode_get_lease - Get Lease\n+ * @count_objects: Number of leased objects.\n+ * @pad: pad.\n+ * @objects_ptr: Pointer to objects.\n+ * Get leased objects\n+ */\n+struct drm_mode_get_lease {\n+\t/** Number of leased objects.\n+\t * On input, provides length of the array.\n+\t * On output, provides total number. No\n+\t * more than the input number will be written\n+\t * back, so two calls can be used to get\n+\t * the size and then the data.\n+\t */\n+\t__u32 count_objects;\n+\t__u32 pad;\n+\n+\t/** Pointer to objects.\n+\t * pointer to __u32 array of object ids\n+\t */\n+\t__u64 objects_ptr;\n+};\n+\n+/**\n+ * struct drm_mode_revoke_lease - Revoke lease\n+ * @lessee_id: Unique ID of lessee.\n+ * Revoke lease\n+ */\n+struct drm_mode_revoke_lease {\n+\t/** Unique ID of lessee\n+\t */\n+\t__u32 lessee_id;\n+};\n+\n+/**\n+ * struct drm_mode_rect - Two dimensional rectangle.\n+ * @x1: Horizontal starting coordinate (inclusive).\n+ * @y1: Vertical starting coordinate (inclusive).\n+ * @x2: Horizontal ending coordinate (exclusive).\n+ * @y2: Vertical ending coordinate (exclusive).\n+ *\n+ * With drm subsystem using struct drm_rect to manage rectangular area this\n+ * export it to user-space.\n+ *\n+ * Currently used by drm_mode_atomic blob property FB_DAMAGE_CLIPS.\n+ */\n+struct drm_mode_rect {\n+\t__s32 x1;\n+\t__s32 y1;\n+\t__s32 x2;\n+\t__s32 y2;\n+};\n+\n+#if defined(__cplusplus)\n+}\n+#endif\n+\n+#endif\n","prefixes":["libcamera-devel","02/10"]}