{"id":19414,"url":"https://patchwork.libcamera.org/api/patches/19414/?format=json","web_url":"https://patchwork.libcamera.org/patch/19414/","project":{"id":1,"url":"https://patchwork.libcamera.org/api/projects/1/?format=json","name":"libcamera","link_name":"libcamera","list_id":"libcamera_core","list_email":"libcamera-devel@lists.libcamera.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20240117144242.9903-2-laurent.pinchart@ideasonboard.com>","date":"2024-01-17T14:42:34","name":"[libcamera-devel,1/2] include: linux: Update kernel headers to version v6.7","commit_ref":"df770d4b0a6dc11569beb225b7f47aaaa3863269","pull_url":null,"state":"accepted","archived":false,"hash":"e3f8df6eac4e73dfd2a2d717df4d58ad8b18380d","submitter":{"id":2,"url":"https://patchwork.libcamera.org/api/people/2/?format=json","name":"Laurent Pinchart","email":"laurent.pinchart@ideasonboard.com"},"delegate":null,"mbox":"https://patchwork.libcamera.org/patch/19414/mbox/","series":[{"id":4144,"url":"https://patchwork.libcamera.org/api/series/4144/?format=json","web_url":"https://patchwork.libcamera.org/project/libcamera/list/?series=4144","date":"2024-01-17T14:42:33","name":"libcamera: Enable V4L2 subdev streams support","version":1,"mbox":"https://patchwork.libcamera.org/series/4144/mbox/"}],"comments":"https://patchwork.libcamera.org/api/patches/19414/comments/","check":"pending","checks":"https://patchwork.libcamera.org/api/patches/19414/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"parsemail@patchwork.libcamera.org","Delivered-To":"parsemail@patchwork.libcamera.org","Received":["from lancelot.ideasonboard.com (lancelot.ideasonboard.com\n\t[92.243.16.209])\n\tby patchwork.libcamera.org (Postfix) with ESMTPS id 59D34C3243\n\tfor ;\n\tWed, 17 Jan 2024 14:42:45 +0000 (UTC)","from lancelot.ideasonboard.com (localhost [IPv6:::1])\n\tby lancelot.ideasonboard.com (Postfix) with ESMTP id 7DC8F628BF;\n\tWed, 17 Jan 2024 15:42:42 +0100 (CET)","from perceval.ideasonboard.com (perceval.ideasonboard.com\n\t[213.167.242.64])\n\tby lancelot.ideasonboard.com (Postfix) with ESMTPS id B666A628AE\n\tfor ;\n\tWed, 17 Jan 2024 15:42:40 +0100 (CET)","from pendragon.ideasonboard.com (89-27-53-110.bb.dnainternet.fi\n\t[89.27.53.110])\n\tby perceval.ideasonboard.com (Postfix) with ESMTPSA id D9D2C7EC;\n\tWed, 17 Jan 2024 15:41:30 +0100 (CET)"],"DKIM-Signature":["v=1; a=rsa-sha256; c=relaxed/simple; d=libcamera.org;\n\ts=mail; t=1705502562;\n\tbh=zQNMzOb/yJEO0f3tccEy1bsZHuQO3vTPT/fw8rA9L7Q=;\n\th=To:Date:In-Reply-To:References:Subject:List-Id:List-Unsubscribe:\n\tList-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To:\n\tFrom;\n\tb=ySEAg9oyS9d9jOtVxKD7FJZtobJQTDdax0XVw+tj9w5kgZYVeEG06TPtVeTTLPkA3\n\t4aI5JKF5GeG466xi/xSu0drRbbbTv9wI+g8aNoRftAXdXNaM9PhmxArRAHMbl7Rgib\n\twnnGbOEh0vbnNofSfKIiwquZqjhnZ94bzTYQqtIC1/Y1SpoyrHbFknnDJOG2RJf7l7\n\tsWSitonbnd01XmtDuPRdYQmbBbYr0rlphaujeeUhn0WWIiPE/oLTyGDryvVKRuI7BN\n\tQZNTdzssaOPnLegn6Q3/EB0BLAjhPqsW48u5SXwVRee87A3t0cofhtCUoMAO3nAU2e\n\tqweHVArMt/W5g==","v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com;\n\ts=mail; t=1705502491;\n\tbh=zQNMzOb/yJEO0f3tccEy1bsZHuQO3vTPT/fw8rA9L7Q=;\n\th=From:To:Cc:Subject:Date:In-Reply-To:References:From;\n\tb=JdeCF0SsDKypz0clLElm8ebe8OjAQPSU+bBq7qgxqeL6tgwRGXwwZLhvfH+m1WzJp\n\tVjtB7SfoYSReRX6MSWWB+Elv1TGP/QC/TcnPAqZecP8s/cNFcWU8RwXlcH0nkY8lyd\n\tLF3MgywKkgEwcAcGXkz3vGlYIe/vkttRG3ra/2EM="],"Authentication-Results":"lancelot.ideasonboard.com; dkim=pass (1024-bit key; \n\tunprotected) header.d=ideasonboard.com\n\theader.i=@ideasonboard.com\n\theader.b=\"JdeCF0Ss\"; dkim-atps=neutral","To":"libcamera-devel@lists.libcamera.org","Date":"Wed, 17 Jan 2024 16:42:34 +0200","Message-ID":"<20240117144242.9903-2-laurent.pinchart@ideasonboard.com>","X-Mailer":"git-send-email 2.43.0","In-Reply-To":"<20240117144242.9903-1-laurent.pinchart@ideasonboard.com>","References":"<20240117144242.9903-1-laurent.pinchart@ideasonboard.com>","MIME-Version":"1.0","Content-Type":"text/plain; charset=UTF-8","Content-Transfer-Encoding":"8bit","Subject":"[libcamera-devel] [PATCH 1/2] include: linux: Update kernel headers\n\tto version v6.7","X-BeenThere":"libcamera-devel@lists.libcamera.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","From":"Laurent Pinchart via libcamera-devel\n\t","Reply-To":"Laurent Pinchart ","Errors-To":"libcamera-devel-bounces@lists.libcamera.org","Sender":"\"libcamera-devel\" "},"content":"Update kernel headers to v6.7 using utils/update-kernel-headers.sh\nand re-instating libcamera local modifications.\n\nThe V4L2_SUBDEV_CAP_MPLEXED flag has been renamed to\nV4L2_SUBDEV_CAP_STREAMS in the upstream streams API. Adapt the code base\naccordingly. The flag's numerical value hasn't changed, there is no ABI\nbreakage introduced by the API update.\n\nSigned-off-by: Laurent Pinchart \n---\n include/libcamera/internal/v4l2_subdevice.h | 2 +-\n include/linux/README | 2 +-\n include/linux/dma-buf.h | 84 ++\n include/linux/drm_fourcc.h | 128 +-\n include/linux/intel-ipu3.h | 7 +-\n include/linux/media-bus-format.h | 13 +-\n include/linux/media.h | 29 +-\n include/linux/v4l2-common.h | 39 -\n include/linux/v4l2-controls.h | 1250 ++++++++++++++++++-\n include/linux/v4l2-mediabus.h | 4 -\n include/linux/v4l2-subdev.h | 56 +-\n include/linux/videodev2.h | 69 +-\n 12 files changed, 1536 insertions(+), 147 deletions(-)","diff":"diff --git a/include/libcamera/internal/v4l2_subdevice.h b/include/libcamera/internal/v4l2_subdevice.h\nindex 69862de0585a..17db311bcfb3 100644\n--- a/include/libcamera/internal/v4l2_subdevice.h\n+++ b/include/libcamera/internal/v4l2_subdevice.h\n@@ -36,7 +36,7 @@ struct V4L2SubdeviceCapability final : v4l2_subdev_capability {\n \t}\n \tbool hasStreams() const\n \t{\n-\t\treturn capabilities & V4L2_SUBDEV_CAP_MPLEXED;\n+\t\treturn capabilities & V4L2_SUBDEV_CAP_STREAMS;\n \t}\n };\n \ndiff --git a/include/linux/README b/include/linux/README\nindex 9f61517a119a..101e49970af2 100644\n--- a/include/linux/README\n+++ b/include/linux/README\n@@ -1,4 +1,4 @@\n # SPDX-License-Identifier: CC0-1.0\n \n-Files in this directory are imported from v5.19 of the Linux kernel. Do not\n+Files in this directory are imported from v6.7 of the Linux kernel. Do not\n modify them manually.\ndiff --git a/include/linux/dma-buf.h b/include/linux/dma-buf.h\nindex b1523cb8ab30..5a6fda66d9ad 100644\n--- a/include/linux/dma-buf.h\n+++ b/include/linux/dma-buf.h\n@@ -85,6 +85,88 @@ struct dma_buf_sync {\n \n #define DMA_BUF_NAME_LEN\t32\n \n+/**\n+ * struct dma_buf_export_sync_file - Get a sync_file from a dma-buf\n+ *\n+ * Userspace can perform a DMA_BUF_IOCTL_EXPORT_SYNC_FILE to retrieve the\n+ * current set of fences on a dma-buf file descriptor as a sync_file. CPU\n+ * waits via poll() or other driver-specific mechanisms typically wait on\n+ * whatever fences are on the dma-buf at the time the wait begins. This\n+ * is similar except that it takes a snapshot of the current fences on the\n+ * dma-buf for waiting later instead of waiting immediately. This is\n+ * useful for modern graphics APIs such as Vulkan which assume an explicit\n+ * synchronization model but still need to inter-operate with dma-buf.\n+ *\n+ * The intended usage pattern is the following:\n+ *\n+ * 1. Export a sync_file with flags corresponding to the expected GPU usage\n+ * via DMA_BUF_IOCTL_EXPORT_SYNC_FILE.\n+ *\n+ * 2. Submit rendering work which uses the dma-buf. The work should wait on\n+ * the exported sync file before rendering and produce another sync_file\n+ * when complete.\n+ *\n+ * 3. Import the rendering-complete sync_file into the dma-buf with flags\n+ * corresponding to the GPU usage via DMA_BUF_IOCTL_IMPORT_SYNC_FILE.\n+ *\n+ * Unlike doing implicit synchronization via a GPU kernel driver's exec ioctl,\n+ * the above is not a single atomic operation. If userspace wants to ensure\n+ * ordering via these fences, it is the respnosibility of userspace to use\n+ * locks or other mechanisms to ensure that no other context adds fences or\n+ * submits work between steps 1 and 3 above.\n+ */\n+struct dma_buf_export_sync_file {\n+\t/**\n+\t * @flags: Read/write flags\n+\t *\n+\t * Must be DMA_BUF_SYNC_READ, DMA_BUF_SYNC_WRITE, or both.\n+\t *\n+\t * If DMA_BUF_SYNC_READ is set and DMA_BUF_SYNC_WRITE is not set,\n+\t * the returned sync file waits on any writers of the dma-buf to\n+\t * complete. Waiting on the returned sync file is equivalent to\n+\t * poll() with POLLIN.\n+\t *\n+\t * If DMA_BUF_SYNC_WRITE is set, the returned sync file waits on\n+\t * any users of the dma-buf (read or write) to complete. Waiting\n+\t * on the returned sync file is equivalent to poll() with POLLOUT.\n+\t * If both DMA_BUF_SYNC_WRITE and DMA_BUF_SYNC_READ are set, this\n+\t * is equivalent to just DMA_BUF_SYNC_WRITE.\n+\t */\n+\t__u32 flags;\n+\t/** @fd: Returned sync file descriptor */\n+\t__s32 fd;\n+};\n+\n+/**\n+ * struct dma_buf_import_sync_file - Insert a sync_file into a dma-buf\n+ *\n+ * Userspace can perform a DMA_BUF_IOCTL_IMPORT_SYNC_FILE to insert a\n+ * sync_file into a dma-buf for the purposes of implicit synchronization\n+ * with other dma-buf consumers. This allows clients using explicitly\n+ * synchronized APIs such as Vulkan to inter-op with dma-buf consumers\n+ * which expect implicit synchronization such as OpenGL or most media\n+ * drivers/video.\n+ */\n+struct dma_buf_import_sync_file {\n+\t/**\n+\t * @flags: Read/write flags\n+\t *\n+\t * Must be DMA_BUF_SYNC_READ, DMA_BUF_SYNC_WRITE, or both.\n+\t *\n+\t * If DMA_BUF_SYNC_READ is set and DMA_BUF_SYNC_WRITE is not set,\n+\t * this inserts the sync_file as a read-only fence. Any subsequent\n+\t * implicitly synchronized writes to this dma-buf will wait on this\n+\t * fence but reads will not.\n+\t *\n+\t * If DMA_BUF_SYNC_WRITE is set, this inserts the sync_file as a\n+\t * write fence. All subsequent implicitly synchronized access to\n+\t * this dma-buf will wait on this fence.\n+\t */\n+\t__u32 flags;\n+\t/** @fd: Sync file descriptor */\n+\t__s32 fd;\n+};\n+\n #define DMA_BUF_BASE\t\t'b'\n #define DMA_BUF_IOCTL_SYNC\t_IOW(DMA_BUF_BASE, 0, struct dma_buf_sync)\n \n@@ -94,5 +176,7 @@ struct dma_buf_sync {\n #define DMA_BUF_SET_NAME\t_IOW(DMA_BUF_BASE, 1, const char *)\n #define DMA_BUF_SET_NAME_A\t_IOW(DMA_BUF_BASE, 1, __u32)\n #define DMA_BUF_SET_NAME_B\t_IOW(DMA_BUF_BASE, 1, __u64)\n+#define DMA_BUF_IOCTL_EXPORT_SYNC_FILE\t_IOWR(DMA_BUF_BASE, 2, struct dma_buf_export_sync_file)\n+#define DMA_BUF_IOCTL_IMPORT_SYNC_FILE\t_IOW(DMA_BUF_BASE, 3, struct dma_buf_import_sync_file)\n \n #endif\ndiff --git a/include/linux/drm_fourcc.h b/include/linux/drm_fourcc.h\nindex 1496e097004c..d6c83d9c49f4 100644\n--- a/include/linux/drm_fourcc.h\n+++ b/include/linux/drm_fourcc.h\n@@ -88,6 +88,18 @@ extern \"C\" {\n *\n * The authoritative list of format modifier codes is found in\n * `include/uapi/drm/drm_fourcc.h`\n+ *\n+ * Open Source User Waiver\n+ * -----------------------\n+ *\n+ * Because this is the authoritative source for pixel formats and modifiers\n+ * referenced by GL, Vulkan extensions and other standards and hence used both\n+ * by open source and closed source driver stacks, the usual requirement for an\n+ * upstream in-kernel or open source userspace user does not apply.\n+ *\n+ * To ensure, as much as feasible, compatibility across stacks and avoid\n+ * confusion with incompatible enumerations stakeholders for all relevant driver\n+ * stacks should approve additions.\n */\n \n #define fourcc_code(a, b, c, d) ((__u32)(a) | ((__u32)(b) << 8) | \\\n@@ -99,18 +111,42 @@ extern \"C\" {\n #define DRM_FORMAT_INVALID\t0\n \n /* color index */\n+#define DRM_FORMAT_C1\t\tfourcc_code('C', '1', ' ', ' ') /* [7:0] C0:C1:C2:C3:C4:C5:C6:C7 1:1:1:1:1:1:1:1 eight pixels/byte */\n+#define DRM_FORMAT_C2\t\tfourcc_code('C', '2', ' ', ' ') /* [7:0] C0:C1:C2:C3 2:2:2:2 four pixels/byte */\n+#define DRM_FORMAT_C4\t\tfourcc_code('C', '4', ' ', ' ') /* [7:0] C0:C1 4:4 two pixels/byte */\n #define DRM_FORMAT_C8\t\tfourcc_code('C', '8', ' ', ' ') /* [7:0] C */\n \n-/* 8 bpp Red */\n+/* 1 bpp Darkness (inverse relationship between channel value and brightness) */\n+#define DRM_FORMAT_D1\t\tfourcc_code('D', '1', ' ', ' ') /* [7:0] D0:D1:D2:D3:D4:D5:D6:D7 1:1:1:1:1:1:1:1 eight pixels/byte */\n+\n+/* 2 bpp Darkness (inverse relationship between channel value and brightness) */\n+#define DRM_FORMAT_D2\t\tfourcc_code('D', '2', ' ', ' ') /* [7:0] D0:D1:D2:D3 2:2:2:2 four pixels/byte */\n+\n+/* 4 bpp Darkness (inverse relationship between channel value and brightness) */\n+#define DRM_FORMAT_D4\t\tfourcc_code('D', '4', ' ', ' ') /* [7:0] D0:D1 4:4 two pixels/byte */\n+\n+/* 8 bpp Darkness (inverse relationship between channel value and brightness) */\n+#define DRM_FORMAT_D8\t\tfourcc_code('D', '8', ' ', ' ') /* [7:0] D */\n+\n+/* 1 bpp Red (direct relationship between channel value and brightness) */\n+#define DRM_FORMAT_R1\t\tfourcc_code('R', '1', ' ', ' ') /* [7:0] R0:R1:R2:R3:R4:R5:R6:R7 1:1:1:1:1:1:1:1 eight pixels/byte */\n+\n+/* 2 bpp Red (direct relationship between channel value and brightness) */\n+#define DRM_FORMAT_R2\t\tfourcc_code('R', '2', ' ', ' ') /* [7:0] R0:R1:R2:R3 2:2:2:2 four pixels/byte */\n+\n+/* 4 bpp Red (direct relationship between channel value and brightness) */\n+#define DRM_FORMAT_R4\t\tfourcc_code('R', '4', ' ', ' ') /* [7:0] R0:R1 4:4 two pixels/byte */\n+\n+/* 8 bpp Red (direct relationship between channel value and brightness) */\n #define DRM_FORMAT_R8\t\tfourcc_code('R', '8', ' ', ' ') /* [7:0] R */\n \n-/* 10 bpp Red */\n+/* 10 bpp Red (direct relationship between channel value and brightness) */\n #define DRM_FORMAT_R10\t\tfourcc_code('R', '1', '0', ' ') /* [15:0] x:R 6:10 little endian */\n \n-/* 12 bpp Red */\n+/* 12 bpp Red (direct relationship between channel value and brightness) */\n #define DRM_FORMAT_R12\t\tfourcc_code('R', '1', '2', ' ') /* [15:0] x:R 4:12 little endian */\n \n-/* 16 bpp Red */\n+/* 16 bpp Red (direct relationship between channel value and brightness) */\n #define DRM_FORMAT_R16\t\tfourcc_code('R', '1', '6', ' ') /* [15:0] R little endian */\n \n /* 16 bpp RG */\n@@ -287,6 +323,8 @@ extern \"C\" {\n * index 1 = Cr:Cb plane, [39:0] Cr1:Cb1:Cr0:Cb0 little endian\n */\n #define DRM_FORMAT_NV15\t\tfourcc_code('N', 'V', '1', '5') /* 2x2 subsampled Cr:Cb plane */\n+#define DRM_FORMAT_NV20\t\tfourcc_code('N', 'V', '2', '0') /* 2x1 subsampled Cr:Cb plane */\n+#define DRM_FORMAT_NV30\t\tfourcc_code('N', 'V', '3', '0') /* non-subsampled Cr:Cb plane */\n \n /*\n * 2 plane YCbCr MSB aligned\n@@ -626,7 +664,7 @@ extern \"C\" {\n *\n * The main surface is Y-tiled and is at plane index 0 whereas CCS is linear\n * and at index 1. The clear color is stored at index 2, and the pitch should\n- * be ignored. The clear color structure is 256 bits. The first 128 bits\n+ * be 64 bytes aligned. The clear color structure is 256 bits. The first 128 bits\n * represents Raw Clear Color Red, Green, Blue and Alpha color each represented\n * by 32 bits. The raw clear color is consumed by the 3d engine and generates\n * the converted clear color of size 64 bits. The first 32 bits store the Lower\n@@ -679,13 +717,56 @@ extern \"C\" {\n * outside of the GEM object in a reserved memory area dedicated for the\n * storage of the CCS data for all RC/RC_CC/MC compressible GEM objects. The\n * main surface pitch is required to be a multiple of four Tile 4 widths. The\n- * clear color is stored at plane index 1 and the pitch should be ignored. The\n- * format of the 256 bits of clear color data matches the one used for the\n- * I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC modifier, see its description\n+ * clear color is stored at plane index 1 and the pitch should be 64 bytes\n+ * aligned. The format of the 256 bits of clear color data matches the one used\n+ * for the I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC modifier, see its description\n * for details.\n */\n #define I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC fourcc_mod_code(INTEL, 12)\n \n+/*\n+ * Intel Color Control Surfaces (CCS) for display ver. 14 render compression.\n+ *\n+ * The main surface is tile4 and at plane index 0, the CCS is linear and\n+ * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in\n+ * main surface. In other words, 4 bits in CCS map to a main surface cache\n+ * line pair. The main surface pitch is required to be a multiple of four\n+ * tile4 widths.\n+ */\n+#define I915_FORMAT_MOD_4_TILED_MTL_RC_CCS fourcc_mod_code(INTEL, 13)\n+\n+/*\n+ * Intel Color Control Surfaces (CCS) for display ver. 14 media compression\n+ *\n+ * The main surface is tile4 and at plane index 0, the CCS is linear and\n+ * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in\n+ * main surface. In other words, 4 bits in CCS map to a main surface cache\n+ * line pair. The main surface pitch is required to be a multiple of four\n+ * tile4 widths. For semi-planar formats like NV12, CCS planes follow the\n+ * Y and UV planes i.e., planes 0 and 1 are used for Y and UV surfaces,\n+ * planes 2 and 3 for the respective CCS.\n+ */\n+#define I915_FORMAT_MOD_4_TILED_MTL_MC_CCS fourcc_mod_code(INTEL, 14)\n+\n+/*\n+ * Intel Color Control Surface with Clear Color (CCS) for display ver. 14 render\n+ * compression.\n+ *\n+ * The main surface is tile4 and is at plane index 0 whereas CCS is linear\n+ * and at index 1. The clear color is stored at index 2, and the pitch should\n+ * be ignored. The clear color structure is 256 bits. The first 128 bits\n+ * represents Raw Clear Color Red, Green, Blue and Alpha color each represented\n+ * by 32 bits. The raw clear color is consumed by the 3d engine and generates\n+ * the converted clear color of size 64 bits. The first 32 bits store the Lower\n+ * Converted Clear Color value and the next 32 bits store the Higher Converted\n+ * Clear Color value when applicable. The Converted Clear Color values are\n+ * consumed by the DE. The last 64 bits are used to store Color Discard Enable\n+ * and Depth Clear Value Valid which are ignored by the DE. A CCS cache line\n+ * corresponds to an area of 4x1 tiles in the main surface. The main surface\n+ * pitch is required to be a multiple of 4 tile widths.\n+ */\n+#define I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC fourcc_mod_code(INTEL, 15)\n+\n /*\n * IPU3 Bayer packing layout\n *\n@@ -795,6 +876,35 @@ extern \"C\" {\n */\n #define DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED fourcc_mod_code(VIVANTE, 4)\n \n+/*\n+ * Vivante TS (tile-status) buffer modifiers. They can be combined with all of\n+ * the color buffer tiling modifiers defined above. When TS is present it's a\n+ * separate buffer containing the clear/compression status of each tile. The\n+ * modifiers are defined as VIVANTE_MOD_TS_c_s, where c is the color buffer\n+ * tile size in bytes covered by one entry in the status buffer and s is the\n+ * number of status bits per entry.\n+ * We reserve the top 8 bits of the Vivante modifier space for tile status\n+ * clear/compression modifiers, as future cores might add some more TS layout\n+ * variations.\n+ */\n+#define VIVANTE_MOD_TS_64_4 (1ULL << 48)\n+#define VIVANTE_MOD_TS_64_2 (2ULL << 48)\n+#define VIVANTE_MOD_TS_128_4 (3ULL << 48)\n+#define VIVANTE_MOD_TS_256_4 (4ULL << 48)\n+#define VIVANTE_MOD_TS_MASK (0xfULL << 48)\n+\n+/*\n+ * Vivante compression modifiers. Those depend on a TS modifier being present\n+ * as the TS bits get reinterpreted as compression tags instead of simple\n+ * clear markers when compression is enabled.\n+ */\n+#define VIVANTE_MOD_COMP_DEC400 (1ULL << 52)\n+#define VIVANTE_MOD_COMP_MASK (0xfULL << 52)\n+\n+/* Masking out the extension bits will yield the base modifier. */\n+#define VIVANTE_MOD_EXT_MASK (VIVANTE_MOD_TS_MASK | \\\n+ VIVANTE_MOD_COMP_MASK)\n+\n /* NVIDIA frame buffer modifiers */\n \n /*\n@@ -1440,6 +1550,7 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier)\n #define AMD_FMT_MOD_TILE_VER_GFX9 1\n #define AMD_FMT_MOD_TILE_VER_GFX10 2\n #define AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS 3\n+#define AMD_FMT_MOD_TILE_VER_GFX11 4\n \n /*\n * 64K_S is the same for GFX9/GFX10/GFX10_RBPLUS and hence has GFX9 as canonical\n@@ -1455,6 +1566,7 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier)\n #define AMD_FMT_MOD_TILE_GFX9_64K_S_X 25\n #define AMD_FMT_MOD_TILE_GFX9_64K_D_X 26\n #define AMD_FMT_MOD_TILE_GFX9_64K_R_X 27\n+#define AMD_FMT_MOD_TILE_GFX11_256K_R_X 31\n \n #define AMD_FMT_MOD_DCC_BLOCK_64B 0\n #define AMD_FMT_MOD_DCC_BLOCK_128B 1\ndiff --git a/include/linux/intel-ipu3.h b/include/linux/intel-ipu3.h\nindex 5c298ec557fa..bd771f1b4f6d 100644\n--- a/include/linux/intel-ipu3.h\n+++ b/include/linux/intel-ipu3.h\n@@ -626,8 +626,11 @@ struct ipu3_uapi_stats_3a {\n * @b:\twhite balance gain for B channel.\n * @gb:\twhite balance gain for Gb channel.\n *\n- * Precision u3.13, range [0, 8). White balance correction is done by applying\n- * a multiplicative gain to each color channels prior to BNR.\n+ * For BNR parameters WB gain factor for the three channels [Ggr, Ggb, Gb, Gr].\n+ * Their precision is U3.13 and the range is (0, 8) and the actual gain is\n+ * Gx + 1, it is typically Gx = 1.\n+ *\n+ * Pout = {Pin * (1 + Gx)}.\n */\n struct ipu3_uapi_bnr_static_config_wb_gains_config {\n \t__u16 gr;\ndiff --git a/include/linux/media-bus-format.h b/include/linux/media-bus-format.h\nindex 0dfc11ee243a..f05f747e444d 100644\n--- a/include/linux/media-bus-format.h\n+++ b/include/linux/media-bus-format.h\n@@ -34,7 +34,7 @@\n \n #define MEDIA_BUS_FMT_FIXED\t\t\t0x0001\n \n-/* RGB - next is\t0x101e */\n+/* RGB - next is\t0x1026 */\n #define MEDIA_BUS_FMT_RGB444_1X12\t\t0x1016\n #define MEDIA_BUS_FMT_RGB444_2X8_PADHI_BE\t0x1001\n #define MEDIA_BUS_FMT_RGB444_2X8_PADHI_LE\t0x1002\n@@ -46,8 +46,12 @@\n #define MEDIA_BUS_FMT_RGB565_2X8_BE\t\t0x1007\n #define MEDIA_BUS_FMT_RGB565_2X8_LE\t\t0x1008\n #define MEDIA_BUS_FMT_RGB666_1X18\t\t0x1009\n+#define MEDIA_BUS_FMT_RGB666_2X9_BE\t\t0x1025\n+#define MEDIA_BUS_FMT_BGR666_1X18\t\t0x1023\n #define MEDIA_BUS_FMT_RBG888_1X24\t\t0x100e\n #define MEDIA_BUS_FMT_RGB666_1X24_CPADHI\t0x1015\n+#define MEDIA_BUS_FMT_BGR666_1X24_CPADHI\t0x1024\n+#define MEDIA_BUS_FMT_RGB565_1X24_CPADHI\t0x1022\n #define MEDIA_BUS_FMT_RGB666_1X7X3_SPWG\t\t0x1010\n #define MEDIA_BUS_FMT_BGR888_1X24\t\t0x1013\n #define MEDIA_BUS_FMT_BGR888_3X8\t\t0x101b\n@@ -59,13 +63,17 @@\n #define MEDIA_BUS_FMT_RGB888_3X8_DELTA\t\t0x101d\n #define MEDIA_BUS_FMT_RGB888_1X7X4_SPWG\t\t0x1011\n #define MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA\t0x1012\n+#define MEDIA_BUS_FMT_RGB666_1X30_CPADLO\t0x101e\n+#define MEDIA_BUS_FMT_RGB888_1X30_CPADLO\t0x101f\n #define MEDIA_BUS_FMT_ARGB8888_1X32\t\t0x100d\n #define MEDIA_BUS_FMT_RGB888_1X32_PADHI\t\t0x100f\n #define MEDIA_BUS_FMT_RGB101010_1X30\t\t0x1018\n+#define MEDIA_BUS_FMT_RGB666_1X36_CPADLO\t0x1020\n+#define MEDIA_BUS_FMT_RGB888_1X36_CPADLO\t0x1021\n #define MEDIA_BUS_FMT_RGB121212_1X36\t\t0x1019\n #define MEDIA_BUS_FMT_RGB161616_1X48\t\t0x101a\n \n-/* YUV (including grey) - next is\t0x202e */\n+/* YUV (including grey) - next is\t0x202f */\n #define MEDIA_BUS_FMT_Y8_1X8\t\t\t0x2001\n #define MEDIA_BUS_FMT_UV8_1X8\t\t\t0x2015\n #define MEDIA_BUS_FMT_UYVY8_1_5X8\t\t0x2002\n@@ -88,6 +96,7 @@\n #define MEDIA_BUS_FMT_YUYV12_2X12\t\t0x201e\n #define MEDIA_BUS_FMT_YVYU12_2X12\t\t0x201f\n #define MEDIA_BUS_FMT_Y14_1X14\t\t\t0x202d\n+#define MEDIA_BUS_FMT_Y16_1X16\t\t\t0x202e\n #define MEDIA_BUS_FMT_UYVY8_1X16\t\t0x200f\n #define MEDIA_BUS_FMT_VYUY8_1X16\t\t0x2010\n #define MEDIA_BUS_FMT_YUYV8_1X16\t\t0x2011\ndiff --git a/include/linux/media.h b/include/linux/media.h\nindex e3123d1aa4ed..b5a77bbf4062 100644\n--- a/include/linux/media.h\n+++ b/include/linux/media.h\n@@ -20,7 +20,6 @@\n #ifndef __LINUX_MEDIA_H\n #define __LINUX_MEDIA_H\n \n-#include \n #include \n #include \n \n@@ -141,8 +140,8 @@ struct media_device_info {\n #define MEDIA_ENT_F_DV_ENCODER\t\t\t(MEDIA_ENT_F_BASE + 0x6002)\n \n /* Entity flags */\n-#define MEDIA_ENT_FL_DEFAULT\t\t\t(1 << 0)\n-#define MEDIA_ENT_FL_CONNECTOR\t\t\t(1 << 1)\n+#define MEDIA_ENT_FL_DEFAULT\t\t\t(1U << 0)\n+#define MEDIA_ENT_FL_CONNECTOR\t\t\t(1U << 1)\n \n /* OR with the entity id value to find the next entity */\n #define MEDIA_ENT_ID_FLAG_NEXT\t\t\t(1U << 31)\n@@ -204,9 +203,9 @@ struct media_entity_desc {\n \t};\n };\n \n-#define MEDIA_PAD_FL_SINK\t\t\t(1 << 0)\n-#define MEDIA_PAD_FL_SOURCE\t\t\t(1 << 1)\n-#define MEDIA_PAD_FL_MUST_CONNECT\t\t(1 << 2)\n+#define MEDIA_PAD_FL_SINK\t\t\t(1U << 0)\n+#define MEDIA_PAD_FL_SOURCE\t\t\t(1U << 1)\n+#define MEDIA_PAD_FL_MUST_CONNECT\t\t(1U << 2)\n \n struct media_pad_desc {\n \t__u32 entity;\t\t/* entity ID */\n@@ -215,14 +214,14 @@ struct media_pad_desc {\n \t__u32 reserved[2];\n };\n \n-#define MEDIA_LNK_FL_ENABLED\t\t\t(1 << 0)\n-#define MEDIA_LNK_FL_IMMUTABLE\t\t\t(1 << 1)\n-#define MEDIA_LNK_FL_DYNAMIC\t\t\t(1 << 2)\n+#define MEDIA_LNK_FL_ENABLED\t\t\t(1U << 0)\n+#define MEDIA_LNK_FL_IMMUTABLE\t\t\t(1U << 1)\n+#define MEDIA_LNK_FL_DYNAMIC\t\t\t(1U << 2)\n \n #define MEDIA_LNK_FL_LINK_TYPE\t\t\t(0xf << 28)\n-# define MEDIA_LNK_FL_DATA_LINK\t\t(0 << 28)\n-# define MEDIA_LNK_FL_INTERFACE_LINK\t\t(1 << 28)\n-# define MEDIA_LNK_FL_ANCILLARY_LINK\t\t(2 << 28)\n+# define MEDIA_LNK_FL_DATA_LINK\t\t(0U << 28)\n+# define MEDIA_LNK_FL_INTERFACE_LINK\t\t(1U << 28)\n+# define MEDIA_LNK_FL_ANCILLARY_LINK\t\t(2U << 28)\n \n struct media_link_desc {\n \tstruct media_pad_desc source;\n@@ -277,7 +276,7 @@ struct media_links_enum {\n * struct media_device_info.\n */\n #define MEDIA_V2_ENTITY_HAS_FLAGS(media_version) \\\n-\t((media_version) >= ((4 << 16) | (19 << 8) | 0))\n+\t((media_version) >= ((4U << 16) | (19U << 8) | 0U))\n \n struct media_v2_entity {\n \t__u32 id;\n@@ -312,7 +311,7 @@ struct media_v2_interface {\n * struct media_device_info.\n */\n #define MEDIA_V2_PAD_HAS_INDEX(media_version) \\\n-\t((media_version) >= ((4 << 16) | (19 << 8) | 0))\n+\t((media_version) >= ((4U << 16) | (19U << 8) | 0U))\n \n struct media_v2_pad {\n \t__u32 id;\n@@ -415,7 +414,7 @@ struct media_v2_topology {\n #define MEDIA_INTF_T_ALSA_TIMER (MEDIA_INTF_T_ALSA_BASE + 7)\n \n /* Obsolete symbol for media_version, no longer used in the kernel */\n-#define MEDIA_API_VERSION\t\t\t((0 << 16) | (1 << 8) | 0)\n+#define MEDIA_API_VERSION\t\t\t((0U << 16) | (1U << 8) | 0U)\n \n \n #endif /* __LINUX_MEDIA_H */\ndiff --git a/include/linux/v4l2-common.h b/include/linux/v4l2-common.h\nindex 14de1731b39c..c3ca11e3e2e0 100644\n--- a/include/linux/v4l2-common.h\n+++ b/include/linux/v4l2-common.h\n@@ -10,45 +10,6 @@\n *\n * Copyright (C) 2012 Nokia Corporation\n * Contact: Sakari Ailus \n- *\n- * This program is free software; you can redistribute it and/or modify\n- * it under the terms of the GNU General Public License as published by\n- * the Free Software Foundation; either version 2 of the License, or\n- * (at your option) any later version.\n- *\n- * This program is distributed in the hope that it will be useful,\n- * but WITHOUT ANY WARRANTY; without even the implied warranty of\n- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n- * GNU General Public License for more details.\n- *\n- * Alternatively you can redistribute this file under the terms of the\n- * BSD license as stated below:\n- *\n- * Redistribution and use in source and binary forms, with or without\n- * modification, are permitted provided that the following conditions\n- * are met:\n- * 1. Redistributions of source code must retain the above copyright\n- * notice, this list of conditions and the following disclaimer.\n- * 2. Redistributions in binary form must reproduce the above copyright\n- * notice, this list of conditions and the following disclaimer in\n- * the documentation and/or other materials provided with the\n- * distribution.\n- * 3. The names of its contributors may not be used to endorse or promote\n- * products derived from this software without specific prior written\n- * permission.\n- *\n- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n- * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED\n- * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR\n- * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\n- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\n- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n- *\n */\n \n #ifndef __V4L2_COMMON__\ndiff --git a/include/linux/v4l2-controls.h b/include/linux/v4l2-controls.h\nindex 9d2a8237e712..b9f6481092c7 100644\n--- a/include/linux/v4l2-controls.h\n+++ b/include/linux/v4l2-controls.h\n@@ -4,44 +4,6 @@\n *\n * Copyright (C) 1999-2012 the contributors\n *\n- * This program is free software; you can redistribute it and/or modify\n- * it under the terms of the GNU General Public License as published by\n- * the Free Software Foundation; either version 2 of the License, or\n- * (at your option) any later version.\n- *\n- * This program is distributed in the hope that it will be useful,\n- * but WITHOUT ANY WARRANTY; without even the implied warranty of\n- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n- * GNU General Public License for more details.\n- *\n- * Alternatively you can redistribute this file under the terms of the\n- * BSD license as stated below:\n- *\n- * Redistribution and use in source and binary forms, with or without\n- * modification, are permitted provided that the following conditions\n- * are met:\n- * 1. Redistributions of source code must retain the above copyright\n- * notice, this list of conditions and the following disclaimer.\n- * 2. Redistributions in binary form must reproduce the above copyright\n- * notice, this list of conditions and the following disclaimer in\n- * the documentation and/or other materials provided with the\n- * distribution.\n- * 3. The names of its contributors may not be used to endorse or promote\n- * products derived from this software without specific prior written\n- * permission.\n- *\n- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n- * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED\n- * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR\n- * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\n- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\n- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n- *\n * The contents of this header was split off from videodev2.h. All control\n * definitions should be added to this header, which is included by\n * videodev2.h.\n@@ -153,8 +115,10 @@ enum v4l2_colorfx {\n \n /* USER-class private control IDs */\n \n-/* The base for the meye driver controls. See linux/meye.h for the list\n- * of controls. We reserve 16 controls for this driver. */\n+/*\n+ * The base for the meye driver controls. This driver was removed, but\n+ * we keep this define in case any software still uses it.\n+ */\n #define V4L2_CID_USER_MEYE_BASE\t\t\t(V4L2_CID_USER_BASE + 0x1000)\n \n /* The base for the bttv driver controls.\n@@ -229,6 +193,24 @@ enum v4l2_colorfx {\n */\n #define V4L2_CID_USER_ISL7998X_BASE\t\t(V4L2_CID_USER_BASE + 0x1180)\n \n+/*\n+ * The base for DW100 driver controls.\n+ * We reserve 16 controls for this driver.\n+ */\n+#define V4L2_CID_USER_DW100_BASE\t\t(V4L2_CID_USER_BASE + 0x1190)\n+\n+/*\n+ * The base for Aspeed driver controls.\n+ * We reserve 16 controls for this driver.\n+ */\n+#define V4L2_CID_USER_ASPEED_BASE\t\t(V4L2_CID_USER_BASE + 0x11a0)\n+\n+/*\n+ * The base for Nuvoton NPCM driver controls.\n+ * We reserve 16 controls for this driver.\n+ */\n+#define V4L2_CID_USER_NPCM_BASE\t\t\t(V4L2_CID_USER_BASE + 0x11b0)\n+\n /* MPEG-class control IDs */\n /* The MPEG controls are applicable to all codec controls\n * and the 'MPEG' part of the define is historical */\n@@ -828,6 +810,88 @@ enum v4l2_mpeg_video_frame_skip_mode {\n #define V4L2_CID_MPEG_VIDEO_DEC_DISPLAY_DELAY\t\t(V4L2_CID_CODEC_BASE + 653)\n #define V4L2_CID_MPEG_VIDEO_DEC_DISPLAY_DELAY_ENABLE\t(V4L2_CID_CODEC_BASE + 654)\n \n+#define V4L2_CID_MPEG_VIDEO_AV1_PROFILE (V4L2_CID_CODEC_BASE + 655)\n+/**\n+ * enum v4l2_mpeg_video_av1_profile - AV1 profiles\n+ *\n+ * @V4L2_MPEG_VIDEO_AV1_PROFILE_MAIN: compliant decoders must be able to decode\n+ * streams with seq_profile equal to 0.\n+ * @V4L2_MPEG_VIDEO_AV1_PROFILE_HIGH: compliant decoders must be able to decode\n+ * streams with seq_profile equal less than or equal to 1.\n+ * @V4L2_MPEG_VIDEO_AV1_PROFILE_PROFESSIONAL: compliant decoders must be able to\n+ * decode streams with seq_profile less than or equal to 2.\n+ *\n+ * Conveys the highest profile a decoder can work with.\n+ */\n+enum v4l2_mpeg_video_av1_profile {\n+\tV4L2_MPEG_VIDEO_AV1_PROFILE_MAIN = 0,\n+\tV4L2_MPEG_VIDEO_AV1_PROFILE_HIGH = 1,\n+\tV4L2_MPEG_VIDEO_AV1_PROFILE_PROFESSIONAL = 2,\n+};\n+\n+#define V4L2_CID_MPEG_VIDEO_AV1_LEVEL (V4L2_CID_CODEC_BASE + 656)\n+/**\n+ * enum v4l2_mpeg_video_av1_level - AV1 levels\n+ *\n+ * @V4L2_MPEG_VIDEO_AV1_LEVEL_2_0: Level 2.0.\n+ * @V4L2_MPEG_VIDEO_AV1_LEVEL_2_1: Level 2.1.\n+ * @V4L2_MPEG_VIDEO_AV1_LEVEL_2_2: Level 2.2.\n+ * @V4L2_MPEG_VIDEO_AV1_LEVEL_2_3: Level 2.3.\n+ * @V4L2_MPEG_VIDEO_AV1_LEVEL_3_0: Level 3.0.\n+ * @V4L2_MPEG_VIDEO_AV1_LEVEL_3_1: Level 3.1.\n+ * @V4L2_MPEG_VIDEO_AV1_LEVEL_3_2: Level 3.2.\n+ * @V4L2_MPEG_VIDEO_AV1_LEVEL_3_3: Level 3.3.\n+ * @V4L2_MPEG_VIDEO_AV1_LEVEL_4_0: Level 4.0.\n+ * @V4L2_MPEG_VIDEO_AV1_LEVEL_4_1: Level 4.1.\n+ * @V4L2_MPEG_VIDEO_AV1_LEVEL_4_2: Level 4.2.\n+ * @V4L2_MPEG_VIDEO_AV1_LEVEL_4_3: Level 4.3.\n+ * @V4L2_MPEG_VIDEO_AV1_LEVEL_5_0: Level 5.0.\n+ * @V4L2_MPEG_VIDEO_AV1_LEVEL_5_1: Level 5.1.\n+ * @V4L2_MPEG_VIDEO_AV1_LEVEL_5_2: Level 5.2.\n+ * @V4L2_MPEG_VIDEO_AV1_LEVEL_5_3: Level 5.3.\n+ * @V4L2_MPEG_VIDEO_AV1_LEVEL_6_0: Level 6.0.\n+ * @V4L2_MPEG_VIDEO_AV1_LEVEL_6_1: Level 6.1.\n+ * @V4L2_MPEG_VIDEO_AV1_LEVEL_6_2: Level 6.2.\n+ * @V4L2_MPEG_VIDEO_AV1_LEVEL_6_3: Level 6.3.\n+ * @V4L2_MPEG_VIDEO_AV1_LEVEL_7_0: Level 7.0.\n+ * @V4L2_MPEG_VIDEO_AV1_LEVEL_7_1: Level 7.1.\n+ * @V4L2_MPEG_VIDEO_AV1_LEVEL_7_2: Level 7.2.\n+ * @V4L2_MPEG_VIDEO_AV1_LEVEL_7_3: Level 7.3.\n+ *\n+ * Conveys the highest level a decoder can work with.\n+ */\n+enum v4l2_mpeg_video_av1_level {\n+\tV4L2_MPEG_VIDEO_AV1_LEVEL_2_0 = 0,\n+\tV4L2_MPEG_VIDEO_AV1_LEVEL_2_1 = 1,\n+\tV4L2_MPEG_VIDEO_AV1_LEVEL_2_2 = 2,\n+\tV4L2_MPEG_VIDEO_AV1_LEVEL_2_3 = 3,\n+\n+\tV4L2_MPEG_VIDEO_AV1_LEVEL_3_0 = 4,\n+\tV4L2_MPEG_VIDEO_AV1_LEVEL_3_1 = 5,\n+\tV4L2_MPEG_VIDEO_AV1_LEVEL_3_2 = 6,\n+\tV4L2_MPEG_VIDEO_AV1_LEVEL_3_3 = 7,\n+\n+\tV4L2_MPEG_VIDEO_AV1_LEVEL_4_0 = 8,\n+\tV4L2_MPEG_VIDEO_AV1_LEVEL_4_1 = 9,\n+\tV4L2_MPEG_VIDEO_AV1_LEVEL_4_2 = 10,\n+\tV4L2_MPEG_VIDEO_AV1_LEVEL_4_3 = 11,\n+\n+\tV4L2_MPEG_VIDEO_AV1_LEVEL_5_0 = 12,\n+\tV4L2_MPEG_VIDEO_AV1_LEVEL_5_1 = 13,\n+\tV4L2_MPEG_VIDEO_AV1_LEVEL_5_2 = 14,\n+\tV4L2_MPEG_VIDEO_AV1_LEVEL_5_3 = 15,\n+\n+\tV4L2_MPEG_VIDEO_AV1_LEVEL_6_0 = 16,\n+\tV4L2_MPEG_VIDEO_AV1_LEVEL_6_1 = 17,\n+\tV4L2_MPEG_VIDEO_AV1_LEVEL_6_2 = 18,\n+\tV4L2_MPEG_VIDEO_AV1_LEVEL_6_3 = 19,\n+\n+\tV4L2_MPEG_VIDEO_AV1_LEVEL_7_0 = 20,\n+\tV4L2_MPEG_VIDEO_AV1_LEVEL_7_1 = 21,\n+\tV4L2_MPEG_VIDEO_AV1_LEVEL_7_2 = 22,\n+\tV4L2_MPEG_VIDEO_AV1_LEVEL_7_3 = 23\n+};\n+\n /* MPEG-class control IDs specific to the CX2341x driver as defined by V4L2 */\n #define V4L2_CID_CODEC_CX2341X_BASE\t\t\t\t(V4L2_CTRL_CLASS_CODEC | 0x1000)\n #define V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE\t\t(V4L2_CID_CODEC_CX2341X_BASE+0)\n@@ -1015,6 +1079,8 @@ enum v4l2_auto_focus_range {\n \n #define V4L2_CID_CAMERA_SENSOR_ROTATION\t\t(V4L2_CID_CAMERA_CLASS_BASE+35)\n \n+#define V4L2_CID_HDR_SENSOR_MODE\t\t(V4L2_CID_CAMERA_CLASS_BASE+36)\n+\n /* FM Modulator class control IDs */\n \n #define V4L2_CID_FM_TX_CLASS_BASE\t\t(V4L2_CTRL_CLASS_FM_TX | 0x900)\n@@ -1732,7 +1798,7 @@ struct v4l2_vp8_segment {\n * @sharpness_level: matches sharpness_level syntax element.\n * @level: matches loop_filter_level syntax element.\n * @padding: padding field. Should be zeroed by applications.\n- * @flags: see V4L2_VP8_LF_FLAG_{}.\n+ * @flags: see V4L2_VP8_LF_{}.\n *\n * This structure contains loop filter related parameters.\n * See the 'mb_lf_adjustments()' part of the frame header syntax,\n@@ -1999,6 +2065,469 @@ struct v4l2_ctrl_mpeg2_quantisation {\n \t__u8\tchroma_non_intra_quantiser_matrix[64];\n };\n \n+#define V4L2_CID_STATELESS_HEVC_SPS\t\t(V4L2_CID_CODEC_STATELESS_BASE + 400)\n+#define V4L2_CID_STATELESS_HEVC_PPS\t\t(V4L2_CID_CODEC_STATELESS_BASE + 401)\n+#define V4L2_CID_STATELESS_HEVC_SLICE_PARAMS\t(V4L2_CID_CODEC_STATELESS_BASE + 402)\n+#define V4L2_CID_STATELESS_HEVC_SCALING_MATRIX\t(V4L2_CID_CODEC_STATELESS_BASE + 403)\n+#define V4L2_CID_STATELESS_HEVC_DECODE_PARAMS\t(V4L2_CID_CODEC_STATELESS_BASE + 404)\n+#define V4L2_CID_STATELESS_HEVC_DECODE_MODE\t(V4L2_CID_CODEC_STATELESS_BASE + 405)\n+#define V4L2_CID_STATELESS_HEVC_START_CODE\t(V4L2_CID_CODEC_STATELESS_BASE + 406)\n+#define V4L2_CID_STATELESS_HEVC_ENTRY_POINT_OFFSETS (V4L2_CID_CODEC_STATELESS_BASE + 407)\n+\n+enum v4l2_stateless_hevc_decode_mode {\n+\tV4L2_STATELESS_HEVC_DECODE_MODE_SLICE_BASED,\n+\tV4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED,\n+};\n+\n+enum v4l2_stateless_hevc_start_code {\n+\tV4L2_STATELESS_HEVC_START_CODE_NONE,\n+\tV4L2_STATELESS_HEVC_START_CODE_ANNEX_B,\n+};\n+\n+#define V4L2_HEVC_SLICE_TYPE_B\t0\n+#define V4L2_HEVC_SLICE_TYPE_P\t1\n+#define V4L2_HEVC_SLICE_TYPE_I\t2\n+\n+#define V4L2_HEVC_SPS_FLAG_SEPARATE_COLOUR_PLANE\t\t(1ULL << 0)\n+#define V4L2_HEVC_SPS_FLAG_SCALING_LIST_ENABLED\t\t\t(1ULL << 1)\n+#define V4L2_HEVC_SPS_FLAG_AMP_ENABLED\t\t\t\t(1ULL << 2)\n+#define V4L2_HEVC_SPS_FLAG_SAMPLE_ADAPTIVE_OFFSET\t\t(1ULL << 3)\n+#define V4L2_HEVC_SPS_FLAG_PCM_ENABLED\t\t\t\t(1ULL << 4)\n+#define V4L2_HEVC_SPS_FLAG_PCM_LOOP_FILTER_DISABLED\t\t(1ULL << 5)\n+#define V4L2_HEVC_SPS_FLAG_LONG_TERM_REF_PICS_PRESENT\t\t(1ULL << 6)\n+#define V4L2_HEVC_SPS_FLAG_SPS_TEMPORAL_MVP_ENABLED\t\t(1ULL << 7)\n+#define V4L2_HEVC_SPS_FLAG_STRONG_INTRA_SMOOTHING_ENABLED\t(1ULL << 8)\n+\n+/**\n+ * struct v4l2_ctrl_hevc_sps - ITU-T Rec. H.265: Sequence parameter set\n+ *\n+ * @video_parameter_set_id: specifies the value of the\n+ *\t\t\tvps_video_parameter_set_id of the active VPS\n+ * @seq_parameter_set_id: provides an identifier for the SPS for\n+ *\t\t\t reference by other syntax elements\n+ * @pic_width_in_luma_samples:\tspecifies the width of each decoded picture\n+ *\t\t\t\tin units of luma samples\n+ * @pic_height_in_luma_samples: specifies the height of each decoded picture\n+ *\t\t\t\tin units of luma samples\n+ * @bit_depth_luma_minus8: this value plus 8specifies the bit depth of the\n+ * samples of the luma array\n+ * @bit_depth_chroma_minus8: this value plus 8 specifies the bit depth of the\n+ * samples of the chroma arrays\n+ * @log2_max_pic_order_cnt_lsb_minus4: this value plus 4 specifies the value of\n+ * the variable MaxPicOrderCntLsb\n+ * @sps_max_dec_pic_buffering_minus1: this value plus 1 specifies the maximum\n+ * required size of the decoded picture\n+ * buffer for the codec video sequence\n+ * @sps_max_num_reorder_pics: indicates the maximum allowed number of pictures\n+ * @sps_max_latency_increase_plus1: not equal to 0 is used to compute the\n+ *\t\t\t\t value of SpsMaxLatencyPictures array\n+ * @log2_min_luma_coding_block_size_minus3: plus 3 specifies the minimum\n+ *\t\t\t\t\t luma coding block size\n+ * @log2_diff_max_min_luma_coding_block_size: specifies the difference between\n+ *\t\t\t\t\t the maximum and minimum luma\n+ *\t\t\t\t\t coding block size\n+ * @log2_min_luma_transform_block_size_minus2: plus 2 specifies the minimum luma\n+ *\t\t\t\t\t transform block size\n+ * @log2_diff_max_min_luma_transform_block_size: specifies the difference between\n+ *\t\t\t\t\t\t the maximum and minimum luma\n+ *\t\t\t\t\t\t transform block size\n+ * @max_transform_hierarchy_depth_inter: specifies the maximum hierarchy\n+ *\t\t\t\t\t depth for transform units of\n+ *\t\t\t\t\t coding units coded in inter\n+ *\t\t\t\t\t prediction mode\n+ * @max_transform_hierarchy_depth_intra: specifies the maximum hierarchy\n+ *\t\t\t\t\t depth for transform units of\n+ *\t\t\t\t\t coding units coded in intra\n+ *\t\t\t\t\t prediction mode\n+ * @pcm_sample_bit_depth_luma_minus1: this value plus 1 specifies the number of\n+ * bits used to represent each of PCM sample\n+ * values of the luma component\n+ * @pcm_sample_bit_depth_chroma_minus1: this value plus 1 specifies the number\n+ * of bits used to represent each of PCM\n+ * sample values of the chroma components\n+ * @log2_min_pcm_luma_coding_block_size_minus3: this value plus 3 specifies the\n+ * minimum size of coding blocks\n+ * @log2_diff_max_min_pcm_luma_coding_block_size: specifies the difference between\n+ *\t\t\t\t\t\t the maximum and minimum size of\n+ *\t\t\t\t\t\t coding blocks\n+ * @num_short_term_ref_pic_sets: specifies the number of st_ref_pic_set()\n+ *\t\t\t\t syntax structures included in the SPS\n+ * @num_long_term_ref_pics_sps: specifies the number of candidate long-term\n+ *\t\t\t\treference pictures that are specified in the SPS\n+ * @chroma_format_idc: specifies the chroma sampling\n+ * @sps_max_sub_layers_minus1: this value plus 1 specifies the maximum number\n+ * of temporal sub-layers\n+ * @reserved: padding field. Should be zeroed by applications.\n+ * @flags: see V4L2_HEVC_SPS_FLAG_{}\n+ */\n+struct v4l2_ctrl_hevc_sps {\n+\t__u8\tvideo_parameter_set_id;\n+\t__u8\tseq_parameter_set_id;\n+\t__u16\tpic_width_in_luma_samples;\n+\t__u16\tpic_height_in_luma_samples;\n+\t__u8\tbit_depth_luma_minus8;\n+\t__u8\tbit_depth_chroma_minus8;\n+\t__u8\tlog2_max_pic_order_cnt_lsb_minus4;\n+\t__u8\tsps_max_dec_pic_buffering_minus1;\n+\t__u8\tsps_max_num_reorder_pics;\n+\t__u8\tsps_max_latency_increase_plus1;\n+\t__u8\tlog2_min_luma_coding_block_size_minus3;\n+\t__u8\tlog2_diff_max_min_luma_coding_block_size;\n+\t__u8\tlog2_min_luma_transform_block_size_minus2;\n+\t__u8\tlog2_diff_max_min_luma_transform_block_size;\n+\t__u8\tmax_transform_hierarchy_depth_inter;\n+\t__u8\tmax_transform_hierarchy_depth_intra;\n+\t__u8\tpcm_sample_bit_depth_luma_minus1;\n+\t__u8\tpcm_sample_bit_depth_chroma_minus1;\n+\t__u8\tlog2_min_pcm_luma_coding_block_size_minus3;\n+\t__u8\tlog2_diff_max_min_pcm_luma_coding_block_size;\n+\t__u8\tnum_short_term_ref_pic_sets;\n+\t__u8\tnum_long_term_ref_pics_sps;\n+\t__u8\tchroma_format_idc;\n+\t__u8\tsps_max_sub_layers_minus1;\n+\n+\t__u8\treserved[6];\n+\t__u64\tflags;\n+};\n+\n+#define V4L2_HEVC_PPS_FLAG_DEPENDENT_SLICE_SEGMENT_ENABLED\t(1ULL << 0)\n+#define V4L2_HEVC_PPS_FLAG_OUTPUT_FLAG_PRESENT\t\t\t(1ULL << 1)\n+#define V4L2_HEVC_PPS_FLAG_SIGN_DATA_HIDING_ENABLED\t\t(1ULL << 2)\n+#define V4L2_HEVC_PPS_FLAG_CABAC_INIT_PRESENT\t\t\t(1ULL << 3)\n+#define V4L2_HEVC_PPS_FLAG_CONSTRAINED_INTRA_PRED\t\t(1ULL << 4)\n+#define V4L2_HEVC_PPS_FLAG_TRANSFORM_SKIP_ENABLED\t\t(1ULL << 5)\n+#define V4L2_HEVC_PPS_FLAG_CU_QP_DELTA_ENABLED\t\t\t(1ULL << 6)\n+#define V4L2_HEVC_PPS_FLAG_PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT\t(1ULL << 7)\n+#define V4L2_HEVC_PPS_FLAG_WEIGHTED_PRED\t\t\t(1ULL << 8)\n+#define V4L2_HEVC_PPS_FLAG_WEIGHTED_BIPRED\t\t\t(1ULL << 9)\n+#define V4L2_HEVC_PPS_FLAG_TRANSQUANT_BYPASS_ENABLED\t\t(1ULL << 10)\n+#define V4L2_HEVC_PPS_FLAG_TILES_ENABLED\t\t\t(1ULL << 11)\n+#define V4L2_HEVC_PPS_FLAG_ENTROPY_CODING_SYNC_ENABLED\t\t(1ULL << 12)\n+#define V4L2_HEVC_PPS_FLAG_LOOP_FILTER_ACROSS_TILES_ENABLED\t(1ULL << 13)\n+#define V4L2_HEVC_PPS_FLAG_PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED (1ULL << 14)\n+#define V4L2_HEVC_PPS_FLAG_DEBLOCKING_FILTER_OVERRIDE_ENABLED\t(1ULL << 15)\n+#define V4L2_HEVC_PPS_FLAG_PPS_DISABLE_DEBLOCKING_FILTER\t(1ULL << 16)\n+#define V4L2_HEVC_PPS_FLAG_LISTS_MODIFICATION_PRESENT\t\t(1ULL << 17)\n+#define V4L2_HEVC_PPS_FLAG_SLICE_SEGMENT_HEADER_EXTENSION_PRESENT (1ULL << 18)\n+#define V4L2_HEVC_PPS_FLAG_DEBLOCKING_FILTER_CONTROL_PRESENT\t(1ULL << 19)\n+#define V4L2_HEVC_PPS_FLAG_UNIFORM_SPACING\t\t\t(1ULL << 20)\n+\n+/**\n+ * struct v4l2_ctrl_hevc_pps - ITU-T Rec. H.265: Picture parameter set\n+ *\n+ * @pic_parameter_set_id: identifies the PPS for reference by other\n+ *\t\t\t syntax elements\n+ * @num_extra_slice_header_bits: specifies the number of extra slice header\n+ *\t\t\t\t bits that are present in the slice header RBSP\n+ *\t\t\t\t for coded pictures referring to the PPS.\n+ * @num_ref_idx_l0_default_active_minus1: this value plus 1 specifies the\n+ * inferred value of num_ref_idx_l0_active_minus1\n+ * @num_ref_idx_l1_default_active_minus1: this value plus 1 specifies the\n+ * inferred value of num_ref_idx_l1_active_minus1\n+ * @init_qp_minus26: this value plus 26 specifies the initial value of SliceQp Y for\n+ *\t\t each slice referring to the PPS\n+ * @diff_cu_qp_delta_depth: specifies the difference between the luma coding\n+ *\t\t\t tree block size and the minimum luma coding block\n+ *\t\t\t size of coding units that convey cu_qp_delta_abs\n+ *\t\t\t and cu_qp_delta_sign_flag\n+ * @pps_cb_qp_offset: specify the offsets to the luma quantization parameter Cb\n+ * @pps_cr_qp_offset: specify the offsets to the luma quantization parameter Cr\n+ * @num_tile_columns_minus1: this value plus 1 specifies the number of tile columns\n+ *\t\t\t partitioning the picture\n+ * @num_tile_rows_minus1: this value plus 1 specifies the number of tile rows partitioning\n+ *\t\t\t the picture\n+ * @column_width_minus1: this value plus 1 specifies the width of the each tile column in\n+ *\t\t\t units of coding tree blocks\n+ * @row_height_minus1: this value plus 1 specifies the height of the each tile row in\n+ *\t\t units of coding tree blocks\n+ * @pps_beta_offset_div2: specify the default deblocking parameter offsets for\n+ *\t\t\t beta divided by 2\n+ * @pps_tc_offset_div2: specify the default deblocking parameter offsets for tC\n+ *\t\t\tdivided by 2\n+ * @log2_parallel_merge_level_minus2: this value plus 2 specifies the value of\n+ * the variable Log2ParMrgLevel\n+ * @reserved: padding field. Should be zeroed by applications.\n+ * @flags: see V4L2_HEVC_PPS_FLAG_{}\n+ */\n+struct v4l2_ctrl_hevc_pps {\n+\t__u8\tpic_parameter_set_id;\n+\t__u8\tnum_extra_slice_header_bits;\n+\t__u8\tnum_ref_idx_l0_default_active_minus1;\n+\t__u8\tnum_ref_idx_l1_default_active_minus1;\n+\t__s8\tinit_qp_minus26;\n+\t__u8\tdiff_cu_qp_delta_depth;\n+\t__s8\tpps_cb_qp_offset;\n+\t__s8\tpps_cr_qp_offset;\n+\t__u8\tnum_tile_columns_minus1;\n+\t__u8\tnum_tile_rows_minus1;\n+\t__u8\tcolumn_width_minus1[20];\n+\t__u8\trow_height_minus1[22];\n+\t__s8\tpps_beta_offset_div2;\n+\t__s8\tpps_tc_offset_div2;\n+\t__u8\tlog2_parallel_merge_level_minus2;\n+\t__u8\treserved;\n+\t__u64\tflags;\n+};\n+\n+#define V4L2_HEVC_DPB_ENTRY_LONG_TERM_REFERENCE\t0x01\n+\n+#define V4L2_HEVC_SEI_PIC_STRUCT_FRAME\t\t\t\t0\n+#define V4L2_HEVC_SEI_PIC_STRUCT_TOP_FIELD\t\t\t1\n+#define V4L2_HEVC_SEI_PIC_STRUCT_BOTTOM_FIELD\t\t\t2\n+#define V4L2_HEVC_SEI_PIC_STRUCT_TOP_BOTTOM\t\t\t3\n+#define V4L2_HEVC_SEI_PIC_STRUCT_BOTTOM_TOP\t\t\t4\n+#define V4L2_HEVC_SEI_PIC_STRUCT_TOP_BOTTOM_TOP\t\t\t5\n+#define V4L2_HEVC_SEI_PIC_STRUCT_BOTTOM_TOP_BOTTOM\t\t6\n+#define V4L2_HEVC_SEI_PIC_STRUCT_FRAME_DOUBLING\t\t\t7\n+#define V4L2_HEVC_SEI_PIC_STRUCT_FRAME_TRIPLING\t\t\t8\n+#define V4L2_HEVC_SEI_PIC_STRUCT_TOP_PAIRED_PREVIOUS_BOTTOM\t9\n+#define V4L2_HEVC_SEI_PIC_STRUCT_BOTTOM_PAIRED_PREVIOUS_TOP\t10\n+#define V4L2_HEVC_SEI_PIC_STRUCT_TOP_PAIRED_NEXT_BOTTOM\t\t11\n+#define V4L2_HEVC_SEI_PIC_STRUCT_BOTTOM_PAIRED_NEXT_TOP\t\t12\n+\n+#define V4L2_HEVC_DPB_ENTRIES_NUM_MAX\t\t16\n+\n+/**\n+ * struct v4l2_hevc_dpb_entry - HEVC decoded picture buffer entry\n+ *\n+ * @timestamp: timestamp of the V4L2 capture buffer to use as reference.\n+ * @flags: long term flag for the reference frame\n+ * @field_pic: whether the reference is a field picture or a frame.\n+ * @reserved: padding field. Should be zeroed by applications.\n+ * @pic_order_cnt_val: the picture order count of the current picture.\n+ */\n+struct v4l2_hevc_dpb_entry {\n+\t__u64\ttimestamp;\n+\t__u8\tflags;\n+\t__u8\tfield_pic;\n+\t__u16\treserved;\n+\t__s32\tpic_order_cnt_val;\n+};\n+\n+/**\n+ * struct v4l2_hevc_pred_weight_table - HEVC weighted prediction parameters\n+ *\n+ * @delta_luma_weight_l0: the difference of the weighting factor applied\n+ *\t\t\t to the luma prediction value for list 0\n+ * @luma_offset_l0: the additive offset applied to the luma prediction value\n+ *\t\t for list 0\n+ * @delta_chroma_weight_l0: the difference of the weighting factor applied\n+ *\t\t\t to the chroma prediction values for list 0\n+ * @chroma_offset_l0: the difference of the additive offset applied to\n+ *\t\t the chroma prediction values for list 0\n+ * @delta_luma_weight_l1: the difference of the weighting factor applied\n+ *\t\t\t to the luma prediction value for list 1\n+ * @luma_offset_l1: the additive offset applied to the luma prediction value\n+ *\t\t for list 1\n+ * @delta_chroma_weight_l1: the difference of the weighting factor applied\n+ *\t\t\t to the chroma prediction values for list 1\n+ * @chroma_offset_l1: the difference of the additive offset applied to\n+ *\t\t the chroma prediction values for list 1\n+ * @luma_log2_weight_denom: the base 2 logarithm of the denominator for\n+ *\t\t\t all luma weighting factors\n+ * @delta_chroma_log2_weight_denom: the difference of the base 2 logarithm\n+ *\t\t\t\t of the denominator for all chroma\n+ *\t\t\t\t weighting factors\n+ */\n+struct v4l2_hevc_pred_weight_table {\n+\t__s8\tdelta_luma_weight_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX];\n+\t__s8\tluma_offset_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX];\n+\t__s8\tdelta_chroma_weight_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX][2];\n+\t__s8\tchroma_offset_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX][2];\n+\n+\t__s8\tdelta_luma_weight_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX];\n+\t__s8\tluma_offset_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX];\n+\t__s8\tdelta_chroma_weight_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX][2];\n+\t__s8\tchroma_offset_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX][2];\n+\n+\t__u8\tluma_log2_weight_denom;\n+\t__s8\tdelta_chroma_log2_weight_denom;\n+};\n+\n+#define V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_SAO_LUMA\t\t(1ULL << 0)\n+#define V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_SAO_CHROMA\t\t(1ULL << 1)\n+#define V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_TEMPORAL_MVP_ENABLED\t(1ULL << 2)\n+#define V4L2_HEVC_SLICE_PARAMS_FLAG_MVD_L1_ZERO\t\t\t(1ULL << 3)\n+#define V4L2_HEVC_SLICE_PARAMS_FLAG_CABAC_INIT\t\t\t(1ULL << 4)\n+#define V4L2_HEVC_SLICE_PARAMS_FLAG_COLLOCATED_FROM_L0\t\t(1ULL << 5)\n+#define V4L2_HEVC_SLICE_PARAMS_FLAG_USE_INTEGER_MV\t\t(1ULL << 6)\n+#define V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_DEBLOCKING_FILTER_DISABLED (1ULL << 7)\n+#define V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_LOOP_FILTER_ACROSS_SLICES_ENABLED (1ULL << 8)\n+#define V4L2_HEVC_SLICE_PARAMS_FLAG_DEPENDENT_SLICE_SEGMENT\t(1ULL << 9)\n+\n+/**\n+ * struct v4l2_ctrl_hevc_slice_params - HEVC slice parameters\n+ *\n+ * This control is a dynamically sized 1-dimensional array,\n+ * V4L2_CTRL_FLAG_DYNAMIC_ARRAY flag must be set when using it.\n+ *\n+ * @bit_size: size (in bits) of the current slice data\n+ * @data_byte_offset: offset (in bytes) to the video data in the current slice data\n+ * @num_entry_point_offsets: specifies the number of entry point offset syntax\n+ *\t\t\t elements in the slice header.\n+ * @nal_unit_type: specifies the coding type of the slice (B, P or I)\n+ * @nuh_temporal_id_plus1: minus 1 specifies a temporal identifier for the NAL unit\n+ * @slice_type: see V4L2_HEVC_SLICE_TYPE_{}\n+ * @colour_plane_id: specifies the colour plane associated with the current slice\n+ * @slice_pic_order_cnt: specifies the picture order count\n+ * @num_ref_idx_l0_active_minus1: this value plus 1 specifies the maximum\n+ * reference index for reference picture list 0\n+ * that may be used to decode the slice\n+ * @num_ref_idx_l1_active_minus1: this value plus 1 specifies the maximum\n+ * reference index for reference picture list 1\n+ * that may be used to decode the slice\n+ * @collocated_ref_idx: specifies the reference index of the collocated picture used\n+ *\t\t\tfor temporal motion vector prediction\n+ * @five_minus_max_num_merge_cand: specifies the maximum number of merging\n+ *\t\t\t\t motion vector prediction candidates supported in\n+ *\t\t\t\t the slice subtracted from 5\n+ * @slice_qp_delta: specifies the initial value of QpY to be used for the coding\n+ *\t\t blocks in the slice\n+ * @slice_cb_qp_offset: specifies a difference to be added to the value of pps_cb_qp_offset\n+ * @slice_cr_qp_offset: specifies a difference to be added to the value of pps_cr_qp_offset\n+ * @slice_act_y_qp_offset: screen content extension parameters\n+ * @slice_act_cb_qp_offset: screen content extension parameters\n+ * @slice_act_cr_qp_offset: screen content extension parameters\n+ * @slice_beta_offset_div2: specify the deblocking parameter offsets for beta divided by 2\n+ * @slice_tc_offset_div2: specify the deblocking parameter offsets for tC divided by 2\n+ * @pic_struct: indicates whether a picture should be displayed as a frame or as one or\n+ *\t\tmore fields\n+ * @reserved0: padding field. Should be zeroed by applications.\n+ * @slice_segment_addr: specifies the address of the first coding tree block in\n+ *\t\t\tthe slice segment\n+ * @ref_idx_l0: the list of L0 reference elements as indices in the DPB\n+ * @ref_idx_l1: the list of L1 reference elements as indices in the DPB\n+ * @short_term_ref_pic_set_size: specifies the size of short-term reference\n+ *\t\t\t\t pictures set included in the SPS\n+ * @long_term_ref_pic_set_size: specifies the size of long-term reference\n+ *\t\t\t\tpictures set include in the SPS\n+ * @pred_weight_table: the prediction weight coefficients for inter-picture\n+ *\t\t prediction\n+ * @reserved1: padding field. Should be zeroed by applications.\n+ * @flags: see V4L2_HEVC_SLICE_PARAMS_FLAG_{}\n+ */\n+struct v4l2_ctrl_hevc_slice_params {\n+\t__u32\tbit_size;\n+\t__u32\tdata_byte_offset;\n+\t__u32\tnum_entry_point_offsets;\n+\n+\t/* ISO/IEC 23008-2, ITU-T Rec. H.265: NAL unit header */\n+\t__u8\tnal_unit_type;\n+\t__u8\tnuh_temporal_id_plus1;\n+\n+\t/* ISO/IEC 23008-2, ITU-T Rec. H.265: General slice segment header */\n+\t__u8\tslice_type;\n+\t__u8\tcolour_plane_id;\n+\t__s32\tslice_pic_order_cnt;\n+\t__u8\tnum_ref_idx_l0_active_minus1;\n+\t__u8\tnum_ref_idx_l1_active_minus1;\n+\t__u8\tcollocated_ref_idx;\n+\t__u8\tfive_minus_max_num_merge_cand;\n+\t__s8\tslice_qp_delta;\n+\t__s8\tslice_cb_qp_offset;\n+\t__s8\tslice_cr_qp_offset;\n+\t__s8\tslice_act_y_qp_offset;\n+\t__s8\tslice_act_cb_qp_offset;\n+\t__s8\tslice_act_cr_qp_offset;\n+\t__s8\tslice_beta_offset_div2;\n+\t__s8\tslice_tc_offset_div2;\n+\n+\t/* ISO/IEC 23008-2, ITU-T Rec. H.265: Picture timing SEI message */\n+\t__u8\tpic_struct;\n+\n+\t__u8\treserved0[3];\n+\t/* ISO/IEC 23008-2, ITU-T Rec. H.265: General slice segment header */\n+\t__u32\tslice_segment_addr;\n+\t__u8\tref_idx_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX];\n+\t__u8\tref_idx_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX];\n+\t__u16\tshort_term_ref_pic_set_size;\n+\t__u16\tlong_term_ref_pic_set_size;\n+\n+\t/* ISO/IEC 23008-2, ITU-T Rec. H.265: Weighted prediction parameter */\n+\tstruct v4l2_hevc_pred_weight_table pred_weight_table;\n+\n+\t__u8\treserved1[2];\n+\t__u64\tflags;\n+};\n+\n+#define V4L2_HEVC_DECODE_PARAM_FLAG_IRAP_PIC\t\t0x1\n+#define V4L2_HEVC_DECODE_PARAM_FLAG_IDR_PIC\t\t0x2\n+#define V4L2_HEVC_DECODE_PARAM_FLAG_NO_OUTPUT_OF_PRIOR 0x4\n+\n+/**\n+ * struct v4l2_ctrl_hevc_decode_params - HEVC decode parameters\n+ *\n+ * @pic_order_cnt_val: picture order count\n+ * @short_term_ref_pic_set_size: specifies the size of short-term reference\n+ *\t\t\t\t pictures set included in the SPS of the first slice\n+ * @long_term_ref_pic_set_size: specifies the size of long-term reference\n+ *\t\t\t\tpictures set include in the SPS of the first slice\n+ * @num_active_dpb_entries: the number of entries in dpb\n+ * @num_poc_st_curr_before: the number of reference pictures in the short-term\n+ *\t\t\t set that come before the current frame\n+ * @num_poc_st_curr_after: the number of reference pictures in the short-term\n+ *\t\t\t set that come after the current frame\n+ * @num_poc_lt_curr: the number of reference pictures in the long-term set\n+ * @poc_st_curr_before: provides the index of the short term before references\n+ *\t\t\tin DPB array\n+ * @poc_st_curr_after: provides the index of the short term after references\n+ *\t\t in DPB array\n+ * @poc_lt_curr: provides the index of the long term references in DPB array\n+ * @num_delta_pocs_of_ref_rps_idx: same as the derived value NumDeltaPocs[RefRpsIdx],\n+ *\t\t\t\t can be used to parse the RPS data in slice headers\n+ *\t\t\t\t instead of skipping it with @short_term_ref_pic_set_size.\n+ * @reserved: padding field. Should be zeroed by applications.\n+ * @dpb: the decoded picture buffer, for meta-data about reference frames\n+ * @flags: see V4L2_HEVC_DECODE_PARAM_FLAG_{}\n+ */\n+struct v4l2_ctrl_hevc_decode_params {\n+\t__s32\tpic_order_cnt_val;\n+\t__u16\tshort_term_ref_pic_set_size;\n+\t__u16\tlong_term_ref_pic_set_size;\n+\t__u8\tnum_active_dpb_entries;\n+\t__u8\tnum_poc_st_curr_before;\n+\t__u8\tnum_poc_st_curr_after;\n+\t__u8\tnum_poc_lt_curr;\n+\t__u8\tpoc_st_curr_before[V4L2_HEVC_DPB_ENTRIES_NUM_MAX];\n+\t__u8\tpoc_st_curr_after[V4L2_HEVC_DPB_ENTRIES_NUM_MAX];\n+\t__u8\tpoc_lt_curr[V4L2_HEVC_DPB_ENTRIES_NUM_MAX];\n+\t__u8\tnum_delta_pocs_of_ref_rps_idx;\n+\t__u8\treserved[3];\n+\tstruct\tv4l2_hevc_dpb_entry dpb[V4L2_HEVC_DPB_ENTRIES_NUM_MAX];\n+\t__u64\tflags;\n+};\n+\n+/**\n+ * struct v4l2_ctrl_hevc_scaling_matrix - HEVC scaling lists parameters\n+ *\n+ * @scaling_list_4x4: scaling list is used for the scaling process for\n+ *\t\t transform coefficients. The values on each scaling\n+ *\t\t list are expected in raster scan order\n+ * @scaling_list_8x8: scaling list is used for the scaling process for\n+ *\t\t transform coefficients. The values on each scaling\n+ *\t\t list are expected in raster scan order\n+ * @scaling_list_16x16:\tscaling list is used for the scaling process for\n+ *\t\t\ttransform coefficients. The values on each scaling\n+ *\t\t\tlist are expected in raster scan order\n+ * @scaling_list_32x32:\tscaling list is used for the scaling process for\n+ *\t\t\ttransform coefficients. The values on each scaling\n+ *\t\t\tlist are expected in raster scan order\n+ * @scaling_list_dc_coef_16x16:\tscaling list is used for the scaling process\n+ *\t\t\t\tfor transform coefficients. The values on each\n+ *\t\t\t\tscaling list are expected in raster scan order.\n+ * @scaling_list_dc_coef_32x32:\tscaling list is used for the scaling process\n+ *\t\t\t\tfor transform coefficients. The values on each\n+ *\t\t\t\tscaling list are expected in raster scan order.\n+ */\n+struct v4l2_ctrl_hevc_scaling_matrix {\n+\t__u8\tscaling_list_4x4[6][16];\n+\t__u8\tscaling_list_8x8[6][64];\n+\t__u8\tscaling_list_16x16[6][64];\n+\t__u8\tscaling_list_32x32[2][64];\n+\t__u8\tscaling_list_dc_coef_16x16[6];\n+\t__u8\tscaling_list_dc_coef_32x32[2];\n+};\n+\n #define V4L2_CID_COLORIMETRY_CLASS_BASE\t(V4L2_CTRL_CLASS_COLORIMETRY | 0x900)\n #define V4L2_CID_COLORIMETRY_CLASS\t(V4L2_CTRL_CLASS_COLORIMETRY | 1)\n \n@@ -2317,6 +2846,645 @@ struct v4l2_ctrl_vp9_compressed_hdr {\n \tstruct v4l2_vp9_mv_probs mv;\n };\n \n+/* Stateless AV1 controls */\n+\n+#define V4L2_AV1_TOTAL_REFS_PER_FRAME\t8\n+#define V4L2_AV1_CDEF_MAX\t\t8\n+#define V4L2_AV1_NUM_PLANES_MAX\t\t3 /* 1 if monochrome, 3 otherwise */\n+#define V4L2_AV1_MAX_SEGMENTS\t\t8\n+#define V4L2_AV1_MAX_OPERATING_POINTS\t(1 << 5) /* 5 bits to encode */\n+#define V4L2_AV1_REFS_PER_FRAME\t\t7\n+#define V4L2_AV1_MAX_NUM_Y_POINTS\t(1 << 4) /* 4 bits to encode */\n+#define V4L2_AV1_MAX_NUM_CB_POINTS\t(1 << 4) /* 4 bits to encode */\n+#define V4L2_AV1_MAX_NUM_CR_POINTS\t(1 << 4) /* 4 bits to encode */\n+#define V4L2_AV1_AR_COEFFS_SIZE\t\t25 /* (2 * 3 * (3 + 1)) + 1 */\n+#define V4L2_AV1_MAX_NUM_PLANES\t\t3\n+#define V4L2_AV1_MAX_TILE_COLS\t\t64\n+#define V4L2_AV1_MAX_TILE_ROWS\t\t64\n+#define V4L2_AV1_MAX_TILE_COUNT\t\t512\n+\n+#define V4L2_AV1_SEQUENCE_FLAG_STILL_PICTURE\t\t 0x00000001\n+#define V4L2_AV1_SEQUENCE_FLAG_USE_128X128_SUPERBLOCK\t 0x00000002\n+#define V4L2_AV1_SEQUENCE_FLAG_ENABLE_FILTER_INTRA\t 0x00000004\n+#define V4L2_AV1_SEQUENCE_FLAG_ENABLE_INTRA_EDGE_FILTER 0x00000008\n+#define V4L2_AV1_SEQUENCE_FLAG_ENABLE_INTERINTRA_COMPOUND 0x00000010\n+#define V4L2_AV1_SEQUENCE_FLAG_ENABLE_MASKED_COMPOUND\t 0x00000020\n+#define V4L2_AV1_SEQUENCE_FLAG_ENABLE_WARPED_MOTION\t 0x00000040\n+#define V4L2_AV1_SEQUENCE_FLAG_ENABLE_DUAL_FILTER\t 0x00000080\n+#define V4L2_AV1_SEQUENCE_FLAG_ENABLE_ORDER_HINT\t 0x00000100\n+#define V4L2_AV1_SEQUENCE_FLAG_ENABLE_JNT_COMP\t\t 0x00000200\n+#define V4L2_AV1_SEQUENCE_FLAG_ENABLE_REF_FRAME_MVS\t 0x00000400\n+#define V4L2_AV1_SEQUENCE_FLAG_ENABLE_SUPERRES\t\t 0x00000800\n+#define V4L2_AV1_SEQUENCE_FLAG_ENABLE_CDEF\t\t 0x00001000\n+#define V4L2_AV1_SEQUENCE_FLAG_ENABLE_RESTORATION\t 0x00002000\n+#define V4L2_AV1_SEQUENCE_FLAG_MONO_CHROME\t\t 0x00004000\n+#define V4L2_AV1_SEQUENCE_FLAG_COLOR_RANGE\t\t 0x00008000\n+#define V4L2_AV1_SEQUENCE_FLAG_SUBSAMPLING_X\t\t 0x00010000\n+#define V4L2_AV1_SEQUENCE_FLAG_SUBSAMPLING_Y\t\t 0x00020000\n+#define V4L2_AV1_SEQUENCE_FLAG_FILM_GRAIN_PARAMS_PRESENT 0x00040000\n+#define V4L2_AV1_SEQUENCE_FLAG_SEPARATE_UV_DELTA_Q\t 0x00080000\n+\n+#define V4L2_CID_STATELESS_AV1_SEQUENCE (V4L2_CID_CODEC_STATELESS_BASE + 500)\n+/**\n+ * struct v4l2_ctrl_av1_sequence - AV1 Sequence\n+ *\n+ * Represents an AV1 Sequence OBU. See section 5.5 \"Sequence header OBU syntax\"\n+ * for more details.\n+ *\n+ * @flags: See V4L2_AV1_SEQUENCE_FLAG_{}.\n+ * @seq_profile: specifies the features that can be used in the coded video\n+ * sequence.\n+ * @order_hint_bits: specifies the number of bits used for the order_hint field\n+ * at each frame.\n+ * @bit_depth: the bitdepth to use for the sequence as described in section\n+ * 5.5.2 \"Color config syntax\".\n+ * @reserved: padding field. Should be zeroed by applications.\n+ * @max_frame_width_minus_1: specifies the maximum frame width minus 1 for the\n+ * frames represented by this sequence header.\n+ * @max_frame_height_minus_1: specifies the maximum frame height minus 1 for the\n+ * frames represented by this sequence header.\n+ */\n+struct v4l2_ctrl_av1_sequence {\n+\t__u32 flags;\n+\t__u8 seq_profile;\n+\t__u8 order_hint_bits;\n+\t__u8 bit_depth;\n+\t__u8 reserved;\n+\t__u16 max_frame_width_minus_1;\n+\t__u16 max_frame_height_minus_1;\n+};\n+\n+#define V4L2_CID_STATELESS_AV1_TILE_GROUP_ENTRY (V4L2_CID_CODEC_STATELESS_BASE + 501)\n+/**\n+ * struct v4l2_ctrl_av1_tile_group_entry - AV1 Tile Group entry\n+ *\n+ * Represents a single AV1 tile inside an AV1 Tile Group. Note that MiRowStart,\n+ * MiRowEnd, MiColStart and MiColEnd can be retrieved from struct\n+ * v4l2_av1_tile_info in struct v4l2_ctrl_av1_frame using tile_row and\n+ * tile_col. See section 6.10.1 \"General tile group OBU semantics\" for more\n+ * details.\n+ *\n+ * @tile_offset: offset from the OBU data, i.e. where the coded tile data\n+ * actually starts.\n+ * @tile_size: specifies the size in bytes of the coded tile. Equivalent to\n+ * \"TileSize\" in the AV1 Specification.\n+ * @tile_row: specifies the row of the current tile. Equivalent to \"TileRow\" in\n+ * the AV1 Specification.\n+ * @tile_col: specifies the col of the current tile. Equivalent to \"TileCol\" in\n+ * the AV1 Specification.\n+ */\n+struct v4l2_ctrl_av1_tile_group_entry {\n+\t__u32 tile_offset;\n+\t__u32 tile_size;\n+\t__u32 tile_row;\n+\t__u32 tile_col;\n+};\n+\n+/**\n+ * enum v4l2_av1_warp_model - AV1 Warp Model as described in section 3\n+ * \"Symbols and abbreviated terms\" of the AV1 Specification.\n+ *\n+ * @V4L2_AV1_WARP_MODEL_IDENTITY: Warp model is just an identity transform.\n+ * @V4L2_AV1_WARP_MODEL_TRANSLATION: Warp model is a pure translation.\n+ * @V4L2_AV1_WARP_MODEL_ROTZOOM: Warp model is a rotation + symmetric zoom +\n+ * translation.\n+ * @V4L2_AV1_WARP_MODEL_AFFINE: Warp model is a general affine transform.\n+ */\n+enum v4l2_av1_warp_model {\n+\tV4L2_AV1_WARP_MODEL_IDENTITY = 0,\n+\tV4L2_AV1_WARP_MODEL_TRANSLATION = 1,\n+\tV4L2_AV1_WARP_MODEL_ROTZOOM = 2,\n+\tV4L2_AV1_WARP_MODEL_AFFINE = 3,\n+};\n+\n+/**\n+ * enum v4l2_av1_reference_frame - AV1 reference frames\n+ *\n+ * @V4L2_AV1_REF_INTRA_FRAME: Intra Frame Reference\n+ * @V4L2_AV1_REF_LAST_FRAME: Last Reference Frame\n+ * @V4L2_AV1_REF_LAST2_FRAME: Last2 Reference Frame\n+ * @V4L2_AV1_REF_LAST3_FRAME: Last3 Reference Frame\n+ * @V4L2_AV1_REF_GOLDEN_FRAME: Golden Reference Frame\n+ * @V4L2_AV1_REF_BWDREF_FRAME: BWD Reference Frame\n+ * @V4L2_AV1_REF_ALTREF2_FRAME: Alternative2 Reference Frame\n+ * @V4L2_AV1_REF_ALTREF_FRAME: Alternative Reference Frame\n+ */\n+enum v4l2_av1_reference_frame {\n+\tV4L2_AV1_REF_INTRA_FRAME = 0,\n+\tV4L2_AV1_REF_LAST_FRAME = 1,\n+\tV4L2_AV1_REF_LAST2_FRAME = 2,\n+\tV4L2_AV1_REF_LAST3_FRAME = 3,\n+\tV4L2_AV1_REF_GOLDEN_FRAME = 4,\n+\tV4L2_AV1_REF_BWDREF_FRAME = 5,\n+\tV4L2_AV1_REF_ALTREF2_FRAME = 6,\n+\tV4L2_AV1_REF_ALTREF_FRAME = 7,\n+};\n+\n+#define V4L2_AV1_GLOBAL_MOTION_IS_INVALID(ref) (1 << (ref))\n+\n+#define V4L2_AV1_GLOBAL_MOTION_FLAG_IS_GLOBAL\t 0x1\n+#define V4L2_AV1_GLOBAL_MOTION_FLAG_IS_ROT_ZOOM\t 0x2\n+#define V4L2_AV1_GLOBAL_MOTION_FLAG_IS_TRANSLATION 0x4\n+/**\n+ * struct v4l2_av1_global_motion - AV1 Global Motion parameters as described in\n+ * section 6.8.17 \"Global motion params semantics\" of the AV1 specification.\n+ *\n+ * @flags: A bitfield containing the flags per reference frame. See\n+ * V4L2_AV1_GLOBAL_MOTION_FLAG_{}\n+ * @type: The type of global motion transform used.\n+ * @params: this field has the same meaning as \"gm_params\" in the AV1\n+ * specification.\n+ * @invalid: bitfield indicating whether the global motion params are invalid\n+ * for a given reference frame. See section 7.11.3.6 Setup shear process and\n+ * the variable \"warpValid\". Use V4L2_AV1_GLOBAL_MOTION_IS_INVALID(ref) to\n+ * create a suitable mask.\n+ * @reserved: padding field. Should be zeroed by applications.\n+ */\n+\n+struct v4l2_av1_global_motion {\n+\t__u8 flags[V4L2_AV1_TOTAL_REFS_PER_FRAME];\n+\tenum v4l2_av1_warp_model type[V4L2_AV1_TOTAL_REFS_PER_FRAME];\n+\t__s32 params[V4L2_AV1_TOTAL_REFS_PER_FRAME][6];\n+\t__u8 invalid;\n+\t__u8 reserved[3];\n+};\n+\n+/**\n+ * enum v4l2_av1_frame_restoration_type - AV1 Frame Restoration Type\n+ * @V4L2_AV1_FRAME_RESTORE_NONE: no filtering is applied.\n+ * @V4L2_AV1_FRAME_RESTORE_WIENER: Wiener filter process is invoked.\n+ * @V4L2_AV1_FRAME_RESTORE_SGRPROJ: self guided filter process is invoked.\n+ * @V4L2_AV1_FRAME_RESTORE_SWITCHABLE: restoration filter is swichtable.\n+ */\n+enum v4l2_av1_frame_restoration_type {\n+\tV4L2_AV1_FRAME_RESTORE_NONE = 0,\n+\tV4L2_AV1_FRAME_RESTORE_WIENER = 1,\n+\tV4L2_AV1_FRAME_RESTORE_SGRPROJ = 2,\n+\tV4L2_AV1_FRAME_RESTORE_SWITCHABLE = 3,\n+};\n+\n+#define V4L2_AV1_LOOP_RESTORATION_FLAG_USES_LR\t\t0x1\n+#define V4L2_AV1_LOOP_RESTORATION_FLAG_USES_CHROMA_LR\t0x2\n+\n+/**\n+ * struct v4l2_av1_loop_restoration - AV1 Loop Restauration as described in\n+ * section 6.10.15 \"Loop restoration params semantics\" of the AV1 specification.\n+ *\n+ * @flags: See V4L2_AV1_LOOP_RESTORATION_FLAG_{}.\n+ * @lr_unit_shift: specifies if the luma restoration size should be halved.\n+ * @lr_uv_shift: specifies if the chroma size should be half the luma size.\n+ * @reserved: padding field. Should be zeroed by applications.\n+ * @frame_restoration_type: specifies the type of restoration used for each\n+ * plane. See enum v4l2_av1_frame_restoration_type.\n+ * @loop_restoration_size: specifies the size of loop restoration units in units\n+ * of samples in the current plane.\n+ */\n+struct v4l2_av1_loop_restoration {\n+\t__u8 flags;\n+\t__u8 lr_unit_shift;\n+\t__u8 lr_uv_shift;\n+\t__u8 reserved;\n+\tenum v4l2_av1_frame_restoration_type frame_restoration_type[V4L2_AV1_NUM_PLANES_MAX];\n+\t__u32 loop_restoration_size[V4L2_AV1_MAX_NUM_PLANES];\n+};\n+\n+/**\n+ * struct v4l2_av1_cdef - AV1 CDEF params semantics as described in section\n+ * 6.10.14 \"CDEF params semantics\" of the AV1 specification\n+ *\n+ * @damping_minus_3: controls the amount of damping in the deringing filter.\n+ * @bits: specifies the number of bits needed to specify which CDEF filter to\n+ * apply.\n+ * @y_pri_strength: specifies the strength of the primary filter.\n+ * @y_sec_strength: specifies the strength of the secondary filter.\n+ * @uv_pri_strength: specifies the strength of the primary filter.\n+ * @uv_sec_strength: specifies the strength of the secondary filter.\n+ */\n+struct v4l2_av1_cdef {\n+\t__u8 damping_minus_3;\n+\t__u8 bits;\n+\t__u8 y_pri_strength[V4L2_AV1_CDEF_MAX];\n+\t__u8 y_sec_strength[V4L2_AV1_CDEF_MAX];\n+\t__u8 uv_pri_strength[V4L2_AV1_CDEF_MAX];\n+\t__u8 uv_sec_strength[V4L2_AV1_CDEF_MAX];\n+};\n+\n+#define V4L2_AV1_SEGMENTATION_FLAG_ENABLED\t 0x1\n+#define V4L2_AV1_SEGMENTATION_FLAG_UPDATE_MAP\t 0x2\n+#define V4L2_AV1_SEGMENTATION_FLAG_TEMPORAL_UPDATE 0x4\n+#define V4L2_AV1_SEGMENTATION_FLAG_UPDATE_DATA\t 0x8\n+#define V4L2_AV1_SEGMENTATION_FLAG_SEG_ID_PRE_SKIP 0x10\n+\n+/**\n+ * enum v4l2_av1_segment_feature - AV1 segment features as described in section\n+ * 3 \"Symbols and abbreviated terms\" of the AV1 specification.\n+ *\n+ * @V4L2_AV1_SEG_LVL_ALT_Q: Index for quantizer segment feature.\n+ * @V4L2_AV1_SEG_LVL_ALT_LF_Y_V: Index for vertical luma loop filter segment\n+ * feature.\n+ * @V4L2_AV1_SEG_LVL_REF_FRAME: Index for reference frame segment feature.\n+ * @V4L2_AV1_SEG_LVL_REF_SKIP: Index for skip segment feature.\n+ * @V4L2_AV1_SEG_LVL_REF_GLOBALMV: Index for global mv feature.\n+ * @V4L2_AV1_SEG_LVL_MAX: Number of segment features.\n+ */\n+enum v4l2_av1_segment_feature {\n+\tV4L2_AV1_SEG_LVL_ALT_Q = 0,\n+\tV4L2_AV1_SEG_LVL_ALT_LF_Y_V = 1,\n+\tV4L2_AV1_SEG_LVL_REF_FRAME = 5,\n+\tV4L2_AV1_SEG_LVL_REF_SKIP = 6,\n+\tV4L2_AV1_SEG_LVL_REF_GLOBALMV = 7,\n+\tV4L2_AV1_SEG_LVL_MAX = 8\n+};\n+\n+#define V4L2_AV1_SEGMENT_FEATURE_ENABLED(id)\t(1 << (id))\n+\n+/**\n+ * struct v4l2_av1_segmentation - AV1 Segmentation params as defined in section\n+ * 6.8.13 \"Segmentation params semantics\" of the AV1 specification.\n+ *\n+ * @flags: see V4L2_AV1_SEGMENTATION_FLAG_{}.\n+ * @last_active_seg_id: indicates the highest numbered segment id that has some\n+ * enabled feature. This is used when decoding the segment id to only decode\n+ * choices corresponding to used segments.\n+ * @feature_enabled: bitmask defining which features are enabled in each\n+ * segment. Use V4L2_AV1_SEGMENT_FEATURE_ENABLED to build a suitable mask.\n+ * @feature_data: data attached to each feature. Data entry is only valid if the\n+ * feature is enabled\n+ */\n+struct v4l2_av1_segmentation {\n+\t__u8 flags;\n+\t__u8 last_active_seg_id;\n+\t__u8 feature_enabled[V4L2_AV1_MAX_SEGMENTS];\n+\t__s16 feature_data[V4L2_AV1_MAX_SEGMENTS][V4L2_AV1_SEG_LVL_MAX];\n+};\n+\n+#define V4L2_AV1_LOOP_FILTER_FLAG_DELTA_ENABLED 0x1\n+#define V4L2_AV1_LOOP_FILTER_FLAG_DELTA_UPDATE 0x2\n+#define V4L2_AV1_LOOP_FILTER_FLAG_DELTA_LF_PRESENT 0x4\n+#define V4L2_AV1_LOOP_FILTER_FLAG_DELTA_LF_MULTI 0x8\n+\n+/**\n+ * struct v4l2_av1_loop_filter - AV1 Loop filter params as defined in section\n+ * 6.8.10 \"Loop filter semantics\" and 6.8.16 \"Loop filter delta parameters\n+ * semantics\" of the AV1 specification.\n+ *\n+ * @flags: see V4L2_AV1_LOOP_FILTER_FLAG_{}\n+ * @level: an array containing loop filter strength values. Different loop\n+ * filter strength values from the array are used depending on the image plane\n+ * being filtered, and the edge direction (vertical or horizontal) being\n+ * filtered.\n+ * @sharpness: indicates the sharpness level. The loop_filter_level and\n+ * loop_filter_sharpness together determine when a block edge is filtered, and\n+ * by how much the filtering can change the sample values. The loop filter\n+ * process is described in section 7.14 of the AV1 specification.\n+ * @ref_deltas: contains the adjustment needed for the filter level based on the\n+ * chosen reference frame. If this syntax element is not present, it maintains\n+ * its previous value.\n+ * @mode_deltas: contains the adjustment needed for the filter level based on\n+ * the chosen mode. If this syntax element is not present, it maintains its\n+ * previous value.\n+ * @delta_lf_res: specifies the left shift which should be applied to decoded\n+ * loop filter delta values.\n+ */\n+struct v4l2_av1_loop_filter {\n+\t__u8 flags;\n+\t__u8 level[4];\n+\t__u8 sharpness;\n+\t__s8 ref_deltas[V4L2_AV1_TOTAL_REFS_PER_FRAME];\n+\t__s8 mode_deltas[2];\n+\t__u8 delta_lf_res;\n+};\n+\n+#define V4L2_AV1_QUANTIZATION_FLAG_DIFF_UV_DELTA 0x1\n+#define V4L2_AV1_QUANTIZATION_FLAG_USING_QMATRIX 0x2\n+#define V4L2_AV1_QUANTIZATION_FLAG_DELTA_Q_PRESENT 0x4\n+\n+/**\n+ * struct v4l2_av1_quantization - AV1 Quantization params as defined in section\n+ * 6.8.11 \"Quantization params semantics\" of the AV1 specification.\n+ *\n+ * @flags: see V4L2_AV1_QUANTIZATION_FLAG_{}\n+ * @base_q_idx: indicates the base frame qindex. This is used for Y AC\n+ * coefficients and as the base value for the other quantizers.\n+ * @delta_q_y_dc: indicates the Y DC quantizer relative to base_q_idx.\n+ * @delta_q_u_dc: indicates the U DC quantizer relative to base_q_idx.\n+ * @delta_q_u_ac: indicates the U AC quantizer relative to base_q_idx.\n+ * @delta_q_v_dc: indicates the V DC quantizer relative to base_q_idx.\n+ * @delta_q_v_ac: indicates the V AC quantizer relative to base_q_idx.\n+ * @qm_y: specifies the level in the quantizer matrix that should be used for\n+ * luma plane decoding.\n+ * @qm_u: specifies the level in the quantizer matrix that should be used for\n+ * chroma U plane decoding.\n+ * @qm_v: specifies the level in the quantizer matrix that should be used for\n+ * chroma V plane decoding.\n+ * @delta_q_res: specifies the left shift which should be applied to decoded\n+ * quantizer index delta values.\n+ */\n+struct v4l2_av1_quantization {\n+\t__u8 flags;\n+\t__u8 base_q_idx;\n+\t__s8 delta_q_y_dc;\n+\t__s8 delta_q_u_dc;\n+\t__s8 delta_q_u_ac;\n+\t__s8 delta_q_v_dc;\n+\t__s8 delta_q_v_ac;\n+\t__u8 qm_y;\n+\t__u8 qm_u;\n+\t__u8 qm_v;\n+\t__u8 delta_q_res;\n+};\n+\n+#define V4L2_AV1_TILE_INFO_FLAG_UNIFORM_TILE_SPACING\t0x1\n+\n+/**\n+ * struct v4l2_av1_tile_info - AV1 Tile info as defined in section 6.8.14 \"Tile\n+ * info semantics\" of the AV1 specification.\n+ *\n+ * @flags: see V4L2_AV1_TILE_INFO_FLAG_{}\n+ * @context_update_tile_id: specifies which tile to use for the CDF update.\n+ * @tile_rows: specifies the number of tiles down the frame.\n+ * @tile_cols: specifies the number of tiles across the frame.\n+ * @mi_col_starts: an array specifying the start column (in units of 4x4 luma\n+ * samples) for each tile across the image.\n+ * @mi_row_starts: an array specifying the start row (in units of 4x4 luma\n+ * samples) for each tile down the image.\n+ * @width_in_sbs_minus_1: specifies the width of a tile minus 1 in units of\n+ * superblocks.\n+ * @height_in_sbs_minus_1: specifies the height of a tile minus 1 in units of\n+ * superblocks.\n+ * @tile_size_bytes: specifies the number of bytes needed to code each tile\n+ * size.\n+ * @reserved: padding field. Should be zeroed by applications.\n+ */\n+struct v4l2_av1_tile_info {\n+\t__u8 flags;\n+\t__u8 context_update_tile_id;\n+\t__u8 tile_cols;\n+\t__u8 tile_rows;\n+\t__u32 mi_col_starts[V4L2_AV1_MAX_TILE_COLS + 1];\n+\t__u32 mi_row_starts[V4L2_AV1_MAX_TILE_ROWS + 1];\n+\t__u32 width_in_sbs_minus_1[V4L2_AV1_MAX_TILE_COLS];\n+\t__u32 height_in_sbs_minus_1[V4L2_AV1_MAX_TILE_ROWS];\n+\t__u8 tile_size_bytes;\n+\t__u8 reserved[3];\n+};\n+\n+/**\n+ * enum v4l2_av1_frame_type - AV1 Frame Type\n+ *\n+ * @V4L2_AV1_KEY_FRAME: Key frame\n+ * @V4L2_AV1_INTER_FRAME: Inter frame\n+ * @V4L2_AV1_INTRA_ONLY_FRAME: Intra-only frame\n+ * @V4L2_AV1_SWITCH_FRAME: Switch frame\n+ */\n+enum v4l2_av1_frame_type {\n+\tV4L2_AV1_KEY_FRAME = 0,\n+\tV4L2_AV1_INTER_FRAME = 1,\n+\tV4L2_AV1_INTRA_ONLY_FRAME = 2,\n+\tV4L2_AV1_SWITCH_FRAME = 3\n+};\n+\n+/**\n+ * enum v4l2_av1_interpolation_filter - AV1 interpolation filter types\n+ *\n+ * @V4L2_AV1_INTERPOLATION_FILTER_EIGHTTAP: eight tap filter\n+ * @V4L2_AV1_INTERPOLATION_FILTER_EIGHTTAP_SMOOTH: eight tap smooth filter\n+ * @V4L2_AV1_INTERPOLATION_FILTER_EIGHTTAP_SHARP: eight tap sharp filter\n+ * @V4L2_AV1_INTERPOLATION_FILTER_BILINEAR: bilinear filter\n+ * @V4L2_AV1_INTERPOLATION_FILTER_SWITCHABLE: filter selection is signaled at\n+ * the block level\n+ *\n+ * See section 6.8.9 \"Interpolation filter semantics\" of the AV1 specification\n+ * for more details.\n+ */\n+enum v4l2_av1_interpolation_filter {\n+\tV4L2_AV1_INTERPOLATION_FILTER_EIGHTTAP = 0,\n+\tV4L2_AV1_INTERPOLATION_FILTER_EIGHTTAP_SMOOTH = 1,\n+\tV4L2_AV1_INTERPOLATION_FILTER_EIGHTTAP_SHARP = 2,\n+\tV4L2_AV1_INTERPOLATION_FILTER_BILINEAR = 3,\n+\tV4L2_AV1_INTERPOLATION_FILTER_SWITCHABLE = 4,\n+};\n+\n+/**\n+ * enum v4l2_av1_tx_mode - AV1 Tx mode as described in section 6.8.21 \"TX mode\n+ * semantics\" of the AV1 specification.\n+ * @V4L2_AV1_TX_MODE_ONLY_4X4: the inverse transform will use only 4x4\n+ * transforms\n+ * @V4L2_AV1_TX_MODE_LARGEST: the inverse transform will use the largest\n+ * transform size that fits inside the block\n+ * @V4L2_AV1_TX_MODE_SELECT: the choice of transform size is specified\n+ * explicitly for each block.\n+ */\n+enum v4l2_av1_tx_mode {\n+\tV4L2_AV1_TX_MODE_ONLY_4X4 = 0,\n+\tV4L2_AV1_TX_MODE_LARGEST = 1,\n+\tV4L2_AV1_TX_MODE_SELECT = 2\n+};\n+\n+#define V4L2_AV1_FRAME_FLAG_SHOW_FRAME\t\t\t 0x00000001\n+#define V4L2_AV1_FRAME_FLAG_SHOWABLE_FRAME\t\t 0x00000002\n+#define V4L2_AV1_FRAME_FLAG_ERROR_RESILIENT_MODE\t 0x00000004\n+#define V4L2_AV1_FRAME_FLAG_DISABLE_CDF_UPDATE\t\t 0x00000008\n+#define V4L2_AV1_FRAME_FLAG_ALLOW_SCREEN_CONTENT_TOOLS\t 0x00000010\n+#define V4L2_AV1_FRAME_FLAG_FORCE_INTEGER_MV\t\t 0x00000020\n+#define V4L2_AV1_FRAME_FLAG_ALLOW_INTRABC\t\t 0x00000040\n+#define V4L2_AV1_FRAME_FLAG_USE_SUPERRES\t\t 0x00000080\n+#define V4L2_AV1_FRAME_FLAG_ALLOW_HIGH_PRECISION_MV\t 0x00000100\n+#define V4L2_AV1_FRAME_FLAG_IS_MOTION_MODE_SWITCHABLE\t 0x00000200\n+#define V4L2_AV1_FRAME_FLAG_USE_REF_FRAME_MVS\t\t 0x00000400\n+#define V4L2_AV1_FRAME_FLAG_DISABLE_FRAME_END_UPDATE_CDF 0x00000800\n+#define V4L2_AV1_FRAME_FLAG_ALLOW_WARPED_MOTION\t\t 0x00001000\n+#define V4L2_AV1_FRAME_FLAG_REFERENCE_SELECT\t\t 0x00002000\n+#define V4L2_AV1_FRAME_FLAG_REDUCED_TX_SET\t\t 0x00004000\n+#define V4L2_AV1_FRAME_FLAG_SKIP_MODE_ALLOWED\t\t 0x00008000\n+#define V4L2_AV1_FRAME_FLAG_SKIP_MODE_PRESENT\t\t 0x00010000\n+#define V4L2_AV1_FRAME_FLAG_FRAME_SIZE_OVERRIDE\t\t 0x00020000\n+#define V4L2_AV1_FRAME_FLAG_BUFFER_REMOVAL_TIME_PRESENT\t 0x00040000\n+#define V4L2_AV1_FRAME_FLAG_FRAME_REFS_SHORT_SIGNALING\t 0x00080000\n+\n+#define V4L2_CID_STATELESS_AV1_FRAME (V4L2_CID_CODEC_STATELESS_BASE + 502)\n+/**\n+ * struct v4l2_ctrl_av1_frame - Represents an AV1 Frame Header OBU.\n+ *\n+ * @tile_info: tile info\n+ * @quantization: quantization params\n+ * @segmentation: segmentation params\n+ * @superres_denom: the denominator for the upscaling ratio.\n+ * @loop_filter: loop filter params\n+ * @cdef: cdef params\n+ * @skip_mode_frame: specifies the frames to use for compound prediction when\n+ * skip_mode is equal to 1.\n+ * @primary_ref_frame: specifies which reference frame contains the CDF values\n+ * and other state that should be loaded at the start of the frame.\n+ * @loop_restoration: loop restoration params\n+ * @global_motion: global motion params\n+ * @flags: see V4L2_AV1_FRAME_FLAG_{}\n+ * @frame_type: specifies the AV1 frame type\n+ * @order_hint: specifies OrderHintBits least significant bits of the expected\n+ * output order for this frame.\n+ * @upscaled_width: the upscaled width.\n+ * @interpolation_filter: specifies the filter selection used for performing\n+ * inter prediction.\n+ * @tx_mode: specifies how the transform size is determined.\n+ * @frame_width_minus_1: add 1 to get the frame's width.\n+ * @frame_height_minus_1: add 1 to get the frame's height\n+ * @render_width_minus_1: add 1 to get the render width of the frame in luma\n+ * samples.\n+ * @render_height_minus_1: add 1 to get the render height of the frame in luma\n+ * samples.\n+ * @current_frame_id: specifies the frame id number for the current frame. Frame\n+ * id numbers are additional information that do not affect the decoding\n+ * process, but provide decoders with a way of detecting missing reference\n+ * frames so that appropriate action can be taken.\n+ * @buffer_removal_time: specifies the frame removal time in units of DecCT clock\n+ * ticks counted from the removal time of the last random access point for\n+ * operating point opNum.\n+ * @reserved: padding field. Should be zeroed by applications.\n+ * @order_hints: specifies the expected output order hint for each reference\n+ * frame. This field corresponds to the OrderHints variable from the\n+ * specification (section 5.9.2 \"Uncompressed header syntax\"). As such, this is\n+ * only used for non-intra frames and ignored otherwise. order_hints[0] is\n+ * always ignored.\n+ * @reference_frame_ts: the V4L2 timestamp of the reference frame slots.\n+ * @ref_frame_idx: used to index into @reference_frame_ts when decoding\n+ * inter-frames. The meaning of this array is the same as in the specification.\n+ * The timestamp refers to the timestamp field in struct v4l2_buffer. Use\n+ * v4l2_timeval_to_ns() to convert the struct timeval to a __u64.\n+ * @refresh_frame_flags: contains a bitmask that specifies which reference frame\n+ * slots will be updated with the current frame after it is decoded.\n+ */\n+struct v4l2_ctrl_av1_frame {\n+\tstruct v4l2_av1_tile_info tile_info;\n+\tstruct v4l2_av1_quantization quantization;\n+\t__u8 superres_denom;\n+\tstruct v4l2_av1_segmentation segmentation;\n+\tstruct v4l2_av1_loop_filter loop_filter;\n+\tstruct v4l2_av1_cdef cdef;\n+\t__u8 skip_mode_frame[2];\n+\t__u8 primary_ref_frame;\n+\tstruct v4l2_av1_loop_restoration loop_restoration;\n+\tstruct v4l2_av1_global_motion global_motion;\n+\t__u32 flags;\n+\tenum v4l2_av1_frame_type frame_type;\n+\t__u32 order_hint;\n+\t__u32 upscaled_width;\n+\tenum v4l2_av1_interpolation_filter interpolation_filter;\n+\tenum v4l2_av1_tx_mode tx_mode;\n+\t__u32 frame_width_minus_1;\n+\t__u32 frame_height_minus_1;\n+\t__u16 render_width_minus_1;\n+\t__u16 render_height_minus_1;\n+\n+\t__u32 current_frame_id;\n+\t__u32 buffer_removal_time[V4L2_AV1_MAX_OPERATING_POINTS];\n+\t__u8 reserved[4];\n+\t__u32 order_hints[V4L2_AV1_TOTAL_REFS_PER_FRAME];\n+\t__u64 reference_frame_ts[V4L2_AV1_TOTAL_REFS_PER_FRAME];\n+\t__s8 ref_frame_idx[V4L2_AV1_REFS_PER_FRAME];\n+\t__u8 refresh_frame_flags;\n+};\n+\n+#define V4L2_AV1_FILM_GRAIN_FLAG_APPLY_GRAIN 0x1\n+#define V4L2_AV1_FILM_GRAIN_FLAG_UPDATE_GRAIN 0x2\n+#define V4L2_AV1_FILM_GRAIN_FLAG_CHROMA_SCALING_FROM_LUMA 0x4\n+#define V4L2_AV1_FILM_GRAIN_FLAG_OVERLAP 0x8\n+#define V4L2_AV1_FILM_GRAIN_FLAG_CLIP_TO_RESTRICTED_RANGE 0x10\n+\n+#define V4L2_CID_STATELESS_AV1_FILM_GRAIN (V4L2_CID_CODEC_STATELESS_BASE + 505)\n+/**\n+ * struct v4l2_ctrl_av1_film_grain - AV1 Film Grain parameters.\n+ *\n+ * Film grain parameters as specified by section 6.8.20 of the AV1 Specification.\n+ *\n+ * @flags: see V4L2_AV1_FILM_GRAIN_{}.\n+ * @cr_mult: represents a multiplier for the cr component used in derivation of\n+ * the input index to the cr component scaling function.\n+ * @grain_seed: specifies the starting value for the pseudo-random numbers used\n+ * during film grain synthesis.\n+ * @film_grain_params_ref_idx: indicates which reference frame contains the\n+ * film grain parameters to be used for this frame.\n+ * @num_y_points: specifies the number of points for the piece-wise linear\n+ * scaling function of the luma component.\n+ * @point_y_value: represents the x (luma value) coordinate for the i-th point\n+ * of the piecewise linear scaling function for luma component. The values are\n+ * signaled on the scale of 0..255. In case of 10 bit video, these values\n+ * correspond to luma values divided by 4. In case of 12 bit video, these values\n+ * correspond to luma values divided by 16.\n+ * @point_y_scaling: represents the scaling (output) value for the i-th point\n+ * of the piecewise linear scaling function for luma component.\n+ * @num_cb_points: specifies the number of points for the piece-wise linear\n+ * scaling function of the cb component.\n+ * @point_cb_value: represents the x coordinate for the i-th point of the\n+ * piece-wise linear scaling function for cb component. The values are signaled\n+ * on the scale of 0..255.\n+ * @point_cb_scaling: represents the scaling (output) value for the i-th point\n+ * of the piecewise linear scaling function for cb component.\n+ * @num_cr_points: specifies represents the number of points for the piece-wise\n+ * linear scaling function of the cr component.\n+ * @point_cr_value: represents the x coordinate for the i-th point of the\n+ * piece-wise linear scaling function for cr component. The values are signaled\n+ * on the scale of 0..255.\n+ * @point_cr_scaling: represents the scaling (output) value for the i-th point\n+ * of the piecewise linear scaling function for cr component.\n+ * @grain_scaling_minus_8: represents the shift – 8 applied to the values of the\n+ * chroma component. The grain_scaling_minus_8 can take values of 0..3 and\n+ * determines the range and quantization step of the standard deviation of film\n+ * grain.\n+ * @ar_coeff_lag: specifies the number of auto-regressive coefficients for luma\n+ * and chroma.\n+ * @ar_coeffs_y_plus_128: specifies auto-regressive coefficients used for the Y\n+ * plane.\n+ * @ar_coeffs_cb_plus_128: specifies auto-regressive coefficients used for the U\n+ * plane.\n+ * @ar_coeffs_cr_plus_128: specifies auto-regressive coefficients used for the V\n+ * plane.\n+ * @ar_coeff_shift_minus_6: specifies the range of the auto-regressive\n+ * coefficients. Values of 0, 1, 2, and 3 correspond to the ranges for\n+ * auto-regressive coefficients of [-2, 2), [-1, 1), [-0.5, 0.5) and [-0.25,\n+ * 0.25) respectively.\n+ * @grain_scale_shift: specifies how much the Gaussian random numbers should be\n+ * scaled down during the grain synthesis process.\n+ * @cb_mult: represents a multiplier for the cb component used in derivation of\n+ * the input index to the cb component scaling function.\n+ * @cb_luma_mult: represents a multiplier for the average luma component used in\n+ * derivation of the input index to the cb component scaling function.\n+ * @cr_luma_mult: represents a multiplier for the average luma component used in\n+ * derivation of the input index to the cr component scaling function.\n+ * @cb_offset: represents an offset used in derivation of the input index to the\n+ * cb component scaling function.\n+ * @cr_offset: represents an offset used in derivation of the input index to the\n+ * cr component scaling function.\n+ * @reserved: padding field. Should be zeroed by applications.\n+ */\n+struct v4l2_ctrl_av1_film_grain {\n+\t__u8 flags;\n+\t__u8 cr_mult;\n+\t__u16 grain_seed;\n+\t__u8 film_grain_params_ref_idx;\n+\t__u8 num_y_points;\n+\t__u8 point_y_value[V4L2_AV1_MAX_NUM_Y_POINTS];\n+\t__u8 point_y_scaling[V4L2_AV1_MAX_NUM_Y_POINTS];\n+\t__u8 num_cb_points;\n+\t__u8 point_cb_value[V4L2_AV1_MAX_NUM_CB_POINTS];\n+\t__u8 point_cb_scaling[V4L2_AV1_MAX_NUM_CB_POINTS];\n+\t__u8 num_cr_points;\n+\t__u8 point_cr_value[V4L2_AV1_MAX_NUM_CR_POINTS];\n+\t__u8 point_cr_scaling[V4L2_AV1_MAX_NUM_CR_POINTS];\n+\t__u8 grain_scaling_minus_8;\n+\t__u8 ar_coeff_lag;\n+\t__u8 ar_coeffs_y_plus_128[V4L2_AV1_AR_COEFFS_SIZE];\n+\t__u8 ar_coeffs_cb_plus_128[V4L2_AV1_AR_COEFFS_SIZE];\n+\t__u8 ar_coeffs_cr_plus_128[V4L2_AV1_AR_COEFFS_SIZE];\n+\t__u8 ar_coeff_shift_minus_6;\n+\t__u8 grain_scale_shift;\n+\t__u8 cb_mult;\n+\t__u8 cb_luma_mult;\n+\t__u8 cr_luma_mult;\n+\t__u16 cb_offset;\n+\t__u16 cr_offset;\n+\t__u8 reserved[4];\n+};\n+\n /* MPEG-compression definitions kept for backwards compatibility */\n #define V4L2_CTRL_CLASS_MPEG V4L2_CTRL_CLASS_CODEC\n #define V4L2_CID_MPEG_CLASS V4L2_CID_CODEC_CLASS\ndiff --git a/include/linux/v4l2-mediabus.h b/include/linux/v4l2-mediabus.h\nindex 846dadfbfc64..2c318de10485 100644\n--- a/include/linux/v4l2-mediabus.h\n+++ b/include/linux/v4l2-mediabus.h\n@@ -3,10 +3,6 @@\n * Media Bus API header\n *\n * Copyright (C) 2009, Guennadi Liakhovetski \n- *\n- * This program is free software; you can redistribute it and/or modify\n- * it under the terms of the GNU General Public License version 2 as\n- * published by the Free Software Foundation.\n */\n \n #ifndef __LINUX_V4L2_MEDIABUS_H\ndiff --git a/include/linux/v4l2-subdev.h b/include/linux/v4l2-subdev.h\nindex 480891dba193..b383c2fe0cf3 100644\n--- a/include/linux/v4l2-subdev.h\n+++ b/include/linux/v4l2-subdev.h\n@@ -6,24 +6,12 @@\n *\n * Contacts: Laurent Pinchart \n *\t Sakari Ailus \n- *\n- * This program is free software; you can redistribute it and/or modify\n- * it under the terms of the GNU General Public License version 2 as\n- * published by the Free Software Foundation.\n- *\n- * This program is distributed in the hope that it will be useful,\n- * but WITHOUT ANY WARRANTY; without even the implied warranty of\n- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n- * GNU General Public License for more details.\n- *\n- * You should have received a copy of the GNU General Public License\n- * along with this program; if not, write to the Free Software\n- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\n */\n \n #ifndef __LINUX_V4L2_SUBDEV_H\n #define __LINUX_V4L2_SUBDEV_H\n \n+#include \n #include \n #include \n #include \n@@ -202,29 +190,14 @@ struct v4l2_subdev_capability {\n /* The v4l2 sub-device video device node is registered in read-only mode. */\n #define V4L2_SUBDEV_CAP_RO_SUBDEV\t\t0x00000001\n \n-/* The v4l2 sub-device supports multiplexed streams. */\n-#define V4L2_SUBDEV_CAP_MPLEXED\t\t\t0x00000002\n+/* The v4l2 sub-device supports routing and multiplexed streams. */\n+#define V4L2_SUBDEV_CAP_STREAMS\t\t\t0x00000002\n \n /*\n * Is the route active? An active route will start when streaming is enabled\n * on a video node.\n */\n-#define V4L2_SUBDEV_ROUTE_FL_ACTIVE\t\t_BITUL(0)\n-\n-/*\n- * Is the route immutable, i.e. can it be activated and inactivated?\n- * Set by the driver.\n- */\n-#define V4L2_SUBDEV_ROUTE_FL_IMMUTABLE\t\t_BITUL(1)\n-\n-/*\n- * Is the route a source endpoint? A source endpoint route refers to a stream\n- * generated internally by the subdevice (usually a sensor), and thus there\n- * is no sink-side endpoint for the route. The sink_pad and sink_stream\n- * fields are unused.\n- * Set by the driver.\n- */\n-#define V4L2_SUBDEV_ROUTE_FL_SOURCE\t\t_BITUL(2)\n+#define V4L2_SUBDEV_ROUTE_FL_ACTIVE\t\t(1U << 0)\n \n /**\n * struct v4l2_subdev_route - A route inside a subdev\n@@ -260,6 +233,24 @@ struct v4l2_subdev_routing {\n \t__u32 reserved[6];\n };\n \n+/*\n+ * The client is aware of streams. Setting this flag enables the use of 'stream'\n+ * fields (referring to the stream number) with various ioctls. If this is not\n+ * set (which is the default), the 'stream' fields will be forced to 0 by the\n+ * kernel.\n+ */\n+ #define V4L2_SUBDEV_CLIENT_CAP_STREAMS\t\t(1ULL << 0)\n+\n+/**\n+ * struct v4l2_subdev_client_capability - Capabilities of the client accessing\n+ *\t\t\t\t\t the subdev\n+ *\n+ * @capabilities: A bitmask of V4L2_SUBDEV_CLIENT_CAP_* flags.\n+ */\n+struct v4l2_subdev_client_capability {\n+\t__u64 capabilities;\n+};\n+\n /* Backwards compatibility define --- to be removed */\n #define v4l2_subdev_edid v4l2_edid\n \n@@ -277,6 +268,9 @@ struct v4l2_subdev_routing {\n #define VIDIOC_SUBDEV_S_SELECTION\t\t_IOWR('V', 62, struct v4l2_subdev_selection)\n #define VIDIOC_SUBDEV_G_ROUTING\t\t\t_IOWR('V', 38, struct v4l2_subdev_routing)\n #define VIDIOC_SUBDEV_S_ROUTING\t\t\t_IOWR('V', 39, struct v4l2_subdev_routing)\n+#define VIDIOC_SUBDEV_G_CLIENT_CAP\t\t_IOR('V', 101, struct v4l2_subdev_client_capability)\n+#define VIDIOC_SUBDEV_S_CLIENT_CAP\t\t_IOWR('V', 102, struct v4l2_subdev_client_capability)\n+\n /* The following ioctls are identical to the ioctls in videodev2.h */\n #define VIDIOC_SUBDEV_G_STD\t\t\t_IOR('V', 23, v4l2_std_id)\n #define VIDIOC_SUBDEV_S_STD\t\t\t_IOW('V', 24, v4l2_std_id)\ndiff --git a/include/linux/videodev2.h b/include/linux/videodev2.h\nindex bfb315d6d058..7e556911c9e1 100644\n--- a/include/linux/videodev2.h\n+++ b/include/linux/videodev2.h\n@@ -243,6 +243,7 @@ enum v4l2_colorspace {\n \n \t/* DCI-P3 colorspace, used by cinema projectors */\n \tV4L2_COLORSPACE_DCI_P3 = 12,\n+\n };\n \n /*\n@@ -474,7 +475,6 @@ struct v4l2_capability {\n #define V4L2_CAP_META_CAPTURE\t\t0x00800000 /* Is a metadata capture device */\n \n #define V4L2_CAP_READWRITE 0x01000000 /* read/write systemcalls */\n-#define V4L2_CAP_ASYNCIO 0x02000000 /* async I/O */\n #define V4L2_CAP_STREAMING 0x04000000 /* streaming I/O ioctls */\n #define V4L2_CAP_META_OUTPUT\t\t0x08000000 /* Is a metadata output device */\n \n@@ -549,6 +549,13 @@ struct v4l2_pix_format {\n #define V4L2_PIX_FMT_RGBX32 v4l2_fourcc('X', 'B', '2', '4') /* 32 RGBX-8-8-8-8 */\n #define V4L2_PIX_FMT_ARGB32 v4l2_fourcc('B', 'A', '2', '4') /* 32 ARGB-8-8-8-8 */\n #define V4L2_PIX_FMT_XRGB32 v4l2_fourcc('B', 'X', '2', '4') /* 32 XRGB-8-8-8-8 */\n+#define V4L2_PIX_FMT_RGBX1010102 v4l2_fourcc('R', 'X', '3', '0') /* 32 RGBX-10-10-10-2 */\n+#define V4L2_PIX_FMT_RGBA1010102 v4l2_fourcc('R', 'A', '3', '0') /* 32 RGBA-10-10-10-2 */\n+#define V4L2_PIX_FMT_ARGB2101010 v4l2_fourcc('A', 'R', '3', '0') /* 32 ARGB-2-10-10-10 */\n+\n+/* RGB formats (6 or 8 bytes per pixel) */\n+#define V4L2_PIX_FMT_BGR48_12 v4l2_fourcc('B', '3', '1', '2') /* 48 BGR 12-bit per component */\n+#define V4L2_PIX_FMT_ABGR64_12 v4l2_fourcc('B', '4', '1', '2') /* 64 BGRA 12-bit per component */\n \n /* Grey formats */\n #define V4L2_PIX_FMT_GREY v4l2_fourcc('G', 'R', 'E', 'Y') /* 8 Greyscale */\n@@ -556,6 +563,7 @@ struct v4l2_pix_format {\n #define V4L2_PIX_FMT_Y6 v4l2_fourcc('Y', '0', '6', ' ') /* 6 Greyscale */\n #define V4L2_PIX_FMT_Y10 v4l2_fourcc('Y', '1', '0', ' ') /* 10 Greyscale */\n #define V4L2_PIX_FMT_Y12 v4l2_fourcc('Y', '1', '2', ' ') /* 12 Greyscale */\n+#define V4L2_PIX_FMT_Y012 v4l2_fourcc('Y', '0', '1', '2') /* 12 Greyscale */\n #define V4L2_PIX_FMT_Y14 v4l2_fourcc('Y', '1', '4', ' ') /* 14 Greyscale */\n #define V4L2_PIX_FMT_Y16 v4l2_fourcc('Y', '1', '6', ' ') /* 16 Greyscale */\n #define V4L2_PIX_FMT_Y16_BE v4l2_fourcc_be('Y', '1', '6', ' ') /* 16 Greyscale BE */\n@@ -590,6 +598,15 @@ struct v4l2_pix_format {\n #define V4L2_PIX_FMT_YUVA32 v4l2_fourcc('Y', 'U', 'V', 'A') /* 32 YUVA-8-8-8-8 */\n #define V4L2_PIX_FMT_YUVX32 v4l2_fourcc('Y', 'U', 'V', 'X') /* 32 YUVX-8-8-8-8 */\n #define V4L2_PIX_FMT_M420 v4l2_fourcc('M', '4', '2', '0') /* 12 YUV 4:2:0 2 lines y, 1 line uv interleaved */\n+#define V4L2_PIX_FMT_YUV48_12 v4l2_fourcc('Y', '3', '1', '2') /* 48 YUV 4:4:4 12-bit per component */\n+\n+/*\n+ * YCbCr packed format. For each Y2xx format, xx bits of valid data occupy the MSBs\n+ * of the 16 bit components, and 16-xx bits of zero padding occupy the LSBs.\n+ */\n+#define V4L2_PIX_FMT_Y210 v4l2_fourcc('Y', '2', '1', '0') /* 32 YUYV 4:2:2 */\n+#define V4L2_PIX_FMT_Y212 v4l2_fourcc('Y', '2', '1', '2') /* 32 YUYV 4:2:2 */\n+#define V4L2_PIX_FMT_Y216 v4l2_fourcc('Y', '2', '1', '6') /* 32 YUYV 4:2:2 */\n \n /* two planes -- one Y, one Cr + Cb interleaved */\n #define V4L2_PIX_FMT_NV12 v4l2_fourcc('N', 'V', '1', '2') /* 12 Y/CbCr 4:2:0 */\n@@ -598,12 +615,15 @@ struct v4l2_pix_format {\n #define V4L2_PIX_FMT_NV61 v4l2_fourcc('N', 'V', '6', '1') /* 16 Y/CrCb 4:2:2 */\n #define V4L2_PIX_FMT_NV24 v4l2_fourcc('N', 'V', '2', '4') /* 24 Y/CbCr 4:4:4 */\n #define V4L2_PIX_FMT_NV42 v4l2_fourcc('N', 'V', '4', '2') /* 24 Y/CrCb 4:4:4 */\n+#define V4L2_PIX_FMT_P010 v4l2_fourcc('P', '0', '1', '0') /* 24 Y/CbCr 4:2:0 10-bit per component */\n+#define V4L2_PIX_FMT_P012 v4l2_fourcc('P', '0', '1', '2') /* 24 Y/CbCr 4:2:0 12-bit per component */\n \n /* two non contiguous planes - one Y, one Cr + Cb interleaved */\n #define V4L2_PIX_FMT_NV12M v4l2_fourcc('N', 'M', '1', '2') /* 12 Y/CbCr 4:2:0 */\n #define V4L2_PIX_FMT_NV21M v4l2_fourcc('N', 'M', '2', '1') /* 21 Y/CrCb 4:2:0 */\n #define V4L2_PIX_FMT_NV16M v4l2_fourcc('N', 'M', '1', '6') /* 16 Y/CbCr 4:2:2 */\n #define V4L2_PIX_FMT_NV61M v4l2_fourcc('N', 'M', '6', '1') /* 16 Y/CrCb 4:2:2 */\n+#define V4L2_PIX_FMT_P012M v4l2_fourcc('P', 'M', '1', '2') /* 24 Y/CbCr 4:2:0 12-bit per component */\n \n /* three planes - Y Cb, Cr */\n #define V4L2_PIX_FMT_YUV410 v4l2_fourcc('Y', 'U', 'V', '9') /* 9 YUV 4:1:0 */\n@@ -625,6 +645,10 @@ struct v4l2_pix_format {\n #define V4L2_PIX_FMT_NV12_4L4 v4l2_fourcc('V', 'T', '1', '2') /* 12 Y/CbCr 4:2:0 4x4 tiles */\n #define V4L2_PIX_FMT_NV12_16L16 v4l2_fourcc('H', 'M', '1', '2') /* 12 Y/CbCr 4:2:0 16x16 tiles */\n #define V4L2_PIX_FMT_NV12_32L32 v4l2_fourcc('S', 'T', '1', '2') /* 12 Y/CbCr 4:2:0 32x32 tiles */\n+#define V4L2_PIX_FMT_NV15_4L4 v4l2_fourcc('V', 'T', '1', '5') /* 15 Y/CbCr 4:2:0 10-bit 4x4 tiles */\n+#define V4L2_PIX_FMT_P010_4L4 v4l2_fourcc('T', '0', '1', '0') /* 12 Y/CbCr 4:2:0 10-bit 4x4 macroblocks */\n+#define V4L2_PIX_FMT_NV12_8L128 v4l2_fourcc('A', 'T', '1', '2') /* Y/CbCr 4:2:0 8x128 tiles */\n+#define V4L2_PIX_FMT_NV12_10BE_8L128 v4l2_fourcc_be('A', 'X', '1', '2') /* Y/CbCr 4:2:0 10-bit 8x128 tiles */\n \n /* Tiled YUV formats, non contiguous planes */\n #define V4L2_PIX_FMT_NV12MT v4l2_fourcc('T', 'M', '1', '2') /* 12 Y/CbCr 4:2:0 64x32 tiles */\n@@ -707,6 +731,11 @@ struct v4l2_pix_format {\n #define V4L2_PIX_FMT_FWHT v4l2_fourcc('F', 'W', 'H', 'T') /* Fast Walsh Hadamard Transform (vicodec) */\n #define V4L2_PIX_FMT_FWHT_STATELESS v4l2_fourcc('S', 'F', 'W', 'H') /* Stateless FWHT (vicodec) */\n #define V4L2_PIX_FMT_H264_SLICE v4l2_fourcc('S', '2', '6', '4') /* H264 parsed slices */\n+#define V4L2_PIX_FMT_HEVC_SLICE v4l2_fourcc('S', '2', '6', '5') /* HEVC parsed slices */\n+#define V4L2_PIX_FMT_AV1_FRAME v4l2_fourcc('A', 'V', '1', 'F') /* AV1 parsed frame */\n+#define V4L2_PIX_FMT_SPK v4l2_fourcc('S', 'P', 'K', '0') /* Sorenson Spark */\n+#define V4L2_PIX_FMT_RV30 v4l2_fourcc('R', 'V', '3', '0') /* RealVideo 8 */\n+#define V4L2_PIX_FMT_RV40 v4l2_fourcc('R', 'V', '4', '0') /* RealVideo 9 & 10 */\n \n /* Vendor-specific formats */\n #define V4L2_PIX_FMT_CPIA1 v4l2_fourcc('C', 'P', 'I', 'A') /* cpia1 YUV */\n@@ -740,11 +769,15 @@ struct v4l2_pix_format {\n #define V4L2_PIX_FMT_Z16 v4l2_fourcc('Z', '1', '6', ' ') /* Depth data 16-bit */\n #define V4L2_PIX_FMT_MT21C v4l2_fourcc('M', 'T', '2', '1') /* Mediatek compressed block mode */\n #define V4L2_PIX_FMT_MM21 v4l2_fourcc('M', 'M', '2', '1') /* Mediatek 8-bit block mode, two non-contiguous planes */\n+#define V4L2_PIX_FMT_MT2110T v4l2_fourcc('M', 'T', '2', 'T') /* Mediatek 10-bit block tile mode */\n+#define V4L2_PIX_FMT_MT2110R v4l2_fourcc('M', 'T', '2', 'R') /* Mediatek 10-bit block raster mode */\n #define V4L2_PIX_FMT_INZI v4l2_fourcc('I', 'N', 'Z', 'I') /* Intel Planar Greyscale 10-bit and Depth 16-bit */\n #define V4L2_PIX_FMT_CNF4 v4l2_fourcc('C', 'N', 'F', '4') /* Intel 4-bit packed depth confidence information */\n #define V4L2_PIX_FMT_HI240 v4l2_fourcc('H', 'I', '2', '4') /* BTTV 8-bit dithered RGB */\n #define V4L2_PIX_FMT_QC08C v4l2_fourcc('Q', '0', '8', 'C') /* Qualcomm 8-bit compressed */\n #define V4L2_PIX_FMT_QC10C v4l2_fourcc('Q', '1', '0', 'C') /* Qualcomm 10-bit compressed */\n+#define V4L2_PIX_FMT_AJPG v4l2_fourcc('A', 'J', 'P', 'G') /* Aspeed JPEG */\n+#define V4L2_PIX_FMT_HEXTILE v4l2_fourcc('H', 'X', 'T', 'L') /* Hextile compressed */\n \n /* 10bit raw packed, 32 bytes for every 25 pixels, last LSB 6 bits unused */\n #define V4L2_PIX_FMT_IPU3_SBGGR10\tv4l2_fourcc('i', 'p', '3', 'b') /* IPU3 packed 10-bit BGGR bayer */\n@@ -1550,7 +1583,8 @@ struct v4l2_bt_timings {\n \t((bt)->width + V4L2_DV_BT_BLANKING_WIDTH(bt))\n #define V4L2_DV_BT_BLANKING_HEIGHT(bt) \\\n \t((bt)->vfrontporch + (bt)->vsync + (bt)->vbackporch + \\\n-\t (bt)->il_vfrontporch + (bt)->il_vsync + (bt)->il_vbackporch)\n+\t ((bt)->interlaced ? \\\n+\t ((bt)->il_vfrontporch + (bt)->il_vsync + (bt)->il_vbackporch) : 0))\n #define V4L2_DV_BT_FRAME_HEIGHT(bt) \\\n \t((bt)->height + V4L2_DV_BT_BLANKING_HEIGHT(bt))\n \n@@ -1641,7 +1675,7 @@ struct v4l2_input {\n \t__u8\t name[32];\t\t/* Label */\n \t__u32\t type;\t\t/* Type of input */\n \t__u32\t audioset;\t\t/* Associated audios (bitfield) */\n-\t__u32 tuner; /* enum v4l2_tuner_type */\n+\t__u32 tuner; /* Tuner index */\n \tv4l2_std_id std;\n \t__u32\t status;\n \t__u32\t capabilities;\n@@ -1728,6 +1762,8 @@ struct v4l2_ext_control {\n \t\t__u8 *p_u8;\n \t\t__u16 *p_u16;\n \t\t__u32 *p_u32;\n+\t\t__s32 *p_s32;\n+\t\t__s64 *p_s64;\n \t\tstruct v4l2_area *p_area;\n \t\tstruct v4l2_ctrl_h264_sps *p_h264_sps;\n \t\tstruct v4l2_ctrl_h264_pps *p_h264_pps;\n@@ -1742,6 +1778,15 @@ struct v4l2_ext_control {\n \t\tstruct v4l2_ctrl_mpeg2_quantisation *p_mpeg2_quantisation;\n \t\tstruct v4l2_ctrl_vp9_compressed_hdr *p_vp9_compressed_hdr_probs;\n \t\tstruct v4l2_ctrl_vp9_frame *p_vp9_frame;\n+\t\tstruct v4l2_ctrl_hevc_sps *p_hevc_sps;\n+\t\tstruct v4l2_ctrl_hevc_pps *p_hevc_pps;\n+\t\tstruct v4l2_ctrl_hevc_slice_params *p_hevc_slice_params;\n+\t\tstruct v4l2_ctrl_hevc_scaling_matrix *p_hevc_scaling_matrix;\n+\t\tstruct v4l2_ctrl_hevc_decode_params *p_hevc_decode_params;\n+\t\tstruct v4l2_ctrl_av1_sequence *p_av1_sequence;\n+\t\tstruct v4l2_ctrl_av1_tile_group_entry *p_av1_tile_group_entry;\n+\t\tstruct v4l2_ctrl_av1_frame *p_av1_frame;\n+\t\tstruct v4l2_ctrl_av1_film_grain *p_av1_film_grain;\n \t\tvoid *ptr;\n \t};\n } __attribute__ ((packed));\n@@ -1805,6 +1850,17 @@ enum v4l2_ctrl_type {\n \n \tV4L2_CTRL_TYPE_VP9_COMPRESSED_HDR\t= 0x0260,\n \tV4L2_CTRL_TYPE_VP9_FRAME\t\t= 0x0261,\n+\n+\tV4L2_CTRL_TYPE_HEVC_SPS\t\t\t= 0x0270,\n+\tV4L2_CTRL_TYPE_HEVC_PPS\t\t\t= 0x0271,\n+\tV4L2_CTRL_TYPE_HEVC_SLICE_PARAMS\t= 0x0272,\n+\tV4L2_CTRL_TYPE_HEVC_SCALING_MATRIX\t= 0x0273,\n+\tV4L2_CTRL_TYPE_HEVC_DECODE_PARAMS\t= 0x0274,\n+\n+\tV4L2_CTRL_TYPE_AV1_SEQUENCE\t = 0x280,\n+\tV4L2_CTRL_TYPE_AV1_TILE_GROUP_ENTRY = 0x281,\n+\tV4L2_CTRL_TYPE_AV1_FRAME\t = 0x282,\n+\tV4L2_CTRL_TYPE_AV1_FILM_GRAIN\t = 0x283,\n };\n \n /* Used in the VIDIOC_QUERYCTRL ioctl for querying controls */\n@@ -1860,6 +1916,7 @@ struct v4l2_querymenu {\n #define V4L2_CTRL_FLAG_HAS_PAYLOAD\t0x0100\n #define V4L2_CTRL_FLAG_EXECUTE_ON_WRITE\t0x0200\n #define V4L2_CTRL_FLAG_MODIFY_LAYOUT\t0x0400\n+#define V4L2_CTRL_FLAG_DYNAMIC_ARRAY\t0x0800\n \n /* Query flags, to be ORed with the control ID */\n #define V4L2_CTRL_FLAG_NEXT_CTRL\t0x80000000\n@@ -2367,6 +2424,7 @@ struct v4l2_event_vsync {\n #define V4L2_EVENT_CTRL_CH_VALUE\t\t(1 << 0)\n #define V4L2_EVENT_CTRL_CH_FLAGS\t\t(1 << 1)\n #define V4L2_EVENT_CTRL_CH_RANGE\t\t(1 << 2)\n+#define V4L2_EVENT_CTRL_CH_DIMENSIONS\t\t(1 << 3)\n \n struct v4l2_event_ctrl {\n \t__u32 changes;\n@@ -2609,5 +2667,10 @@ struct v4l2_create_buffers {\n /* Deprecated definitions kept for backwards compatibility */\n #define V4L2_PIX_FMT_HM12 V4L2_PIX_FMT_NV12_16L16\n #define V4L2_PIX_FMT_SUNXI_TILED_NV12 V4L2_PIX_FMT_NV12_32L32\n+/*\n+ * This capability was never implemented, anyone using this cap should drop it\n+ * from their code.\n+ */\n+#define V4L2_CAP_ASYNCIO 0x02000000\n \n #endif /* __LINUX_VIDEODEV2_H */\n","prefixes":["libcamera-devel","1/2"]}