[{"id":15452,"web_url":"https://patchwork.libcamera.org/comment/15452/","msgid":"<4edf6bbd-0328-7823-7122-474e94b81072@ideasonboard.com>","date":"2021-03-03T16:31:50","subject":"Re: [libcamera-devel] [PATCH 1/2] include: linux: Update Linux\n\theaders to v5.12-rc1","submitter":{"id":4,"url":"https://patchwork.libcamera.org/api/people/4/","name":"Kieran Bingham","email":"kieran.bingham@ideasonboard.com"},"content":"Hi Laurent,\n\nOn 02/03/2021 20:16, Laurent Pinchart wrote:\n> Update Linux headers to v5.12-rc1, to provide the\n> MEDIA_ENT_F_PROC_VIDEO_ISP entity function.\n> \n> The DRM FourCC and modifiers that were manually added in commits\n> 9db0ed5e2065, 38f2efb05cef and 90c793c6989f are kept. New Intel DRM\n> format modifiers are conflicting with IPU3_FORMAT_MOD_PACKED, which is\n> updated as a result.\n> \n> The V4L2 controls and formats that were manually added in commit\n> 43d81d43fe91 are kept. This causes a conflict in the V4L2 control base\n> for V4L2_CID_USER_BCM2835_ISP_BASE that needs to be resolved in the\n> downstream Raspberry Pi kernel first.\n> \n> The intel-ipu3.h header is manually exported with the\n> scripts/headers_install.sh script. The script complained about a missing\n> \"WITH Linux-syscall-note\" license extension, which has been worked\n> around manually. The issue has been reported upstream in [1].\n> \n> [1] https://lore.kernel.org/linux-media/20210207235610.15687-1-laurent.pinchart@ideasonboard.com/T/#u\n> \n> Signed-off-by: Laurent Pinchart \n\nThat's a lot of churn, so it's hard to review precisely. Perhaps we\nshould try to do this every kernel release to minimise the changes.\n\nAcked-by: Kieran Bingham \n\n> ---\n> include/linux/dma-heap.h | 6 +-\n> include/linux/drm_fourcc.h | 530 +++++++++++++++++-\n> include/linux/intel-ipu3.h | 22 +-\n> include/linux/media-bus-format.h | 14 +-\n> include/linux/media.h | 1 +\n> include/linux/rkisp1-config.h | 92 +++-\n> include/linux/v4l2-controls.h | 916 ++++++++++++++++++++++++-------\n> include/linux/v4l2-mediabus.h | 15 +-\n> include/linux/v4l2-subdev.h | 26 +-\n> include/linux/videodev2.h | 99 +++-\n> 10 files changed, 1444 insertions(+), 277 deletions(-)\n> \n> diff --git a/include/linux/dma-heap.h b/include/linux/dma-heap.h\n> index 6f84fa08e074..96b90cf0f8f7 100644\n> --- a/include/linux/dma-heap.h\n> +++ b/include/linux/dma-heap.h\n> @@ -5,8 +5,8 @@\n> * Copyright (C) 2011 Google, Inc.\n> * Copyright (C) 2019 Linaro Ltd.\n> */\n> -#ifndef _UAPI_LINUX_DMABUF_POOL_H\n> -#define _UAPI_LINUX_DMABUF_POOL_H\n> +#ifndef _LINUX_DMABUF_POOL_H\n> +#define _LINUX_DMABUF_POOL_H\n> \n> #include \n> #include \n> @@ -50,4 +50,4 @@ struct dma_heap_allocation_data {\n> #define DMA_HEAP_IOCTL_ALLOC\t_IOWR(DMA_HEAP_IOC_MAGIC, 0x0,\\\n> \t\t\t\t struct dma_heap_allocation_data)\n> \n> -#endif /* _UAPI_LINUX_DMABUF_POOL_H */\n> +#endif /* _LINUX_DMABUF_POOL_H */\n> diff --git a/include/linux/drm_fourcc.h b/include/linux/drm_fourcc.h\n> index 72453692bdef..05d697ff30ce 100644\n> --- a/include/linux/drm_fourcc.h\n> +++ b/include/linux/drm_fourcc.h\n> @@ -58,6 +58,30 @@ extern \"C\" {\n> * may preserve meaning - such as number of planes - from the fourcc code,\n> * whereas others may not.\n> *\n> + * Modifiers must uniquely encode buffer layout. In other words, a buffer must\n> + * match only a single modifier. A modifier must not be a subset of layouts of\n> + * another modifier. For instance, it's incorrect to encode pitch alignment in\n> + * a modifier: a buffer may match a 64-pixel aligned modifier and a 32-pixel\n> + * aligned modifier. That said, modifiers can have implicit minimal\n> + * requirements.\n> + *\n> + * For modifiers where the combination of fourcc code and modifier can alias,\n> + * a canonical pair needs to be defined and used by all drivers. Preferred\n> + * combinations are also encouraged where all combinations might lead to\n> + * confusion and unnecessarily reduced interoperability. An example for the\n> + * latter is AFBC, where the ABGR layouts are preferred over ARGB layouts.\n> + *\n> + * There are two kinds of modifier users:\n> + *\n> + * - Kernel and user-space drivers: for drivers it's important that modifiers\n> + * don't alias, otherwise two drivers might support the same format but use\n> + * different aliases, preventing them from sharing buffers in an efficient\n> + * format.\n> + * - Higher-level programs interfacing with KMS/GBM/EGL/Vulkan/etc: these users\n> + * see modifiers as opaque tokens they can check for equality and intersect.\n> + * These users musn't need to know to reason about the modifier value\n> + * (i.e. they are not expected to extract information out of the modifier).\n> + *\n> * Vendors should document their modifier usage in as much detail as\n> * possible, to ensure maximum compatibility across devices, drivers and\n> * applications.\n> @@ -69,7 +93,7 @@ extern \"C\" {\n> #define fourcc_code(a, b, c, d) ((__u32)(a) | ((__u32)(b) << 8) | \\\n> \t\t\t\t ((__u32)(c) << 16) | ((__u32)(d) << 24))\n> \n> -#define DRM_FORMAT_BIG_ENDIAN (1<<31) /* format is big endian instead of little endian */\n> +#define DRM_FORMAT_BIG_ENDIAN (1U<<31) /* format is big endian instead of little endian */\n> \n> /* Reserve 0 for the invalid format specifier */\n> #define DRM_FORMAT_INVALID\t0\n> @@ -155,6 +179,12 @@ extern \"C\" {\n> #define DRM_FORMAT_ARGB16161616F fourcc_code('A', 'R', '4', 'H') /* [63:0] A:R:G:B 16:16:16:16 little endian */\n> #define DRM_FORMAT_ABGR16161616F fourcc_code('A', 'B', '4', 'H') /* [63:0] A:B:G:R 16:16:16:16 little endian */\n> \n> +/*\n> + * RGBA format with 10-bit components packed in 64-bit per pixel, with 6 bits\n> + * of unused padding per component:\n> + */\n> +#define DRM_FORMAT_AXBXGXRX106106106106 fourcc_code('A', 'B', '1', '0') /* [63:0] A:x:B:x:G:x:R:x 10:6:10:6:10:6:10:6 little endian */\n> +\n> /* packed YCbCr */\n> #define DRM_FORMAT_YUYV\t\tfourcc_code('Y', 'U', 'Y', 'V') /* [31:0] Cr0:Y1:Cb0:Y0 8:8:8:8 little endian */\n> #define DRM_FORMAT_YVYU\t\tfourcc_code('Y', 'V', 'Y', 'U') /* [31:0] Cb0:Y1:Cr0:Y0 8:8:8:8 little endian */\n> @@ -236,6 +266,12 @@ extern \"C\" {\n> #define DRM_FORMAT_NV61\t\tfourcc_code('N', 'V', '6', '1') /* 2x1 subsampled Cb:Cr plane */\n> #define DRM_FORMAT_NV24\t\tfourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */\n> #define DRM_FORMAT_NV42\t\tfourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */\n> +/*\n> + * 2 plane YCbCr\n> + * index 0 = Y plane, [39:0] Y3:Y2:Y1:Y0 little endian\n> + * index 1 = Cr:Cb plane, [39:0] Cr1:Cb1:Cr0:Cb0 little endian\n> + */\n> +#define DRM_FORMAT_NV15\t\tfourcc_code('N', 'V', '1', '5') /* 2x2 subsampled Cr:Cb plane */\n> \n> /*\n> * 2 plane YCbCr MSB aligned\n> @@ -265,6 +301,22 @@ extern \"C\" {\n> */\n> #define DRM_FORMAT_P016\t\tfourcc_code('P', '0', '1', '6') /* 2x2 subsampled Cr:Cb plane 16 bits per channel */\n> \n> +/* 3 plane non-subsampled (444) YCbCr\n> + * 16 bits per component, but only 10 bits are used and 6 bits are padded\n> + * index 0: Y plane, [15:0] Y:x [10:6] little endian\n> + * index 1: Cb plane, [15:0] Cb:x [10:6] little endian\n> + * index 2: Cr plane, [15:0] Cr:x [10:6] little endian\n> + */\n> +#define DRM_FORMAT_Q410\t\tfourcc_code('Q', '4', '1', '0')\n> +\n> +/* 3 plane non-subsampled (444) YCrCb\n> + * 16 bits per component, but only 10 bits are used and 6 bits are padded\n> + * index 0: Y plane, [15:0] Y:x [10:6] little endian\n> + * index 1: Cr plane, [15:0] Cr:x [10:6] little endian\n> + * index 2: Cb plane, [15:0] Cb:x [10:6] little endian\n> + */\n> +#define DRM_FORMAT_Q401\t\tfourcc_code('Q', '4', '0', '1')\n> +\n> /*\n> * 3 plane YCbCr\n> * index 0: Y plane, [7:0] Y\n> @@ -362,7 +414,6 @@ extern \"C\" {\n> */\n> \n> /* Vendor Ids: */\n> -#define DRM_FORMAT_MOD_NONE 0\n> #define DRM_FORMAT_MOD_VENDOR_NONE 0\n> #define DRM_FORMAT_MOD_VENDOR_INTEL 0x01\n> #define DRM_FORMAT_MOD_VENDOR_AMD 0x02\n> @@ -373,7 +424,8 @@ extern \"C\" {\n> #define DRM_FORMAT_MOD_VENDOR_BROADCOM 0x07\n> #define DRM_FORMAT_MOD_VENDOR_ARM 0x08\n> #define DRM_FORMAT_MOD_VENDOR_ALLWINNER 0x09\n> -#define DRM_FORMAT_MOD_VENDOR_MIPI 0x0a\n> +#define DRM_FORMAT_MOD_VENDOR_AMLOGIC 0x0a\n> +#define DRM_FORMAT_MOD_VENDOR_MIPI 0x0b\n> \n> /* add more to the end as needed */\n> \n> @@ -388,8 +440,33 @@ extern \"C\" {\n> * When adding a new token please document the layout with a code comment,\n> * similar to the fourcc codes above. drm_fourcc.h is considered the\n> * authoritative source for all of these.\n> + *\n> + * Generic modifier names:\n> + *\n> + * DRM_FORMAT_MOD_GENERIC_* definitions are used to provide vendor-neutral names\n> + * for layouts which are common across multiple vendors. To preserve\n> + * compatibility, in cases where a vendor-specific definition already exists and\n> + * a generic name for it is desired, the common name is a purely symbolic alias\n> + * and must use the same numerical value as the original definition.\n> + *\n> + * Note that generic names should only be used for modifiers which describe\n> + * generic layouts (such as pixel re-ordering), which may have\n> + * independently-developed support across multiple vendors.\n> + *\n> + * In future cases where a generic layout is identified before merging with a\n> + * vendor-specific modifier, a new 'GENERIC' vendor or modifier using vendor\n> + * 'NONE' could be considered. This should only be for obvious, exceptional\n> + * cases to avoid polluting the 'GENERIC' namespace with modifiers which only\n> + * apply to a single vendor.\n> + *\n> + * Generic names should not be used for cases where multiple hardware vendors\n> + * have implementations of the same standardised compression scheme (such as\n> + * AFBC). In those cases, all implementations should use the same format\n> + * modifier(s), reflecting the vendor of the standard.\n> */\n> \n> +#define DRM_FORMAT_MOD_GENERIC_16_16_TILE DRM_FORMAT_MOD_SAMSUNG_16_16_TILE\n> +\n> /*\n> * Invalid Modifier\n> *\n> @@ -409,6 +486,16 @@ extern \"C\" {\n> */\n> #define DRM_FORMAT_MOD_LINEAR\tfourcc_mod_code(NONE, 0)\n> \n> +/*\n> + * Deprecated: use DRM_FORMAT_MOD_LINEAR instead\n> + *\n> + * The \"none\" format modifier doesn't actually mean that the modifier is\n> + * implicit, instead it means that the layout is linear. Whether modifiers are\n> + * used is out-of-band information carried in an API-specific way (e.g. in a\n> + * flag for drm_mode_fb_cmd2).\n> + */\n> +#define DRM_FORMAT_MOD_NONE\t0\n> +\n> /* Intel framebuffer modifiers */\n> \n> /*\n> @@ -419,9 +506,12 @@ extern \"C\" {\n> * a platform-dependent stride. On top of that the memory can apply\n> * platform-depending swizzling of some higher address bits into bit6.\n> *\n> - * This format is highly platforms specific and not useful for cross-driver\n> - * sharing. It exists since on a given platform it does uniquely identify the\n> - * layout in a simple way for i915-specific userspace.\n> + * Note that this layout is only accurate on intel gen 8+ or valleyview chipsets.\n> + * On earlier platforms the is highly platforms specific and not useful for\n> + * cross-driver sharing. It exists since on a given platform it does uniquely\n> + * identify the layout in a simple way for i915-specific userspace, which\n> + * facilitated conversion of userspace to modifiers. Additionally the exact\n> + * format on some really old platforms is not known.\n> */\n> #define I915_FORMAT_MOD_X_TILED\tfourcc_mod_code(INTEL, 1)\n> \n> @@ -434,9 +524,12 @@ extern \"C\" {\n> * memory can apply platform-depending swizzling of some higher address bits\n> * into bit6.\n> *\n> - * This format is highly platforms specific and not useful for cross-driver\n> - * sharing. It exists since on a given platform it does uniquely identify the\n> - * layout in a simple way for i915-specific userspace.\n> + * Note that this layout is only accurate on intel gen 8+ or valleyview chipsets.\n> + * On earlier platforms the is highly platforms specific and not useful for\n> + * cross-driver sharing. It exists since on a given platform it does uniquely\n> + * identify the layout in a simple way for i915-specific userspace, which\n> + * facilitated conversion of userspace to modifiers. Additionally the exact\n> + * format on some really old platforms is not known.\n> */\n> #define I915_FORMAT_MOD_Y_TILED\tfourcc_mod_code(INTEL, 2)\n> \n> @@ -475,6 +568,49 @@ extern \"C\" {\n> #define I915_FORMAT_MOD_Y_TILED_CCS\tfourcc_mod_code(INTEL, 4)\n> #define I915_FORMAT_MOD_Yf_TILED_CCS\tfourcc_mod_code(INTEL, 5)\n> \n> +/*\n> + * Intel color control surfaces (CCS) for Gen-12 render compression.\n> + *\n> + * The main surface is Y-tiled and at plane index 0, the CCS is linear and\n> + * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in\n> + * main surface. In other words, 4 bits in CCS map to a main surface cache\n> + * line pair. The main surface pitch is required to be a multiple of four\n> + * Y-tile widths.\n> + */\n> +#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6)\n> +\n> +/*\n> + * Intel color control surfaces (CCS) for Gen-12 media compression\n> + *\n> + * The main surface is Y-tiled and at plane index 0, the CCS is linear and\n> + * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in\n> + * main surface. In other words, 4 bits in CCS map to a main surface cache\n> + * line pair. The main surface pitch is required to be a multiple of four\n> + * Y-tile widths. For semi-planar formats like NV12, CCS planes follow the\n> + * Y and UV planes i.e., planes 0 and 1 are used for Y and UV surfaces,\n> + * planes 2 and 3 for the respective CCS.\n> + */\n> +#define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7)\n> +\n> +/*\n> + * Intel Color Control Surface with Clear Color (CCS) for Gen-12 render\n> + * compression.\n> + *\n> + * The main surface is Y-tiled and is at plane index 0 whereas CCS is linear\n> + * and at index 1. The clear color is stored at index 2, and the pitch should\n> + * be ignored. The clear color structure is 256 bits. The first 128 bits\n> + * represents Raw Clear Color Red, Green, Blue and Alpha color each represented\n> + * by 32 bits. The raw clear color is consumed by the 3d engine and generates\n> + * the converted clear color of size 64 bits. The first 32 bits store the Lower\n> + * Converted Clear Color value and the next 32 bits store the Higher Converted\n> + * Clear Color value when applicable. The Converted Clear Color values are\n> + * consumed by the DE. The last 64 bits are used to store Color Discard Enable\n> + * and Depth Clear Value Valid which are ignored by the DE. A CCS cache line\n> + * corresponds to an area of 4x1 tiles in the main surface. The main surface\n> + * pitch is required to be a multiple of 4 tile widths.\n> + */\n> +#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)\n> +\n> /*\n> * IPU3 Bayer packing layout\n> *\n> @@ -483,7 +619,7 @@ extern \"C\" {\n> * the 6 most significant bits in the last byte unused. The format is little\n> * endian.\n> */\n> -#define IPU3_FORMAT_MOD_PACKED fourcc_mod_code(INTEL, 8)\n> +#define IPU3_FORMAT_MOD_PACKED fourcc_mod_code(INTEL, 9)\n> \n> /*\n> * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks\n> @@ -572,7 +708,113 @@ extern \"C\" {\n> #define DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED fourcc_mod_code(NVIDIA, 1)\n> \n> /*\n> - * 16Bx2 Block Linear layout, used by desktop GPUs, and Tegra K1 and later\n> + * Generalized Block Linear layout, used by desktop GPUs starting with NV50/G80,\n> + * and Tegra GPUs starting with Tegra K1.\n> + *\n> + * Pixels are arranged in Groups of Bytes (GOBs). GOB size and layout varies\n> + * based on the architecture generation. GOBs themselves are then arranged in\n> + * 3D blocks, with the block dimensions (in terms of GOBs) always being a power\n> + * of two, and hence expressible as their log2 equivalent (E.g., \"2\" represents\n> + * a block depth or height of \"4\").\n> + *\n> + * Chapter 20 \"Pixel Memory Formats\" of the Tegra X1 TRM describes this format\n> + * in full detail.\n> + *\n> + * Macro\n> + * Bits Param Description\n> + * ---- ----- -----------------------------------------------------------------\n> + *\n> + * 3:0 h log2(height) of each block, in GOBs. Placed here for\n> + * compatibility with the existing\n> + * DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers.\n> + *\n> + * 4:4 - Must be 1, to indicate block-linear layout. Necessary for\n> + * compatibility with the existing\n> + * DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers.\n> + *\n> + * 8:5 - Reserved (To support 3D-surfaces with variable log2(depth) block\n> + * size). Must be zero.\n> + *\n> + * Note there is no log2(width) parameter. Some portions of the\n> + * hardware support a block width of two gobs, but it is impractical\n> + * to use due to lack of support elsewhere, and has no known\n> + * benefits.\n> + *\n> + * 11:9 - Reserved (To support 2D-array textures with variable array stride\n> + * in blocks, specified via log2(tile width in blocks)). Must be\n> + * zero.\n> + *\n> + * 19:12 k Page Kind. This value directly maps to a field in the page\n> + * tables of all GPUs >= NV50. It affects the exact layout of bits\n> + * in memory and can be derived from the tuple\n> + *\n> + * (format, GPU model, compression type, samples per pixel)\n> + *\n> + * Where compression type is defined below. If GPU model were\n> + * implied by the format modifier, format, or memory buffer, page\n> + * kind would not need to be included in the modifier itself, but\n> + * since the modifier should define the layout of the associated\n> + * memory buffer independent from any device or other context, it\n> + * must be included here.\n> + *\n> + * 21:20 g GOB Height and Page Kind Generation. The height of a GOB changed\n> + * starting with Fermi GPUs. Additionally, the mapping between page\n> + * kind and bit layout has changed at various points.\n> + *\n> + * 0 = Gob Height 8, Fermi - Volta, Tegra K1+ Page Kind mapping\n> + * 1 = Gob Height 4, G80 - GT2XX Page Kind mapping\n> + * 2 = Gob Height 8, Turing+ Page Kind mapping\n> + * 3 = Reserved for future use.\n> + *\n> + * 22:22 s Sector layout. On Tegra GPUs prior to Xavier, there is a further\n> + * bit remapping step that occurs at an even lower level than the\n> + * page kind and block linear swizzles. This causes the layout of\n> + * surfaces mapped in those SOC's GPUs to be incompatible with the\n> + * equivalent mapping on other GPUs in the same system.\n> + *\n> + * 0 = Tegra K1 - Tegra Parker/TX2 Layout.\n> + * 1 = Desktop GPU and Tegra Xavier+ Layout\n> + *\n> + * 25:23 c Lossless Framebuffer Compression type.\n> + *\n> + * 0 = none\n> + * 1 = ROP/3D, layout 1, exact compression format implied by Page\n> + * Kind field\n> + * 2 = ROP/3D, layout 2, exact compression format implied by Page\n> + * Kind field\n> + * 3 = CDE horizontal\n> + * 4 = CDE vertical\n> + * 5 = Reserved for future use\n> + * 6 = Reserved for future use\n> + * 7 = Reserved for future use\n> + *\n> + * 55:25 - Reserved for future use. Must be zero.\n> + */\n> +#define DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(c, s, g, k, h) \\\n> +\tfourcc_mod_code(NVIDIA, (0x10 | \\\n> +\t\t\t\t ((h) & 0xf) | \\\n> +\t\t\t\t (((k) & 0xff) << 12) | \\\n> +\t\t\t\t (((g) & 0x3) << 20) | \\\n> +\t\t\t\t (((s) & 0x1) << 22) | \\\n> +\t\t\t\t (((c) & 0x7) << 23)))\n> +\n> +/* To grandfather in prior block linear format modifiers to the above layout,\n> + * the page kind \"0\", which corresponds to \"pitch/linear\" and hence is unusable\n> + * with block-linear layouts, is remapped within drivers to the value 0xfe,\n> + * which corresponds to the \"generic\" kind used for simple single-sample\n> + * uncompressed color formats on Fermi - Volta GPUs.\n> + */\n> +static __inline__ __u64\n> +drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier)\n> +{\n> +\tif (!(modifier & 0x10) || (modifier & (0xff << 12)))\n> +\t\treturn modifier;\n> +\telse\n> +\t\treturn modifier | (0xfe << 12);\n> +}\n> +\n> +/*\n> + * 16Bx2 Block Linear layout, used by Tegra K1 and later\n> *\n> * Pixels are arranged in 64x8 Groups Of Bytes (GOBs). GOBs are then stacked\n> * vertically by a power of 2 (1 to 32 GOBs) to form a block.\n> @@ -593,20 +835,20 @@ extern \"C\" {\n> * in full detail.\n> */\n> #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(v) \\\n> -\tfourcc_mod_code(NVIDIA, 0x10 | ((v) & 0xf))\n> +\tDRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 0, 0, 0, (v))\n> \n> #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_ONE_GOB \\\n> -\tfourcc_mod_code(NVIDIA, 0x10)\n> +\tDRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(0)\n> #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_TWO_GOB \\\n> -\tfourcc_mod_code(NVIDIA, 0x11)\n> +\tDRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(1)\n> #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_FOUR_GOB \\\n> -\tfourcc_mod_code(NVIDIA, 0x12)\n> +\tDRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(2)\n> #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_EIGHT_GOB \\\n> -\tfourcc_mod_code(NVIDIA, 0x13)\n> +\tDRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(3)\n> #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_SIXTEEN_GOB \\\n> -\tfourcc_mod_code(NVIDIA, 0x14)\n> +\tDRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(4)\n> #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_THIRTYTWO_GOB \\\n> -\tfourcc_mod_code(NVIDIA, 0x15)\n> +\tDRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(5)\n> \n> /*\n> * Some Broadcom modifiers take parameters, for example the number of\n> @@ -723,7 +965,21 @@ extern \"C\" {\n> * Further information on the use of AFBC modifiers can be found in\n> * Documentation/gpu/afbc.rst\n> */\n> -#define DRM_FORMAT_MOD_ARM_AFBC(__afbc_mode)\tfourcc_mod_code(ARM, __afbc_mode)\n> +\n> +/*\n> + * The top 4 bits (out of the 56 bits alloted for specifying vendor specific\n> + * modifiers) denote the category for modifiers. Currently we have only two\n> + * categories of modifiers ie AFBC and MISC. We can have a maximum of sixteen\n> + * different categories.\n> + */\n> +#define DRM_FORMAT_MOD_ARM_CODE(__type, __val) \\\n> +\tfourcc_mod_code(ARM, ((__u64)(__type) << 52) | ((__val) & 0x000fffffffffffffULL))\n> +\n> +#define DRM_FORMAT_MOD_ARM_TYPE_AFBC 0x00\n> +#define DRM_FORMAT_MOD_ARM_TYPE_MISC 0x01\n> +\n> +#define DRM_FORMAT_MOD_ARM_AFBC(__afbc_mode) \\\n> +\tDRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_AFBC, __afbc_mode)\n> \n> /*\n> * AFBC superblock size\n> @@ -817,6 +1073,28 @@ extern \"C\" {\n> */\n> #define AFBC_FORMAT_MOD_BCH (1ULL << 11)\n> \n> +/* AFBC uncompressed storage mode\n> + *\n> + * Indicates that the buffer is using AFBC uncompressed storage mode.\n> + * In this mode all superblock payloads in the buffer use the uncompressed\n> + * storage mode, which is usually only used for data which cannot be compressed.\n> + * The buffer layout is the same as for AFBC buffers without USM set, this only\n> + * affects the storage mode of the individual superblocks. Note that even a\n> + * buffer without USM set may use uncompressed storage mode for some or all\n> + * superblocks, USM just guarantees it for all.\n> + */\n> +#define AFBC_FORMAT_MOD_USM\t(1ULL << 12)\n> +\n> +/*\n> + * Arm 16x16 Block U-Interleaved modifier\n> + *\n> + * This is used by Arm Mali Utgard and Midgard GPUs. It divides the image\n> + * into 16x16 pixel blocks. Blocks are stored linearly in order, but pixels\n> + * in the block are reordered.\n> + */\n> +#define DRM_FORMAT_MOD_ARM_16X16_BLOCK_U_INTERLEAVED \\\n> +\tDRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_MISC, 1ULL)\n> +\n> /*\n> * Allwinner tiled modifier\n> *\n> @@ -831,6 +1109,220 @@ extern \"C\" {\n> */\n> #define DRM_FORMAT_MOD_ALLWINNER_TILED fourcc_mod_code(ALLWINNER, 1)\n> \n> +/*\n> + * Amlogic Video Framebuffer Compression modifiers\n> + *\n> + * Amlogic uses a proprietary lossless image compression protocol and format\n> + * for their hardware video codec accelerators, either video decoders or\n> + * video input encoders.\n> + *\n> + * It considerably reduces memory bandwidth while writing and reading\n> + * frames in memory.\n> + *\n> + * The underlying storage is considered to be 3 components, 8bit or 10-bit\n> + * per component YCbCr 420, single plane :\n> + * - DRM_FORMAT_YUV420_8BIT\n> + * - DRM_FORMAT_YUV420_10BIT\n> + *\n> + * The first 8 bits of the mode defines the layout, then the following 8 bits\n> + * defines the options changing the layout.\n> + *\n> + * Not all combinations are valid, and different SoCs may support different\n> + * combinations of layout and options.\n> + */\n> +#define __fourcc_mod_amlogic_layout_mask 0xff\n> +#define __fourcc_mod_amlogic_options_shift 8\n> +#define __fourcc_mod_amlogic_options_mask 0xff\n> +\n> +#define DRM_FORMAT_MOD_AMLOGIC_FBC(__layout, __options) \\\n> +\tfourcc_mod_code(AMLOGIC, \\\n> +\t\t\t((__layout) & __fourcc_mod_amlogic_layout_mask) | \\\n> +\t\t\t(((__options) & __fourcc_mod_amlogic_options_mask) \\\n> +\t\t\t << __fourcc_mod_amlogic_options_shift))\n> +\n> +/* Amlogic FBC Layouts */\n> +\n> +/*\n> + * Amlogic FBC Basic Layout\n> + *\n> + * The basic layout is composed of:\n> + * - a body content organized in 64x32 superblocks with 4096 bytes per\n> + * superblock in default mode.\n> + * - a 32 bytes per 128x64 header block\n> + *\n> + * This layout is transferrable between Amlogic SoCs supporting this modifier.\n> + */\n> +#define AMLOGIC_FBC_LAYOUT_BASIC\t\t(1ULL)\n> +\n> +/*\n> + * Amlogic FBC Scatter Memory layout\n> + *\n> + * Indicates the header contains IOMMU references to the compressed\n> + * frames content to optimize memory access and layout.\n> + *\n> + * In this mode, only the header memory address is needed, thus the\n> + * content memory organization is tied to the current producer\n> + * execution and cannot be saved/dumped neither transferrable between\n> + * Amlogic SoCs supporting this modifier.\n> + *\n> + * Due to the nature of the layout, these buffers are not expected to\n> + * be accessible by the user-space clients, but only accessible by the\n> + * hardware producers and consumers.\n> + *\n> + * The user-space clients should expect a failure while trying to mmap\n> + * the DMA-BUF handle returned by the producer.\n> + */\n> +#define AMLOGIC_FBC_LAYOUT_SCATTER\t\t(2ULL)\n> +\n> +/* Amlogic FBC Layout Options Bit Mask */\n> +\n> +/*\n> + * Amlogic FBC Memory Saving mode\n> + *\n> + * Indicates the storage is packed when pixel size is multiple of word\n> + * boudaries, i.e. 8bit should be stored in this mode to save allocation\n> + * memory.\n> + *\n> + * This mode reduces body layout to 3072 bytes per 64x32 superblock with\n> + * the basic layout and 3200 bytes per 64x32 superblock combined with\n> + * the scatter layout.\n> + */\n> +#define AMLOGIC_FBC_OPTION_MEM_SAVING\t\t(1ULL << 0)\n> +\n> +/*\n> + * AMD modifiers\n> + *\n> + * Memory layout:\n> + *\n> + * without DCC:\n> + * - main surface\n> + *\n> + * with DCC & without DCC_RETILE:\n> + * - main surface in plane 0\n> + * - DCC surface in plane 1 (RB-aligned, pipe-aligned if DCC_PIPE_ALIGN is set)\n> + *\n> + * with DCC & DCC_RETILE:\n> + * - main surface in plane 0\n> + * - displayable DCC surface in plane 1 (not RB-aligned & not pipe-aligned)\n> + * - pipe-aligned DCC surface in plane 2 (RB-aligned & pipe-aligned)\n> + *\n> + * For multi-plane formats the above surfaces get merged into one plane for\n> + * each format plane, based on the required alignment only.\n> + *\n> + * Bits Parameter Notes\n> + * ----- ------------------------ ---------------------------------------------\n> + *\n> + * 7:0 TILE_VERSION Values are AMD_FMT_MOD_TILE_VER_*\n> + * 12:8 TILE Values are AMD_FMT_MOD_TILE__*\n> + * 13 DCC\n> + * 14 DCC_RETILE\n> + * 15 DCC_PIPE_ALIGN\n> + * 16 DCC_INDEPENDENT_64B\n> + * 17 DCC_INDEPENDENT_128B\n> + * 19:18 DCC_MAX_COMPRESSED_BLOCK Values are AMD_FMT_MOD_DCC_BLOCK_*\n> + * 20 DCC_CONSTANT_ENCODE\n> + * 23:21 PIPE_XOR_BITS Only for some chips\n> + * 26:24 BANK_XOR_BITS Only for some chips\n> + * 29:27 PACKERS Only for some chips\n> + * 32:30 RB Only for some chips\n> + * 35:33 PIPE Only for some chips\n> + * 55:36 - Reserved for future use, must be zero\n> + */\n> +#define AMD_FMT_MOD fourcc_mod_code(AMD, 0)\n> +\n> +#define IS_AMD_FMT_MOD(val) (((val) >> 56) == DRM_FORMAT_MOD_VENDOR_AMD)\n> +\n> +/* Reserve 0 for GFX8 and older */\n> +#define AMD_FMT_MOD_TILE_VER_GFX9 1\n> +#define AMD_FMT_MOD_TILE_VER_GFX10 2\n> +#define AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS 3\n> +\n> +/*\n> + * 64K_S is the same for GFX9/GFX10/GFX10_RBPLUS and hence has GFX9 as canonical\n> + * version.\n> + */\n> +#define AMD_FMT_MOD_TILE_GFX9_64K_S 9\n> +\n> +/*\n> + * 64K_D for non-32 bpp is the same for GFX9/GFX10/GFX10_RBPLUS and hence has\n> + * GFX9 as canonical version.\n> + */\n> +#define AMD_FMT_MOD_TILE_GFX9_64K_D 10\n> +#define AMD_FMT_MOD_TILE_GFX9_64K_S_X 25\n> +#define AMD_FMT_MOD_TILE_GFX9_64K_D_X 26\n> +#define AMD_FMT_MOD_TILE_GFX9_64K_R_X 27\n> +\n> +#define AMD_FMT_MOD_DCC_BLOCK_64B 0\n> +#define AMD_FMT_MOD_DCC_BLOCK_128B 1\n> +#define AMD_FMT_MOD_DCC_BLOCK_256B 2\n> +\n> +#define AMD_FMT_MOD_TILE_VERSION_SHIFT 0\n> +#define AMD_FMT_MOD_TILE_VERSION_MASK 0xFF\n> +#define AMD_FMT_MOD_TILE_SHIFT 8\n> +#define AMD_FMT_MOD_TILE_MASK 0x1F\n> +\n> +/* Whether DCC compression is enabled. */\n> +#define AMD_FMT_MOD_DCC_SHIFT 13\n> +#define AMD_FMT_MOD_DCC_MASK 0x1\n> +\n> +/*\n> + * Whether to include two DCC surfaces, one which is rb & pipe aligned, and\n> + * one which is not-aligned.\n> + */\n> +#define AMD_FMT_MOD_DCC_RETILE_SHIFT 14\n> +#define AMD_FMT_MOD_DCC_RETILE_MASK 0x1\n> +\n> +/* Only set if DCC_RETILE = false */\n> +#define AMD_FMT_MOD_DCC_PIPE_ALIGN_SHIFT 15\n> +#define AMD_FMT_MOD_DCC_PIPE_ALIGN_MASK 0x1\n> +\n> +#define AMD_FMT_MOD_DCC_INDEPENDENT_64B_SHIFT 16\n> +#define AMD_FMT_MOD_DCC_INDEPENDENT_64B_MASK 0x1\n> +#define AMD_FMT_MOD_DCC_INDEPENDENT_128B_SHIFT 17\n> +#define AMD_FMT_MOD_DCC_INDEPENDENT_128B_MASK 0x1\n> +#define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_SHIFT 18\n> +#define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_MASK 0x3\n> +\n> +/*\n> + * DCC supports embedding some clear colors directly in the DCC surface.\n> + * However, on older GPUs the rendering HW ignores the embedded clear color\n> + * and prefers the driver provided color. This necessitates doing a fastclear\n> + * eliminate operation before a process transfers control.\n> + *\n> + * If this bit is set that means the fastclear eliminate is not needed for these\n> + * embeddable colors.\n> + */\n> +#define AMD_FMT_MOD_DCC_CONSTANT_ENCODE_SHIFT 20\n> +#define AMD_FMT_MOD_DCC_CONSTANT_ENCODE_MASK 0x1\n> +\n> +/*\n> + * The below fields are for accounting for per GPU differences. These are only\n> + * relevant for GFX9 and later and if the tile field is *_X/_T.\n> + *\n> + * PIPE_XOR_BITS = always needed\n> + * BANK_XOR_BITS = only for TILE_VER_GFX9\n> + * PACKERS = only for TILE_VER_GFX10_RBPLUS\n> + * RB = only for TILE_VER_GFX9 & DCC\n> + * PIPE = only for TILE_VER_GFX9 & DCC & (DCC_RETILE | DCC_PIPE_ALIGN)\n> + */\n> +#define AMD_FMT_MOD_PIPE_XOR_BITS_SHIFT 21\n> +#define AMD_FMT_MOD_PIPE_XOR_BITS_MASK 0x7\n> +#define AMD_FMT_MOD_BANK_XOR_BITS_SHIFT 24\n> +#define AMD_FMT_MOD_BANK_XOR_BITS_MASK 0x7\n> +#define AMD_FMT_MOD_PACKERS_SHIFT 27\n> +#define AMD_FMT_MOD_PACKERS_MASK 0x7\n> +#define AMD_FMT_MOD_RB_SHIFT 30\n> +#define AMD_FMT_MOD_RB_MASK 0x7\n> +#define AMD_FMT_MOD_PIPE_SHIFT 33\n> +#define AMD_FMT_MOD_PIPE_MASK 0x7\n> +\n> +#define AMD_FMT_MOD_SET(field, value) \\\n> +\t((uint64_t)(value) << AMD_FMT_MOD_##field##_SHIFT)\n> +#define AMD_FMT_MOD_GET(field, value) \\\n> +\t(((value) >> AMD_FMT_MOD_##field##_SHIFT) & AMD_FMT_MOD_##field##_MASK)\n> +#define AMD_FMT_MOD_CLEAR(field) \\\n> +\t(~((uint64_t)AMD_FMT_MOD_##field##_MASK << AMD_FMT_MOD_##field##_SHIFT))\n> +\n> /* Mobile Industry Processor Interface (MIPI) modifiers */\n> \n> /*\n> diff --git a/include/linux/intel-ipu3.h b/include/linux/intel-ipu3.h\n> index 8ed1632164fd..ee0e6d0e4b2c 100644\n> --- a/include/linux/intel-ipu3.h\n> +++ b/include/linux/intel-ipu3.h\n> @@ -120,13 +120,13 @@ struct ipu3_uapi_awb_config {\n> #define IPU3_UAPI_AE_WEIGHTS\t\t\t\t96\n> \n> /**\n> - + * struct ipu3_uapi_ae_raw_buffer - AE global weighted histogram\n> - + *\n> - + * @vals: Sum of IPU3_UAPI_AE_COLORS in cell\n> - + *\n> - + * Each histogram contains IPU3_UAPI_AE_BINS bins. Each bin has 24 bit unsigned\n> - + * for counting the number of the pixel.\n> - + */\n> + * struct ipu3_uapi_ae_raw_buffer - AE global weighted histogram\n> + *\n> + * @vals: Sum of IPU3_UAPI_AE_COLORS in cell\n> + *\n> + * Each histogram contains IPU3_UAPI_AE_BINS bins. Each bin has 24 bit unsigned\n> + * for counting the number of the pixel.\n> + */\n> struct ipu3_uapi_ae_raw_buffer {\n> \t__u32 vals[IPU3_UAPI_AE_BINS * IPU3_UAPI_AE_COLORS];\n> } __attribute__((packed));\n> @@ -418,7 +418,7 @@ struct ipu3_uapi_af_config_s {\n> \t IPU3_UAPI_AWB_FR_SPARE_FOR_BUBBLES) * IPU3_UAPI_MAX_STRIPES)\n> \n> /**\n> - * struct ipu3_uapi_awb_fr_meta_data - AWB filter response meta data\n> + * struct ipu3_uapi_awb_fr_raw_buffer - AWB filter response meta data\n> *\n> * @meta_data: Statistics output on the grid after convolving with 1D filter.\n> */\n> @@ -1506,7 +1506,7 @@ struct ipu3_uapi_sharp_cfg {\n> } __attribute__((packed));\n> \n> /**\n> - * struct struct ipu3_uapi_far_w - Sharpening config for far sub-group\n> + * struct ipu3_uapi_far_w - Sharpening config for far sub-group\n> *\n> * @dir_shrp:\tWeight of wide direct sharpening, u1.6, range [0, 64], default 64.\n> * @reserved0:\treserved\n> @@ -1526,7 +1526,7 @@ struct ipu3_uapi_far_w {\n> } __attribute__((packed));\n> \n> /**\n> - * struct struct ipu3_uapi_unsharp_cfg - Unsharp config\n> + * struct ipu3_uapi_unsharp_cfg - Unsharp config\n> *\n> * @unsharp_weight: Unsharp mask blending weight.\n> *\t\t u1.6, range [0, 64], default 16.\n> @@ -1772,7 +1772,7 @@ struct ipu3_uapi_vss_lut_y {\n> } __attribute__((packed));\n> \n> /**\n> - * struct ipu3_uapi_yuvp1_iefd_vssnlm_cf - IEFd Vssnlm Lookup table\n> + * struct ipu3_uapi_yuvp1_iefd_vssnlm_cfg - IEFd Vssnlm Lookup table\n> *\n> * @vss_lut_x: vss lookup table. See &ipu3_uapi_vss_lut_x description\n> * @vss_lut_y: vss lookup table. See &ipu3_uapi_vss_lut_y description\n> diff --git a/include/linux/media-bus-format.h b/include/linux/media-bus-format.h\n> index 16c1fa2d89a4..0dfc11ee243a 100644\n> --- a/include/linux/media-bus-format.h\n> +++ b/include/linux/media-bus-format.h\n> @@ -34,7 +34,7 @@\n> \n> #define MEDIA_BUS_FMT_FIXED\t\t\t0x0001\n> \n> -/* RGB - next is\t0x101d */\n> +/* RGB - next is\t0x101e */\n> #define MEDIA_BUS_FMT_RGB444_1X12\t\t0x1016\n> #define MEDIA_BUS_FMT_RGB444_2X8_PADHI_BE\t0x1001\n> #define MEDIA_BUS_FMT_RGB444_2X8_PADHI_LE\t0x1002\n> @@ -56,6 +56,7 @@\n> #define MEDIA_BUS_FMT_RGB888_2X12_BE\t\t0x100b\n> #define MEDIA_BUS_FMT_RGB888_2X12_LE\t\t0x100c\n> #define MEDIA_BUS_FMT_RGB888_3X8\t\t0x101c\n> +#define MEDIA_BUS_FMT_RGB888_3X8_DELTA\t\t0x101d\n> #define MEDIA_BUS_FMT_RGB888_1X7X4_SPWG\t\t0x1011\n> #define MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA\t0x1012\n> #define MEDIA_BUS_FMT_ARGB8888_1X32\t\t0x100d\n> @@ -64,7 +65,7 @@\n> #define MEDIA_BUS_FMT_RGB121212_1X36\t\t0x1019\n> #define MEDIA_BUS_FMT_RGB161616_1X48\t\t0x101a\n> \n> -/* YUV (including grey) - next is\t0x202d */\n> +/* YUV (including grey) - next is\t0x202e */\n> #define MEDIA_BUS_FMT_Y8_1X8\t\t\t0x2001\n> #define MEDIA_BUS_FMT_UV8_1X8\t\t\t0x2015\n> #define MEDIA_BUS_FMT_UYVY8_1_5X8\t\t0x2002\n> @@ -86,6 +87,7 @@\n> #define MEDIA_BUS_FMT_VYUY12_2X12\t\t0x201d\n> #define MEDIA_BUS_FMT_YUYV12_2X12\t\t0x201e\n> #define MEDIA_BUS_FMT_YVYU12_2X12\t\t0x201f\n> +#define MEDIA_BUS_FMT_Y14_1X14\t\t\t0x202d\n> #define MEDIA_BUS_FMT_UYVY8_1X16\t\t0x200f\n> #define MEDIA_BUS_FMT_VYUY8_1X16\t\t0x2010\n> #define MEDIA_BUS_FMT_YUYV8_1X16\t\t0x2011\n> @@ -155,4 +157,12 @@\n> /* HSV - next is\t0x6002 */\n> #define MEDIA_BUS_FMT_AHSV8888_1X32\t\t0x6001\n> \n> +/*\n> + * This format should be used when the same driver handles\n> + * both sides of the link and the bus format is a fixed\n> + * metadata format that is not configurable from userspace.\n> + * Width and height will be set to 0 for this format.\n> + */\n> +#define MEDIA_BUS_FMT_METADATA_FIXED\t\t0x7001\n> +\n> #endif /* __LINUX_MEDIA_BUS_FORMAT_H */\n> diff --git a/include/linux/media.h b/include/linux/media.h\n> index f4ba8ae3e410..17432318a07e 100644\n> --- a/include/linux/media.h\n> +++ b/include/linux/media.h\n> @@ -125,6 +125,7 @@ struct media_device_info {\n> #define MEDIA_ENT_F_PROC_VIDEO_STATISTICS\t(MEDIA_ENT_F_BASE + 0x4006)\n> #define MEDIA_ENT_F_PROC_VIDEO_ENCODER\t\t(MEDIA_ENT_F_BASE + 0x4007)\n> #define MEDIA_ENT_F_PROC_VIDEO_DECODER\t\t(MEDIA_ENT_F_BASE + 0x4008)\n> +#define MEDIA_ENT_F_PROC_VIDEO_ISP\t\t(MEDIA_ENT_F_BASE + 0x4009)\n> \n> /*\n> * Switch and bridge entity functions\n> diff --git a/include/linux/rkisp1-config.h b/include/linux/rkisp1-config.h\n> index 9c24867ddd68..1b14c2303121 100644\n> --- a/include/linux/rkisp1-config.h\n> +++ b/include/linux/rkisp1-config.h\n> @@ -1,4 +1,4 @@\n> -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */\n> +/* SPDX-License-Identifier: ((GPL-2.0+ WITH Linux-syscall-note) OR MIT) */\n> /*\n> * Rockchip ISP1 userspace API\n> * Copyright (C) 2017 Rockchip Electronics Co., Ltd.\n> @@ -9,10 +9,6 @@\n> \n> #include \n> \n> -/* Vendor specific - used for RK_ISP1 camera sub-system */\n> -#define V4L2_META_FMT_RK_ISP1_PARAMS v4l2_fourcc('R', 'K', '1', 'P') /* Rockchip ISP1 params */\n> -#define V4L2_META_FMT_RK_ISP1_STAT_3A v4l2_fourcc('R', 'K', '1', 'S') /* Rockchip ISP1 3A statistics */\n> -\n> /* Defect Pixel Cluster Detection */\n> #define RKISP1_CIF_ISP_MODULE_DPCC\t\t(1U << 0)\n> /* Black Level Subtraction */\n> @@ -53,8 +49,14 @@\n> #define RKISP1_CIF_ISP_CTK_COEFF_MAX 0x100\n> #define RKISP1_CIF_ISP_CTK_OFFSET_MAX 0x800\n> \n> -#define RKISP1_CIF_ISP_AE_MEAN_MAX 25\n> -#define RKISP1_CIF_ISP_HIST_BIN_N_MAX 16\n> +#define RKISP1_CIF_ISP_AE_MEAN_MAX_V10\t\t25\n> +#define RKISP1_CIF_ISP_AE_MEAN_MAX_V12\t\t81\n> +#define RKISP1_CIF_ISP_AE_MEAN_MAX\t\tRKISP1_CIF_ISP_AE_MEAN_MAX_V12\n> +\n> +#define RKISP1_CIF_ISP_HIST_BIN_N_MAX_V10\t16\n> +#define RKISP1_CIF_ISP_HIST_BIN_N_MAX_V12\t32\n> +#define RKISP1_CIF_ISP_HIST_BIN_N_MAX\t\tRKISP1_CIF_ISP_HIST_BIN_N_MAX_V12\n> +\n> #define RKISP1_CIF_ISP_AFM_MAX_WINDOWS 3\n> #define RKISP1_CIF_ISP_DEGAMMA_CURVE_SIZE 17\n> \n> @@ -90,7 +92,9 @@\n> * Gamma out\n> */\n> /* Maximum number of color samples supported */\n> -#define RKISP1_CIF_ISP_GAMMA_OUT_MAX_SAMPLES 17\n> +#define RKISP1_CIF_ISP_GAMMA_OUT_MAX_SAMPLES_V10 17\n> +#define RKISP1_CIF_ISP_GAMMA_OUT_MAX_SAMPLES_V12 34\n> +#define RKISP1_CIF_ISP_GAMMA_OUT_MAX_SAMPLES RKISP1_CIF_ISP_GAMMA_OUT_MAX_SAMPLES_V12\n> \n> /*\n> * Lens shade correction\n> @@ -106,8 +110,9 @@\n> /*\n> * Histogram calculation\n> */\n> -/* Last 3 values unused. */\n> -#define RKISP1_CIF_ISP_HISTOGRAM_WEIGHT_GRIDS_SIZE 28\n> +#define RKISP1_CIF_ISP_HISTOGRAM_WEIGHT_GRIDS_SIZE_V10 25\n> +#define RKISP1_CIF_ISP_HISTOGRAM_WEIGHT_GRIDS_SIZE_V12 81\n> +#define RKISP1_CIF_ISP_HISTOGRAM_WEIGHT_GRIDS_SIZE RKISP1_CIF_ISP_HISTOGRAM_WEIGHT_GRIDS_SIZE_V12\n> \n> /*\n> * Defect Pixel Cluster Correction\n> @@ -128,6 +133,21 @@\n> #define RKISP1_CIF_ISP_STAT_AFM (1U << 2)\n> #define RKISP1_CIF_ISP_STAT_HIST (1U << 3)\n> \n> +/**\n> + * enum rkisp1_cif_isp_version - ISP variants\n> + *\n> + * @RKISP1_V10: used at least in rk3288 and rk3399\n> + * @RKISP1_V11: declared in the original vendor code, but not used\n> + * @RKISP1_V12: used at least in rk3326 and px30\n> + * @RKISP1_V13: used at least in rk1808\n> + */\n> +enum rkisp1_cif_isp_version {\n> +\tRKISP1_V10 = 10,\n> +\tRKISP1_V11,\n> +\tRKISP1_V12,\n> +\tRKISP1_V13,\n> +};\n> +\n> enum rkisp1_cif_isp_histogram_mode {\n> \tRKISP1_CIF_ISP_HISTOGRAM_MODE_DISABLE,\n> \tRKISP1_CIF_ISP_HISTOGRAM_MODE_RGB_COMBINED,\n> @@ -514,6 +534,15 @@ enum rkisp1_cif_isp_goc_mode {\n> *\n> * @mode: goc mode (from enum rkisp1_cif_isp_goc_mode)\n> * @gamma_y: gamma out curve y-axis for all color components\n> + *\n> + * The number of entries of @gamma_y depends on the hardware revision\n> + * as is reported by the hw_revision field of the struct media_device_info\n> + * that is returned by ioctl MEDIA_IOC_DEVICE_INFO.\n> + *\n> + * Versions <= V11 have RKISP1_CIF_ISP_GAMMA_OUT_MAX_SAMPLES_V10\n> + * entries, versions >= V12 have RKISP1_CIF_ISP_GAMMA_OUT_MAX_SAMPLES_V12\n> + * entries. RKISP1_CIF_ISP_GAMMA_OUT_MAX_SAMPLES is equal to the maximum\n> + * of the two.\n> */\n> struct rkisp1_cif_isp_goc_config {\n> \t__u32 mode;\n> @@ -528,6 +557,15 @@ struct rkisp1_cif_isp_goc_config {\n> *\t\t\t skipped\n> * @meas_window: coordinates of the measure window\n> * @hist_weight: weighting factor for sub-windows\n> + *\n> + * The number of entries of @hist_weight depends on the hardware revision\n> + * as is reported by the hw_revision field of the struct media_device_info\n> + * that is returned by ioctl MEDIA_IOC_DEVICE_INFO.\n> + *\n> + * Versions <= V11 have RKISP1_CIF_ISP_HISTOGRAM_WEIGHT_GRIDS_SIZE_V10\n> + * entries, versions >= V12 have RKISP1_CIF_ISP_HISTOGRAM_WEIGHT_GRIDS_SIZE_V12\n> + * entries. RKISP1_CIF_ISP_HISTOGRAM_WEIGHT_GRIDS_SIZE is equal to the maximum\n> + * of the two.\n> */\n> struct rkisp1_cif_isp_hst_config {\n> \t__u32 mode;\n> @@ -815,7 +853,15 @@ struct rkisp1_cif_isp_bls_meas_val {\n> * @exp_mean: Mean luminance value of block xx\n> * @bls_val: BLS measured values\n> *\n> - * Image is divided into 5x5 blocks.\n> + * The number of entries of @exp_mean depends on the hardware revision\n> + * as is reported by the hw_revision field of the struct media_device_info\n> + * that is returned by ioctl MEDIA_IOC_DEVICE_INFO.\n> + *\n> + * Versions <= V11 have RKISP1_CIF_ISP_AE_MEAN_MAX_V10 entries,\n> + * versions >= V12 have RKISP1_CIF_ISP_AE_MEAN_MAX_V12 entries.\n> + * RKISP1_CIF_ISP_AE_MEAN_MAX is equal to the maximum of the two.\n> + *\n> + * Image is divided into 5x5 blocks on V10 and 9x9 blocks on V12.\n> */\n> struct rkisp1_cif_isp_ae_stat {\n> \t__u8 exp_mean[RKISP1_CIF_ISP_AE_MEAN_MAX];\n> @@ -848,13 +894,29 @@ struct rkisp1_cif_isp_af_stat {\n> /**\n> * struct rkisp1_cif_isp_hist_stat - statistics histogram data\n> *\n> - * @hist_bins: measured bin counters\n> + * @hist_bins: measured bin counters. Each bin is a 20 bits unsigned fixed point\n> + *\t type. Bits 0-4 are the fractional part and bits 5-19 are the\n> + *\t integer part.\n> *\n> - * Measurement window divided into 25 sub-windows, set\n> - * with ISP_HIST_XXX\n> + * The window of the measurements area is divided to 5x5 sub-windows for\n> + * V10/V11 and to 9x9 sub-windows for V12. The histogram is then computed for\n> + * each sub-window independently and the final result is a weighted average of\n> + * the histogram measurements on all sub-windows. The window of the\n> + * measurements area and the weight of each sub-window are configurable using\n> + * struct @rkisp1_cif_isp_hst_config.\n> + *\n> + * The histogram contains 16 bins in V10/V11 and 32 bins in V12/V13.\n> + *\n> + * The number of entries of @hist_bins depends on the hardware revision\n> + * as is reported by the hw_revision field of the struct media_device_info\n> + * that is returned by ioctl MEDIA_IOC_DEVICE_INFO.\n> + *\n> + * Versions <= V11 have RKISP1_CIF_ISP_HIST_BIN_N_MAX_V10 entries,\n> + * versions >= V12 have RKISP1_CIF_ISP_HIST_BIN_N_MAX_V12 entries.\n> + * RKISP1_CIF_ISP_HIST_BIN_N_MAX is equal to the maximum of the two.\n> */\n> struct rkisp1_cif_isp_hist_stat {\n> -\t__u16 hist_bins[RKISP1_CIF_ISP_HIST_BIN_N_MAX];\n> +\t__u32 hist_bins[RKISP1_CIF_ISP_HIST_BIN_N_MAX];\n> };\n> \n> /**\n> diff --git a/include/linux/v4l2-controls.h b/include/linux/v4l2-controls.h\n> index 39f4bcb5c564..59a57418947e 100644\n> --- a/include/linux/v4l2-controls.h\n> +++ b/include/linux/v4l2-controls.h\n> @@ -54,7 +54,7 @@\n> \n> /* Control classes */\n> #define V4L2_CTRL_CLASS_USER\t\t0x00980000\t/* Old-style 'user' controls */\n> -#define V4L2_CTRL_CLASS_MPEG\t\t0x00990000\t/* MPEG-compression controls */\n> +#define V4L2_CTRL_CLASS_CODEC\t\t0x00990000\t/* Stateful codec controls */\n> #define V4L2_CTRL_CLASS_CAMERA\t\t0x009a0000\t/* Camera class controls */\n> #define V4L2_CTRL_CLASS_FM_TX\t\t0x009b0000\t/* FM Modulator controls */\n> #define V4L2_CTRL_CLASS_FLASH\t\t0x009c0000\t/* Camera flash controls */\n> @@ -65,6 +65,7 @@\n> #define V4L2_CTRL_CLASS_FM_RX\t\t0x00a10000\t/* FM Receiver controls */\n> #define V4L2_CTRL_CLASS_RF_TUNER\t0x00a20000\t/* RF tuner controls */\n> #define V4L2_CTRL_CLASS_DETECT\t\t0x00a30000\t/* Detection controls */\n> +#define V4L2_CTRL_CLASS_CODEC_STATELESS 0x00a40000\t/* Stateless codecs controls */\n> \n> /* User-class control IDs */\n> \n> @@ -198,6 +199,17 @@ enum v4l2_colorfx {\n> */\n> #define V4L2_CID_USER_ATMEL_ISC_BASE\t\t(V4L2_CID_USER_BASE + 0x10c0)\n> \n> +/*\n> + * The base for the CODA driver controls.\n> + * We reserve 16 controls for this driver.\n> + */\n> +#define V4L2_CID_USER_CODA_BASE\t\t\t(V4L2_CID_USER_BASE + 0x10e0)\n> +/*\n> + * The base for MIPI CCS driver controls.\n> + * We reserve 128 controls for this driver.\n> + */\n> +#define V4L2_CID_USER_CCS_BASE\t\t\t(V4L2_CID_USER_BASE + 0x10f0)\n> +\n> /* The base for the bcm2835-isp driver controls.\n> * We reserve 16 controls for this driver. */\n> #define V4L2_CID_USER_BCM2835_ISP_BASE\t\t(V4L2_CID_USER_BASE + 0x10e0)\n> @@ -206,11 +218,11 @@ enum v4l2_colorfx {\n> /* The MPEG controls are applicable to all codec controls\n> * and the 'MPEG' part of the define is historical */\n> \n> -#define V4L2_CID_MPEG_BASE\t\t\t(V4L2_CTRL_CLASS_MPEG | 0x900)\n> -#define V4L2_CID_MPEG_CLASS\t\t\t(V4L2_CTRL_CLASS_MPEG | 1)\n> +#define V4L2_CID_CODEC_BASE\t\t\t(V4L2_CTRL_CLASS_CODEC | 0x900)\n> +#define V4L2_CID_CODEC_CLASS\t\t\t(V4L2_CTRL_CLASS_CODEC | 1)\n> \n> /* MPEG streams, specific to multiplexed streams */\n> -#define V4L2_CID_MPEG_STREAM_TYPE\t\t(V4L2_CID_MPEG_BASE+0)\n> +#define V4L2_CID_MPEG_STREAM_TYPE\t\t(V4L2_CID_CODEC_BASE+0)\n> enum v4l2_mpeg_stream_type {\n> \tV4L2_MPEG_STREAM_TYPE_MPEG2_PS = 0, /* MPEG-2 program stream */\n> \tV4L2_MPEG_STREAM_TYPE_MPEG2_TS = 1, /* MPEG-2 transport stream */\n> @@ -219,26 +231,26 @@ enum v4l2_mpeg_stream_type {\n> \tV4L2_MPEG_STREAM_TYPE_MPEG1_VCD = 4, /* MPEG-1 VCD-compatible stream */\n> \tV4L2_MPEG_STREAM_TYPE_MPEG2_SVCD = 5, /* MPEG-2 SVCD-compatible stream */\n> };\n> -#define V4L2_CID_MPEG_STREAM_PID_PMT\t\t(V4L2_CID_MPEG_BASE+1)\n> -#define V4L2_CID_MPEG_STREAM_PID_AUDIO\t\t(V4L2_CID_MPEG_BASE+2)\n> -#define V4L2_CID_MPEG_STREAM_PID_VIDEO\t\t(V4L2_CID_MPEG_BASE+3)\n> -#define V4L2_CID_MPEG_STREAM_PID_PCR\t\t(V4L2_CID_MPEG_BASE+4)\n> -#define V4L2_CID_MPEG_STREAM_PES_ID_AUDIO\t(V4L2_CID_MPEG_BASE+5)\n> -#define V4L2_CID_MPEG_STREAM_PES_ID_VIDEO\t(V4L2_CID_MPEG_BASE+6)\n> -#define V4L2_CID_MPEG_STREAM_VBI_FMT\t\t(V4L2_CID_MPEG_BASE+7)\n> +#define V4L2_CID_MPEG_STREAM_PID_PMT\t\t(V4L2_CID_CODEC_BASE+1)\n> +#define V4L2_CID_MPEG_STREAM_PID_AUDIO\t\t(V4L2_CID_CODEC_BASE+2)\n> +#define V4L2_CID_MPEG_STREAM_PID_VIDEO\t\t(V4L2_CID_CODEC_BASE+3)\n> +#define V4L2_CID_MPEG_STREAM_PID_PCR\t\t(V4L2_CID_CODEC_BASE+4)\n> +#define V4L2_CID_MPEG_STREAM_PES_ID_AUDIO\t(V4L2_CID_CODEC_BASE+5)\n> +#define V4L2_CID_MPEG_STREAM_PES_ID_VIDEO\t(V4L2_CID_CODEC_BASE+6)\n> +#define V4L2_CID_MPEG_STREAM_VBI_FMT\t\t(V4L2_CID_CODEC_BASE+7)\n> enum v4l2_mpeg_stream_vbi_fmt {\n> \tV4L2_MPEG_STREAM_VBI_FMT_NONE = 0, /* No VBI in the MPEG stream */\n> \tV4L2_MPEG_STREAM_VBI_FMT_IVTV = 1, /* VBI in private packets, IVTV format */\n> };\n> \n> /* MPEG audio controls specific to multiplexed streams */\n> -#define V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ\t(V4L2_CID_MPEG_BASE+100)\n> +#define V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ\t(V4L2_CID_CODEC_BASE+100)\n> enum v4l2_mpeg_audio_sampling_freq {\n> \tV4L2_MPEG_AUDIO_SAMPLING_FREQ_44100 = 0,\n> \tV4L2_MPEG_AUDIO_SAMPLING_FREQ_48000 = 1,\n> \tV4L2_MPEG_AUDIO_SAMPLING_FREQ_32000 = 2,\n> };\n> -#define V4L2_CID_MPEG_AUDIO_ENCODING\t\t(V4L2_CID_MPEG_BASE+101)\n> +#define V4L2_CID_MPEG_AUDIO_ENCODING\t\t(V4L2_CID_CODEC_BASE+101)\n> enum v4l2_mpeg_audio_encoding {\n> \tV4L2_MPEG_AUDIO_ENCODING_LAYER_1 = 0,\n> \tV4L2_MPEG_AUDIO_ENCODING_LAYER_2 = 1,\n> @@ -246,7 +258,7 @@ enum v4l2_mpeg_audio_encoding {\n> \tV4L2_MPEG_AUDIO_ENCODING_AAC = 3,\n> \tV4L2_MPEG_AUDIO_ENCODING_AC3 = 4,\n> };\n> -#define V4L2_CID_MPEG_AUDIO_L1_BITRATE\t\t(V4L2_CID_MPEG_BASE+102)\n> +#define V4L2_CID_MPEG_AUDIO_L1_BITRATE\t\t(V4L2_CID_CODEC_BASE+102)\n> enum v4l2_mpeg_audio_l1_bitrate {\n> \tV4L2_MPEG_AUDIO_L1_BITRATE_32K = 0,\n> \tV4L2_MPEG_AUDIO_L1_BITRATE_64K = 1,\n> @@ -263,7 +275,7 @@ enum v4l2_mpeg_audio_l1_bitrate {\n> \tV4L2_MPEG_AUDIO_L1_BITRATE_416K = 12,\n> \tV4L2_MPEG_AUDIO_L1_BITRATE_448K = 13,\n> };\n> -#define V4L2_CID_MPEG_AUDIO_L2_BITRATE\t\t(V4L2_CID_MPEG_BASE+103)\n> +#define V4L2_CID_MPEG_AUDIO_L2_BITRATE\t\t(V4L2_CID_CODEC_BASE+103)\n> enum v4l2_mpeg_audio_l2_bitrate {\n> \tV4L2_MPEG_AUDIO_L2_BITRATE_32K = 0,\n> \tV4L2_MPEG_AUDIO_L2_BITRATE_48K = 1,\n> @@ -280,7 +292,7 @@ enum v4l2_mpeg_audio_l2_bitrate {\n> \tV4L2_MPEG_AUDIO_L2_BITRATE_320K = 12,\n> \tV4L2_MPEG_AUDIO_L2_BITRATE_384K = 13,\n> };\n> -#define V4L2_CID_MPEG_AUDIO_L3_BITRATE\t\t(V4L2_CID_MPEG_BASE+104)\n> +#define V4L2_CID_MPEG_AUDIO_L3_BITRATE\t\t(V4L2_CID_CODEC_BASE+104)\n> enum v4l2_mpeg_audio_l3_bitrate {\n> \tV4L2_MPEG_AUDIO_L3_BITRATE_32K = 0,\n> \tV4L2_MPEG_AUDIO_L3_BITRATE_40K = 1,\n> @@ -297,34 +309,34 @@ enum v4l2_mpeg_audio_l3_bitrate {\n> \tV4L2_MPEG_AUDIO_L3_BITRATE_256K = 12,\n> \tV4L2_MPEG_AUDIO_L3_BITRATE_320K = 13,\n> };\n> -#define V4L2_CID_MPEG_AUDIO_MODE\t\t(V4L2_CID_MPEG_BASE+105)\n> +#define V4L2_CID_MPEG_AUDIO_MODE\t\t(V4L2_CID_CODEC_BASE+105)\n> enum v4l2_mpeg_audio_mode {\n> \tV4L2_MPEG_AUDIO_MODE_STEREO = 0,\n> \tV4L2_MPEG_AUDIO_MODE_JOINT_STEREO = 1,\n> \tV4L2_MPEG_AUDIO_MODE_DUAL = 2,\n> \tV4L2_MPEG_AUDIO_MODE_MONO = 3,\n> };\n> -#define V4L2_CID_MPEG_AUDIO_MODE_EXTENSION\t(V4L2_CID_MPEG_BASE+106)\n> +#define V4L2_CID_MPEG_AUDIO_MODE_EXTENSION\t(V4L2_CID_CODEC_BASE+106)\n> enum v4l2_mpeg_audio_mode_extension {\n> \tV4L2_MPEG_AUDIO_MODE_EXTENSION_BOUND_4 = 0,\n> \tV4L2_MPEG_AUDIO_MODE_EXTENSION_BOUND_8 = 1,\n> \tV4L2_MPEG_AUDIO_MODE_EXTENSION_BOUND_12 = 2,\n> \tV4L2_MPEG_AUDIO_MODE_EXTENSION_BOUND_16 = 3,\n> };\n> -#define V4L2_CID_MPEG_AUDIO_EMPHASIS\t\t(V4L2_CID_MPEG_BASE+107)\n> +#define V4L2_CID_MPEG_AUDIO_EMPHASIS\t\t(V4L2_CID_CODEC_BASE+107)\n> enum v4l2_mpeg_audio_emphasis {\n> \tV4L2_MPEG_AUDIO_EMPHASIS_NONE = 0,\n> \tV4L2_MPEG_AUDIO_EMPHASIS_50_DIV_15_uS = 1,\n> \tV4L2_MPEG_AUDIO_EMPHASIS_CCITT_J17 = 2,\n> };\n> -#define V4L2_CID_MPEG_AUDIO_CRC\t\t\t(V4L2_CID_MPEG_BASE+108)\n> +#define V4L2_CID_MPEG_AUDIO_CRC\t\t\t(V4L2_CID_CODEC_BASE+108)\n> enum v4l2_mpeg_audio_crc {\n> \tV4L2_MPEG_AUDIO_CRC_NONE = 0,\n> \tV4L2_MPEG_AUDIO_CRC_CRC16 = 1,\n> };\n> -#define V4L2_CID_MPEG_AUDIO_MUTE\t\t(V4L2_CID_MPEG_BASE+109)\n> -#define V4L2_CID_MPEG_AUDIO_AAC_BITRATE\t\t(V4L2_CID_MPEG_BASE+110)\n> -#define V4L2_CID_MPEG_AUDIO_AC3_BITRATE\t\t(V4L2_CID_MPEG_BASE+111)\n> +#define V4L2_CID_MPEG_AUDIO_MUTE\t\t(V4L2_CID_CODEC_BASE+109)\n> +#define V4L2_CID_MPEG_AUDIO_AAC_BITRATE\t\t(V4L2_CID_CODEC_BASE+110)\n> +#define V4L2_CID_MPEG_AUDIO_AC3_BITRATE\t\t(V4L2_CID_CODEC_BASE+111)\n> enum v4l2_mpeg_audio_ac3_bitrate {\n> \tV4L2_MPEG_AUDIO_AC3_BITRATE_32K = 0,\n> \tV4L2_MPEG_AUDIO_AC3_BITRATE_40K = 1,\n> @@ -346,7 +358,7 @@ enum v4l2_mpeg_audio_ac3_bitrate {\n> \tV4L2_MPEG_AUDIO_AC3_BITRATE_576K = 17,\n> \tV4L2_MPEG_AUDIO_AC3_BITRATE_640K = 18,\n> };\n> -#define V4L2_CID_MPEG_AUDIO_DEC_PLAYBACK\t(V4L2_CID_MPEG_BASE+112)\n> +#define V4L2_CID_MPEG_AUDIO_DEC_PLAYBACK\t(V4L2_CID_CODEC_BASE+112)\n> enum v4l2_mpeg_audio_dec_playback {\n> \tV4L2_MPEG_AUDIO_DEC_PLAYBACK_AUTO\t = 0,\n> \tV4L2_MPEG_AUDIO_DEC_PLAYBACK_STEREO\t = 1,\n> @@ -355,51 +367,52 @@ enum v4l2_mpeg_audio_dec_playback {\n> \tV4L2_MPEG_AUDIO_DEC_PLAYBACK_MONO\t = 4,\n> \tV4L2_MPEG_AUDIO_DEC_PLAYBACK_SWAPPED_STEREO = 5,\n> };\n> -#define V4L2_CID_MPEG_AUDIO_DEC_MULTILINGUAL_PLAYBACK (V4L2_CID_MPEG_BASE+113)\n> +#define V4L2_CID_MPEG_AUDIO_DEC_MULTILINGUAL_PLAYBACK (V4L2_CID_CODEC_BASE+113)\n> \n> /* MPEG video controls specific to multiplexed streams */\n> -#define V4L2_CID_MPEG_VIDEO_ENCODING\t\t(V4L2_CID_MPEG_BASE+200)\n> +#define V4L2_CID_MPEG_VIDEO_ENCODING\t\t(V4L2_CID_CODEC_BASE+200)\n> enum v4l2_mpeg_video_encoding {\n> \tV4L2_MPEG_VIDEO_ENCODING_MPEG_1 = 0,\n> \tV4L2_MPEG_VIDEO_ENCODING_MPEG_2 = 1,\n> \tV4L2_MPEG_VIDEO_ENCODING_MPEG_4_AVC = 2,\n> };\n> -#define V4L2_CID_MPEG_VIDEO_ASPECT\t\t(V4L2_CID_MPEG_BASE+201)\n> +#define V4L2_CID_MPEG_VIDEO_ASPECT\t\t(V4L2_CID_CODEC_BASE+201)\n> enum v4l2_mpeg_video_aspect {\n> \tV4L2_MPEG_VIDEO_ASPECT_1x1 = 0,\n> \tV4L2_MPEG_VIDEO_ASPECT_4x3 = 1,\n> \tV4L2_MPEG_VIDEO_ASPECT_16x9 = 2,\n> \tV4L2_MPEG_VIDEO_ASPECT_221x100 = 3,\n> };\n> -#define V4L2_CID_MPEG_VIDEO_B_FRAMES\t\t(V4L2_CID_MPEG_BASE+202)\n> -#define V4L2_CID_MPEG_VIDEO_GOP_SIZE\t\t(V4L2_CID_MPEG_BASE+203)\n> -#define V4L2_CID_MPEG_VIDEO_GOP_CLOSURE\t\t(V4L2_CID_MPEG_BASE+204)\n> -#define V4L2_CID_MPEG_VIDEO_PULLDOWN\t\t(V4L2_CID_MPEG_BASE+205)\n> -#define V4L2_CID_MPEG_VIDEO_BITRATE_MODE\t(V4L2_CID_MPEG_BASE+206)\n> +#define V4L2_CID_MPEG_VIDEO_B_FRAMES\t\t(V4L2_CID_CODEC_BASE+202)\n> +#define V4L2_CID_MPEG_VIDEO_GOP_SIZE\t\t(V4L2_CID_CODEC_BASE+203)\n> +#define V4L2_CID_MPEG_VIDEO_GOP_CLOSURE\t\t(V4L2_CID_CODEC_BASE+204)\n> +#define V4L2_CID_MPEG_VIDEO_PULLDOWN\t\t(V4L2_CID_CODEC_BASE+205)\n> +#define V4L2_CID_MPEG_VIDEO_BITRATE_MODE\t(V4L2_CID_CODEC_BASE+206)\n> enum v4l2_mpeg_video_bitrate_mode {\n> \tV4L2_MPEG_VIDEO_BITRATE_MODE_VBR = 0,\n> \tV4L2_MPEG_VIDEO_BITRATE_MODE_CBR = 1,\n> +\tV4L2_MPEG_VIDEO_BITRATE_MODE_CQ = 2,\n> };\n> -#define V4L2_CID_MPEG_VIDEO_BITRATE\t\t(V4L2_CID_MPEG_BASE+207)\n> -#define V4L2_CID_MPEG_VIDEO_BITRATE_PEAK\t(V4L2_CID_MPEG_BASE+208)\n> -#define V4L2_CID_MPEG_VIDEO_TEMPORAL_DECIMATION (V4L2_CID_MPEG_BASE+209)\n> -#define V4L2_CID_MPEG_VIDEO_MUTE\t\t(V4L2_CID_MPEG_BASE+210)\n> -#define V4L2_CID_MPEG_VIDEO_MUTE_YUV\t\t(V4L2_CID_MPEG_BASE+211)\n> -#define V4L2_CID_MPEG_VIDEO_DECODER_SLICE_INTERFACE\t\t(V4L2_CID_MPEG_BASE+212)\n> -#define V4L2_CID_MPEG_VIDEO_DECODER_MPEG4_DEBLOCK_FILTER\t(V4L2_CID_MPEG_BASE+213)\n> -#define V4L2_CID_MPEG_VIDEO_CYCLIC_INTRA_REFRESH_MB\t\t(V4L2_CID_MPEG_BASE+214)\n> -#define V4L2_CID_MPEG_VIDEO_FRAME_RC_ENABLE\t\t\t(V4L2_CID_MPEG_BASE+215)\n> -#define V4L2_CID_MPEG_VIDEO_HEADER_MODE\t\t\t\t(V4L2_CID_MPEG_BASE+216)\n> +#define V4L2_CID_MPEG_VIDEO_BITRATE\t\t(V4L2_CID_CODEC_BASE+207)\n> +#define V4L2_CID_MPEG_VIDEO_BITRATE_PEAK\t(V4L2_CID_CODEC_BASE+208)\n> +#define V4L2_CID_MPEG_VIDEO_TEMPORAL_DECIMATION (V4L2_CID_CODEC_BASE+209)\n> +#define V4L2_CID_MPEG_VIDEO_MUTE\t\t(V4L2_CID_CODEC_BASE+210)\n> +#define V4L2_CID_MPEG_VIDEO_MUTE_YUV\t\t(V4L2_CID_CODEC_BASE+211)\n> +#define V4L2_CID_MPEG_VIDEO_DECODER_SLICE_INTERFACE\t\t(V4L2_CID_CODEC_BASE+212)\n> +#define V4L2_CID_MPEG_VIDEO_DECODER_MPEG4_DEBLOCK_FILTER\t(V4L2_CID_CODEC_BASE+213)\n> +#define V4L2_CID_MPEG_VIDEO_CYCLIC_INTRA_REFRESH_MB\t\t(V4L2_CID_CODEC_BASE+214)\n> +#define V4L2_CID_MPEG_VIDEO_FRAME_RC_ENABLE\t\t\t(V4L2_CID_CODEC_BASE+215)\n> +#define V4L2_CID_MPEG_VIDEO_HEADER_MODE\t\t\t\t(V4L2_CID_CODEC_BASE+216)\n> enum v4l2_mpeg_video_header_mode {\n> \tV4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE\t\t\t= 0,\n> \tV4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME\t= 1,\n> \n> };\n> -#define V4L2_CID_MPEG_VIDEO_MAX_REF_PIC\t\t\t(V4L2_CID_MPEG_BASE+217)\n> -#define V4L2_CID_MPEG_VIDEO_MB_RC_ENABLE\t\t(V4L2_CID_MPEG_BASE+218)\n> -#define V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_BYTES\t(V4L2_CID_MPEG_BASE+219)\n> -#define V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_MB\t\t(V4L2_CID_MPEG_BASE+220)\n> -#define V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MODE\t\t(V4L2_CID_MPEG_BASE+221)\n> +#define V4L2_CID_MPEG_VIDEO_MAX_REF_PIC\t\t\t(V4L2_CID_CODEC_BASE+217)\n> +#define V4L2_CID_MPEG_VIDEO_MB_RC_ENABLE\t\t(V4L2_CID_CODEC_BASE+218)\n> +#define V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_BYTES\t(V4L2_CID_CODEC_BASE+219)\n> +#define V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_MB\t\t(V4L2_CID_CODEC_BASE+220)\n> +#define V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MODE\t\t(V4L2_CID_CODEC_BASE+221)\n> enum v4l2_mpeg_video_multi_slice_mode {\n> \tV4L2_MPEG_VIDEO_MULTI_SLICE_MODE_SINGLE\t\t= 0,\n> \tV4L2_MPEG_VIDEO_MULTI_SLICE_MODE_MAX_MB\t\t= 1,\n> @@ -408,24 +421,25 @@ enum v4l2_mpeg_video_multi_slice_mode {\n> \tV4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_MB\t\t= 1,\n> \tV4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_BYTES\t= 2,\n> };\n> -#define V4L2_CID_MPEG_VIDEO_VBV_SIZE\t\t\t(V4L2_CID_MPEG_BASE+222)\n> -#define V4L2_CID_MPEG_VIDEO_DEC_PTS\t\t\t(V4L2_CID_MPEG_BASE+223)\n> -#define V4L2_CID_MPEG_VIDEO_DEC_FRAME\t\t\t(V4L2_CID_MPEG_BASE+224)\n> -#define V4L2_CID_MPEG_VIDEO_VBV_DELAY\t\t\t(V4L2_CID_MPEG_BASE+225)\n> -#define V4L2_CID_MPEG_VIDEO_REPEAT_SEQ_HEADER\t\t(V4L2_CID_MPEG_BASE+226)\n> -#define V4L2_CID_MPEG_VIDEO_MV_H_SEARCH_RANGE\t\t(V4L2_CID_MPEG_BASE+227)\n> -#define V4L2_CID_MPEG_VIDEO_MV_V_SEARCH_RANGE\t\t(V4L2_CID_MPEG_BASE+228)\n> -#define V4L2_CID_MPEG_VIDEO_FORCE_KEY_FRAME\t\t(V4L2_CID_MPEG_BASE+229)\n> +#define V4L2_CID_MPEG_VIDEO_VBV_SIZE\t\t\t(V4L2_CID_CODEC_BASE+222)\n> +#define V4L2_CID_MPEG_VIDEO_DEC_PTS\t\t\t(V4L2_CID_CODEC_BASE+223)\n> +#define V4L2_CID_MPEG_VIDEO_DEC_FRAME\t\t\t(V4L2_CID_CODEC_BASE+224)\n> +#define V4L2_CID_MPEG_VIDEO_VBV_DELAY\t\t\t(V4L2_CID_CODEC_BASE+225)\n> +#define V4L2_CID_MPEG_VIDEO_REPEAT_SEQ_HEADER\t\t(V4L2_CID_CODEC_BASE+226)\n> +#define V4L2_CID_MPEG_VIDEO_MV_H_SEARCH_RANGE\t\t(V4L2_CID_CODEC_BASE+227)\n> +#define V4L2_CID_MPEG_VIDEO_MV_V_SEARCH_RANGE\t\t(V4L2_CID_CODEC_BASE+228)\n> +#define V4L2_CID_MPEG_VIDEO_FORCE_KEY_FRAME\t\t(V4L2_CID_CODEC_BASE+229)\n> +#define V4L2_CID_MPEG_VIDEO_BASELAYER_PRIORITY_ID\t(V4L2_CID_CODEC_BASE+230)\n> \n> /* CIDs for the MPEG-2 Part 2 (H.262) codec */\n> -#define V4L2_CID_MPEG_VIDEO_MPEG2_LEVEL\t\t\t(V4L2_CID_MPEG_BASE+270)\n> +#define V4L2_CID_MPEG_VIDEO_MPEG2_LEVEL\t\t\t(V4L2_CID_CODEC_BASE+270)\n> enum v4l2_mpeg_video_mpeg2_level {\n> \tV4L2_MPEG_VIDEO_MPEG2_LEVEL_LOW\t\t= 0,\n> \tV4L2_MPEG_VIDEO_MPEG2_LEVEL_MAIN\t= 1,\n> \tV4L2_MPEG_VIDEO_MPEG2_LEVEL_HIGH_1440\t= 2,\n> \tV4L2_MPEG_VIDEO_MPEG2_LEVEL_HIGH\t= 3,\n> };\n> -#define V4L2_CID_MPEG_VIDEO_MPEG2_PROFILE\t\t(V4L2_CID_MPEG_BASE+271)\n> +#define V4L2_CID_MPEG_VIDEO_MPEG2_PROFILE\t\t(V4L2_CID_CODEC_BASE+271)\n> enum v4l2_mpeg_video_mpeg2_profile {\n> \tV4L2_MPEG_VIDEO_MPEG2_PROFILE_SIMPLE\t\t\t\t= 0,\n> \tV4L2_MPEG_VIDEO_MPEG2_PROFILE_MAIN\t\t\t\t= 1,\n> @@ -436,28 +450,28 @@ enum v4l2_mpeg_video_mpeg2_profile {\n> };\n> \n> /* CIDs for the FWHT codec as used by the vicodec driver. */\n> -#define V4L2_CID_FWHT_I_FRAME_QP (V4L2_CID_MPEG_BASE + 290)\n> -#define V4L2_CID_FWHT_P_FRAME_QP (V4L2_CID_MPEG_BASE + 291)\n> +#define V4L2_CID_FWHT_I_FRAME_QP (V4L2_CID_CODEC_BASE + 290)\n> +#define V4L2_CID_FWHT_P_FRAME_QP (V4L2_CID_CODEC_BASE + 291)\n> \n> -#define V4L2_CID_MPEG_VIDEO_H263_I_FRAME_QP\t\t(V4L2_CID_MPEG_BASE+300)\n> -#define V4L2_CID_MPEG_VIDEO_H263_P_FRAME_QP\t\t(V4L2_CID_MPEG_BASE+301)\n> -#define V4L2_CID_MPEG_VIDEO_H263_B_FRAME_QP\t\t(V4L2_CID_MPEG_BASE+302)\n> -#define V4L2_CID_MPEG_VIDEO_H263_MIN_QP\t\t\t(V4L2_CID_MPEG_BASE+303)\n> -#define V4L2_CID_MPEG_VIDEO_H263_MAX_QP\t\t\t(V4L2_CID_MPEG_BASE+304)\n> -#define V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP\t\t(V4L2_CID_MPEG_BASE+350)\n> -#define V4L2_CID_MPEG_VIDEO_H264_P_FRAME_QP\t\t(V4L2_CID_MPEG_BASE+351)\n> -#define V4L2_CID_MPEG_VIDEO_H264_B_FRAME_QP\t\t(V4L2_CID_MPEG_BASE+352)\n> -#define V4L2_CID_MPEG_VIDEO_H264_MIN_QP\t\t\t(V4L2_CID_MPEG_BASE+353)\n> -#define V4L2_CID_MPEG_VIDEO_H264_MAX_QP\t\t\t(V4L2_CID_MPEG_BASE+354)\n> -#define V4L2_CID_MPEG_VIDEO_H264_8X8_TRANSFORM\t\t(V4L2_CID_MPEG_BASE+355)\n> -#define V4L2_CID_MPEG_VIDEO_H264_CPB_SIZE\t\t(V4L2_CID_MPEG_BASE+356)\n> -#define V4L2_CID_MPEG_VIDEO_H264_ENTROPY_MODE\t\t(V4L2_CID_MPEG_BASE+357)\n> +#define V4L2_CID_MPEG_VIDEO_H263_I_FRAME_QP\t\t(V4L2_CID_CODEC_BASE+300)\n> +#define V4L2_CID_MPEG_VIDEO_H263_P_FRAME_QP\t\t(V4L2_CID_CODEC_BASE+301)\n> +#define V4L2_CID_MPEG_VIDEO_H263_B_FRAME_QP\t\t(V4L2_CID_CODEC_BASE+302)\n> +#define V4L2_CID_MPEG_VIDEO_H263_MIN_QP\t\t\t(V4L2_CID_CODEC_BASE+303)\n> +#define V4L2_CID_MPEG_VIDEO_H263_MAX_QP\t\t\t(V4L2_CID_CODEC_BASE+304)\n> +#define V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP\t\t(V4L2_CID_CODEC_BASE+350)\n> +#define V4L2_CID_MPEG_VIDEO_H264_P_FRAME_QP\t\t(V4L2_CID_CODEC_BASE+351)\n> +#define V4L2_CID_MPEG_VIDEO_H264_B_FRAME_QP\t\t(V4L2_CID_CODEC_BASE+352)\n> +#define V4L2_CID_MPEG_VIDEO_H264_MIN_QP\t\t\t(V4L2_CID_CODEC_BASE+353)\n> +#define V4L2_CID_MPEG_VIDEO_H264_MAX_QP\t\t\t(V4L2_CID_CODEC_BASE+354)\n> +#define V4L2_CID_MPEG_VIDEO_H264_8X8_TRANSFORM\t\t(V4L2_CID_CODEC_BASE+355)\n> +#define V4L2_CID_MPEG_VIDEO_H264_CPB_SIZE\t\t(V4L2_CID_CODEC_BASE+356)\n> +#define V4L2_CID_MPEG_VIDEO_H264_ENTROPY_MODE\t\t(V4L2_CID_CODEC_BASE+357)\n> enum v4l2_mpeg_video_h264_entropy_mode {\n> \tV4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC\t= 0,\n> \tV4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC\t= 1,\n> };\n> -#define V4L2_CID_MPEG_VIDEO_H264_I_PERIOD\t\t(V4L2_CID_MPEG_BASE+358)\n> -#define V4L2_CID_MPEG_VIDEO_H264_LEVEL\t\t\t(V4L2_CID_MPEG_BASE+359)\n> +#define V4L2_CID_MPEG_VIDEO_H264_I_PERIOD\t\t(V4L2_CID_CODEC_BASE+358)\n> +#define V4L2_CID_MPEG_VIDEO_H264_LEVEL\t\t\t(V4L2_CID_CODEC_BASE+359)\n> enum v4l2_mpeg_video_h264_level {\n> \tV4L2_MPEG_VIDEO_H264_LEVEL_1_0\t= 0,\n> \tV4L2_MPEG_VIDEO_H264_LEVEL_1B\t= 1,\n> @@ -475,16 +489,20 @@ enum v4l2_mpeg_video_h264_level {\n> \tV4L2_MPEG_VIDEO_H264_LEVEL_4_2\t= 13,\n> \tV4L2_MPEG_VIDEO_H264_LEVEL_5_0\t= 14,\n> \tV4L2_MPEG_VIDEO_H264_LEVEL_5_1\t= 15,\n> +\tV4L2_MPEG_VIDEO_H264_LEVEL_5_2\t= 16,\n> +\tV4L2_MPEG_VIDEO_H264_LEVEL_6_0\t= 17,\n> +\tV4L2_MPEG_VIDEO_H264_LEVEL_6_1\t= 18,\n> +\tV4L2_MPEG_VIDEO_H264_LEVEL_6_2\t= 19,\n> };\n> -#define V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_ALPHA\t(V4L2_CID_MPEG_BASE+360)\n> -#define V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_BETA\t(V4L2_CID_MPEG_BASE+361)\n> -#define V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_MODE\t(V4L2_CID_MPEG_BASE+362)\n> +#define V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_ALPHA\t(V4L2_CID_CODEC_BASE+360)\n> +#define V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_BETA\t(V4L2_CID_CODEC_BASE+361)\n> +#define V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_MODE\t(V4L2_CID_CODEC_BASE+362)\n> enum v4l2_mpeg_video_h264_loop_filter_mode {\n> \tV4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_ENABLED\t\t\t\t= 0,\n> \tV4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_DISABLED\t\t\t\t= 1,\n> \tV4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_DISABLED_AT_SLICE_BOUNDARY\t= 2,\n> };\n> -#define V4L2_CID_MPEG_VIDEO_H264_PROFILE\t\t(V4L2_CID_MPEG_BASE+363)\n> +#define V4L2_CID_MPEG_VIDEO_H264_PROFILE\t\t(V4L2_CID_CODEC_BASE+363)\n> enum v4l2_mpeg_video_h264_profile {\n> \tV4L2_MPEG_VIDEO_H264_PROFILE_BASELINE\t\t\t= 0,\n> \tV4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE\t= 1,\n> @@ -503,11 +521,12 @@ enum v4l2_mpeg_video_h264_profile {\n> \tV4L2_MPEG_VIDEO_H264_PROFILE_SCALABLE_HIGH_INTRA\t= 14,\n> \tV4L2_MPEG_VIDEO_H264_PROFILE_STEREO_HIGH\t\t= 15,\n> \tV4L2_MPEG_VIDEO_H264_PROFILE_MULTIVIEW_HIGH\t\t= 16,\n> +\tV4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_HIGH\t\t= 17,\n> };\n> -#define V4L2_CID_MPEG_VIDEO_H264_VUI_EXT_SAR_HEIGHT\t(V4L2_CID_MPEG_BASE+364)\n> -#define V4L2_CID_MPEG_VIDEO_H264_VUI_EXT_SAR_WIDTH\t(V4L2_CID_MPEG_BASE+365)\n> -#define V4L2_CID_MPEG_VIDEO_H264_VUI_SAR_ENABLE\t\t(V4L2_CID_MPEG_BASE+366)\n> -#define V4L2_CID_MPEG_VIDEO_H264_VUI_SAR_IDC\t\t(V4L2_CID_MPEG_BASE+367)\n> +#define V4L2_CID_MPEG_VIDEO_H264_VUI_EXT_SAR_HEIGHT\t(V4L2_CID_CODEC_BASE+364)\n> +#define V4L2_CID_MPEG_VIDEO_H264_VUI_EXT_SAR_WIDTH\t(V4L2_CID_CODEC_BASE+365)\n> +#define V4L2_CID_MPEG_VIDEO_H264_VUI_SAR_ENABLE\t\t(V4L2_CID_CODEC_BASE+366)\n> +#define V4L2_CID_MPEG_VIDEO_H264_VUI_SAR_IDC\t\t(V4L2_CID_CODEC_BASE+367)\n> enum v4l2_mpeg_video_h264_vui_sar_idc {\n> \tV4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_UNSPECIFIED\t= 0,\n> \tV4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_1x1\t\t= 1,\n> @@ -528,9 +547,9 @@ enum v4l2_mpeg_video_h264_vui_sar_idc {\n> \tV4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_2x1\t\t= 16,\n> \tV4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_EXTENDED\t= 17,\n> };\n> -#define V4L2_CID_MPEG_VIDEO_H264_SEI_FRAME_PACKING\t\t(V4L2_CID_MPEG_BASE+368)\n> -#define V4L2_CID_MPEG_VIDEO_H264_SEI_FP_CURRENT_FRAME_0\t\t(V4L2_CID_MPEG_BASE+369)\n> -#define V4L2_CID_MPEG_VIDEO_H264_SEI_FP_ARRANGEMENT_TYPE\t(V4L2_CID_MPEG_BASE+370)\n> +#define V4L2_CID_MPEG_VIDEO_H264_SEI_FRAME_PACKING\t\t(V4L2_CID_CODEC_BASE+368)\n> +#define V4L2_CID_MPEG_VIDEO_H264_SEI_FP_CURRENT_FRAME_0\t\t(V4L2_CID_CODEC_BASE+369)\n> +#define V4L2_CID_MPEG_VIDEO_H264_SEI_FP_ARRANGEMENT_TYPE\t(V4L2_CID_CODEC_BASE+370)\n> enum v4l2_mpeg_video_h264_sei_fp_arrangement_type {\n> \tV4L2_MPEG_VIDEO_H264_SEI_FP_ARRANGEMENT_TYPE_CHECKERBOARD\t= 0,\n> \tV4L2_MPEG_VIDEO_H264_SEI_FP_ARRANGEMENT_TYPE_COLUMN\t\t= 1,\n> @@ -539,8 +558,8 @@ enum v4l2_mpeg_video_h264_sei_fp_arrangement_type {\n> \tV4L2_MPEG_VIDEO_H264_SEI_FP_ARRANGEMENT_TYPE_TOP_BOTTOM\t\t= 4,\n> \tV4L2_MPEG_VIDEO_H264_SEI_FP_ARRANGEMENT_TYPE_TEMPORAL\t\t= 5,\n> };\n> -#define V4L2_CID_MPEG_VIDEO_H264_FMO\t\t\t(V4L2_CID_MPEG_BASE+371)\n> -#define V4L2_CID_MPEG_VIDEO_H264_FMO_MAP_TYPE\t\t(V4L2_CID_MPEG_BASE+372)\n> +#define V4L2_CID_MPEG_VIDEO_H264_FMO\t\t\t(V4L2_CID_CODEC_BASE+371)\n> +#define V4L2_CID_MPEG_VIDEO_H264_FMO_MAP_TYPE\t\t(V4L2_CID_CODEC_BASE+372)\n> enum v4l2_mpeg_video_h264_fmo_map_type {\n> \tV4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_INTERLEAVED_SLICES\t\t= 0,\n> \tV4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_SCATTERED_SLICES\t\t= 1,\n> @@ -550,36 +569,45 @@ enum v4l2_mpeg_video_h264_fmo_map_type {\n> \tV4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_WIPE_SCAN\t\t\t= 5,\n> \tV4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_EXPLICIT\t\t\t= 6,\n> };\n> -#define V4L2_CID_MPEG_VIDEO_H264_FMO_SLICE_GROUP\t(V4L2_CID_MPEG_BASE+373)\n> -#define V4L2_CID_MPEG_VIDEO_H264_FMO_CHANGE_DIRECTION\t(V4L2_CID_MPEG_BASE+374)\n> +#define V4L2_CID_MPEG_VIDEO_H264_FMO_SLICE_GROUP\t(V4L2_CID_CODEC_BASE+373)\n> +#define V4L2_CID_MPEG_VIDEO_H264_FMO_CHANGE_DIRECTION\t(V4L2_CID_CODEC_BASE+374)\n> enum v4l2_mpeg_video_h264_fmo_change_dir {\n> \tV4L2_MPEG_VIDEO_H264_FMO_CHANGE_DIR_RIGHT\t= 0,\n> \tV4L2_MPEG_VIDEO_H264_FMO_CHANGE_DIR_LEFT\t= 1,\n> };\n> -#define V4L2_CID_MPEG_VIDEO_H264_FMO_CHANGE_RATE\t(V4L2_CID_MPEG_BASE+375)\n> -#define V4L2_CID_MPEG_VIDEO_H264_FMO_RUN_LENGTH\t\t(V4L2_CID_MPEG_BASE+376)\n> -#define V4L2_CID_MPEG_VIDEO_H264_ASO\t\t\t(V4L2_CID_MPEG_BASE+377)\n> -#define V4L2_CID_MPEG_VIDEO_H264_ASO_SLICE_ORDER\t(V4L2_CID_MPEG_BASE+378)\n> -#define V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING\t\t(V4L2_CID_MPEG_BASE+379)\n> -#define V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_TYPE\t(V4L2_CID_MPEG_BASE+380)\n> +#define V4L2_CID_MPEG_VIDEO_H264_FMO_CHANGE_RATE\t(V4L2_CID_CODEC_BASE+375)\n> +#define V4L2_CID_MPEG_VIDEO_H264_FMO_RUN_LENGTH\t\t(V4L2_CID_CODEC_BASE+376)\n> +#define V4L2_CID_MPEG_VIDEO_H264_ASO\t\t\t(V4L2_CID_CODEC_BASE+377)\n> +#define V4L2_CID_MPEG_VIDEO_H264_ASO_SLICE_ORDER\t(V4L2_CID_CODEC_BASE+378)\n> +#define V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING\t\t(V4L2_CID_CODEC_BASE+379)\n> +#define V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_TYPE\t(V4L2_CID_CODEC_BASE+380)\n> enum v4l2_mpeg_video_h264_hierarchical_coding_type {\n> \tV4L2_MPEG_VIDEO_H264_HIERARCHICAL_CODING_B\t= 0,\n> \tV4L2_MPEG_VIDEO_H264_HIERARCHICAL_CODING_P\t= 1,\n> };\n> -#define V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_LAYER\t(V4L2_CID_MPEG_BASE+381)\n> -#define V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_LAYER_QP\t(V4L2_CID_MPEG_BASE+382)\n> -#define V4L2_CID_MPEG_VIDEO_H264_CONSTRAINED_INTRA_PREDICTION\t(V4L2_CID_MPEG_BASE+383)\n> -#define V4L2_CID_MPEG_VIDEO_H264_CHROMA_QP_INDEX_OFFSET\t\t(V4L2_CID_MPEG_BASE+384)\n> -#define V4L2_CID_MPEG_VIDEO_H264_I_FRAME_MIN_QP\t(V4L2_CID_MPEG_BASE+385)\n> -#define V4L2_CID_MPEG_VIDEO_H264_I_FRAME_MAX_QP\t(V4L2_CID_MPEG_BASE+386)\n> -#define V4L2_CID_MPEG_VIDEO_H264_P_FRAME_MIN_QP\t(V4L2_CID_MPEG_BASE+387)\n> -#define V4L2_CID_MPEG_VIDEO_H264_P_FRAME_MAX_QP\t(V4L2_CID_MPEG_BASE+388)\n> -#define V4L2_CID_MPEG_VIDEO_MPEG4_I_FRAME_QP\t(V4L2_CID_MPEG_BASE+400)\n> -#define V4L2_CID_MPEG_VIDEO_MPEG4_P_FRAME_QP\t(V4L2_CID_MPEG_BASE+401)\n> -#define V4L2_CID_MPEG_VIDEO_MPEG4_B_FRAME_QP\t(V4L2_CID_MPEG_BASE+402)\n> -#define V4L2_CID_MPEG_VIDEO_MPEG4_MIN_QP\t(V4L2_CID_MPEG_BASE+403)\n> -#define V4L2_CID_MPEG_VIDEO_MPEG4_MAX_QP\t(V4L2_CID_MPEG_BASE+404)\n> -#define V4L2_CID_MPEG_VIDEO_MPEG4_LEVEL\t\t(V4L2_CID_MPEG_BASE+405)\n> +#define V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_LAYER\t(V4L2_CID_CODEC_BASE+381)\n> +#define V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_LAYER_QP\t(V4L2_CID_CODEC_BASE+382)\n> +#define V4L2_CID_MPEG_VIDEO_H264_CONSTRAINED_INTRA_PREDICTION\t(V4L2_CID_CODEC_BASE+383)\n> +#define V4L2_CID_MPEG_VIDEO_H264_CHROMA_QP_INDEX_OFFSET\t\t(V4L2_CID_CODEC_BASE+384)\n> +#define V4L2_CID_MPEG_VIDEO_H264_I_FRAME_MIN_QP\t(V4L2_CID_CODEC_BASE+385)\n> +#define V4L2_CID_MPEG_VIDEO_H264_I_FRAME_MAX_QP\t(V4L2_CID_CODEC_BASE+386)\n> +#define V4L2_CID_MPEG_VIDEO_H264_P_FRAME_MIN_QP\t(V4L2_CID_CODEC_BASE+387)\n> +#define V4L2_CID_MPEG_VIDEO_H264_P_FRAME_MAX_QP\t(V4L2_CID_CODEC_BASE+388)\n> +#define V4L2_CID_MPEG_VIDEO_H264_B_FRAME_MIN_QP\t(V4L2_CID_CODEC_BASE+389)\n> +#define V4L2_CID_MPEG_VIDEO_H264_B_FRAME_MAX_QP\t(V4L2_CID_CODEC_BASE+390)\n> +#define V4L2_CID_MPEG_VIDEO_H264_HIER_CODING_L0_BR\t(V4L2_CID_CODEC_BASE+391)\n> +#define V4L2_CID_MPEG_VIDEO_H264_HIER_CODING_L1_BR\t(V4L2_CID_CODEC_BASE+392)\n> +#define V4L2_CID_MPEG_VIDEO_H264_HIER_CODING_L2_BR\t(V4L2_CID_CODEC_BASE+393)\n> +#define V4L2_CID_MPEG_VIDEO_H264_HIER_CODING_L3_BR\t(V4L2_CID_CODEC_BASE+394)\n> +#define V4L2_CID_MPEG_VIDEO_H264_HIER_CODING_L4_BR\t(V4L2_CID_CODEC_BASE+395)\n> +#define V4L2_CID_MPEG_VIDEO_H264_HIER_CODING_L5_BR\t(V4L2_CID_CODEC_BASE+396)\n> +#define V4L2_CID_MPEG_VIDEO_H264_HIER_CODING_L6_BR\t(V4L2_CID_CODEC_BASE+397)\n> +#define V4L2_CID_MPEG_VIDEO_MPEG4_I_FRAME_QP\t(V4L2_CID_CODEC_BASE+400)\n> +#define V4L2_CID_MPEG_VIDEO_MPEG4_P_FRAME_QP\t(V4L2_CID_CODEC_BASE+401)\n> +#define V4L2_CID_MPEG_VIDEO_MPEG4_B_FRAME_QP\t(V4L2_CID_CODEC_BASE+402)\n> +#define V4L2_CID_MPEG_VIDEO_MPEG4_MIN_QP\t(V4L2_CID_CODEC_BASE+403)\n> +#define V4L2_CID_MPEG_VIDEO_MPEG4_MAX_QP\t(V4L2_CID_CODEC_BASE+404)\n> +#define V4L2_CID_MPEG_VIDEO_MPEG4_LEVEL\t\t(V4L2_CID_CODEC_BASE+405)\n> enum v4l2_mpeg_video_mpeg4_level {\n> \tV4L2_MPEG_VIDEO_MPEG4_LEVEL_0\t= 0,\n> \tV4L2_MPEG_VIDEO_MPEG4_LEVEL_0B\t= 1,\n> @@ -590,7 +618,7 @@ enum v4l2_mpeg_video_mpeg4_level {\n> \tV4L2_MPEG_VIDEO_MPEG4_LEVEL_4\t= 6,\n> \tV4L2_MPEG_VIDEO_MPEG4_LEVEL_5\t= 7,\n> };\n> -#define V4L2_CID_MPEG_VIDEO_MPEG4_PROFILE\t(V4L2_CID_MPEG_BASE+406)\n> +#define V4L2_CID_MPEG_VIDEO_MPEG4_PROFILE\t(V4L2_CID_CODEC_BASE+406)\n> enum v4l2_mpeg_video_mpeg4_profile {\n> \tV4L2_MPEG_VIDEO_MPEG4_PROFILE_SIMPLE\t\t\t\t= 0,\n> \tV4L2_MPEG_VIDEO_MPEG4_PROFILE_ADVANCED_SIMPLE\t\t\t= 1,\n> @@ -598,40 +626,40 @@ enum v4l2_mpeg_video_mpeg4_profile {\n> \tV4L2_MPEG_VIDEO_MPEG4_PROFILE_SIMPLE_SCALABLE\t\t\t= 3,\n> \tV4L2_MPEG_VIDEO_MPEG4_PROFILE_ADVANCED_CODING_EFFICIENCY\t= 4,\n> };\n> -#define V4L2_CID_MPEG_VIDEO_MPEG4_QPEL\t\t(V4L2_CID_MPEG_BASE+407)\n> +#define V4L2_CID_MPEG_VIDEO_MPEG4_QPEL\t\t(V4L2_CID_CODEC_BASE+407)\n> \n> /* Control IDs for VP8 streams\n> * Although VP8 is not part of MPEG we add these controls to the MPEG class\n> * as that class is already handling other video compression standards\n> */\n> -#define V4L2_CID_MPEG_VIDEO_VPX_NUM_PARTITIONS\t\t(V4L2_CID_MPEG_BASE+500)\n> +#define V4L2_CID_MPEG_VIDEO_VPX_NUM_PARTITIONS\t\t(V4L2_CID_CODEC_BASE+500)\n> enum v4l2_vp8_num_partitions {\n> \tV4L2_CID_MPEG_VIDEO_VPX_1_PARTITION\t= 0,\n> \tV4L2_CID_MPEG_VIDEO_VPX_2_PARTITIONS\t= 1,\n> \tV4L2_CID_MPEG_VIDEO_VPX_4_PARTITIONS\t= 2,\n> \tV4L2_CID_MPEG_VIDEO_VPX_8_PARTITIONS\t= 3,\n> };\n> -#define V4L2_CID_MPEG_VIDEO_VPX_IMD_DISABLE_4X4\t\t(V4L2_CID_MPEG_BASE+501)\n> -#define V4L2_CID_MPEG_VIDEO_VPX_NUM_REF_FRAMES\t\t(V4L2_CID_MPEG_BASE+502)\n> +#define V4L2_CID_MPEG_VIDEO_VPX_IMD_DISABLE_4X4\t\t(V4L2_CID_CODEC_BASE+501)\n> +#define V4L2_CID_MPEG_VIDEO_VPX_NUM_REF_FRAMES\t\t(V4L2_CID_CODEC_BASE+502)\n> enum v4l2_vp8_num_ref_frames {\n> \tV4L2_CID_MPEG_VIDEO_VPX_1_REF_FRAME\t= 0,\n> \tV4L2_CID_MPEG_VIDEO_VPX_2_REF_FRAME\t= 1,\n> \tV4L2_CID_MPEG_VIDEO_VPX_3_REF_FRAME\t= 2,\n> };\n> -#define V4L2_CID_MPEG_VIDEO_VPX_FILTER_LEVEL\t\t(V4L2_CID_MPEG_BASE+503)\n> -#define V4L2_CID_MPEG_VIDEO_VPX_FILTER_SHARPNESS\t(V4L2_CID_MPEG_BASE+504)\n> -#define V4L2_CID_MPEG_VIDEO_VPX_GOLDEN_FRAME_REF_PERIOD\t(V4L2_CID_MPEG_BASE+505)\n> -#define V4L2_CID_MPEG_VIDEO_VPX_GOLDEN_FRAME_SEL\t(V4L2_CID_MPEG_BASE+506)\n> +#define V4L2_CID_MPEG_VIDEO_VPX_FILTER_LEVEL\t\t(V4L2_CID_CODEC_BASE+503)\n> +#define V4L2_CID_MPEG_VIDEO_VPX_FILTER_SHARPNESS\t(V4L2_CID_CODEC_BASE+504)\n> +#define V4L2_CID_MPEG_VIDEO_VPX_GOLDEN_FRAME_REF_PERIOD\t(V4L2_CID_CODEC_BASE+505)\n> +#define V4L2_CID_MPEG_VIDEO_VPX_GOLDEN_FRAME_SEL\t(V4L2_CID_CODEC_BASE+506)\n> enum v4l2_vp8_golden_frame_sel {\n> \tV4L2_CID_MPEG_VIDEO_VPX_GOLDEN_FRAME_USE_PREV\t\t= 0,\n> \tV4L2_CID_MPEG_VIDEO_VPX_GOLDEN_FRAME_USE_REF_PERIOD\t= 1,\n> };\n> -#define V4L2_CID_MPEG_VIDEO_VPX_MIN_QP\t\t\t(V4L2_CID_MPEG_BASE+507)\n> -#define V4L2_CID_MPEG_VIDEO_VPX_MAX_QP\t\t\t(V4L2_CID_MPEG_BASE+508)\n> -#define V4L2_CID_MPEG_VIDEO_VPX_I_FRAME_QP\t\t(V4L2_CID_MPEG_BASE+509)\n> -#define V4L2_CID_MPEG_VIDEO_VPX_P_FRAME_QP\t\t(V4L2_CID_MPEG_BASE+510)\n> +#define V4L2_CID_MPEG_VIDEO_VPX_MIN_QP\t\t\t(V4L2_CID_CODEC_BASE+507)\n> +#define V4L2_CID_MPEG_VIDEO_VPX_MAX_QP\t\t\t(V4L2_CID_CODEC_BASE+508)\n> +#define V4L2_CID_MPEG_VIDEO_VPX_I_FRAME_QP\t\t(V4L2_CID_CODEC_BASE+509)\n> +#define V4L2_CID_MPEG_VIDEO_VPX_P_FRAME_QP\t\t(V4L2_CID_CODEC_BASE+510)\n> \n> -#define V4L2_CID_MPEG_VIDEO_VP8_PROFILE\t\t\t(V4L2_CID_MPEG_BASE+511)\n> +#define V4L2_CID_MPEG_VIDEO_VP8_PROFILE\t\t\t(V4L2_CID_CODEC_BASE+511)\n> enum v4l2_mpeg_video_vp8_profile {\n> \tV4L2_MPEG_VIDEO_VP8_PROFILE_0\t\t\t\t= 0,\n> \tV4L2_MPEG_VIDEO_VP8_PROFILE_1\t\t\t\t= 1,\n> @@ -640,42 +668,59 @@ enum v4l2_mpeg_video_vp8_profile {\n> };\n> /* Deprecated alias for compatibility reasons. */\n> #define V4L2_CID_MPEG_VIDEO_VPX_PROFILE\tV4L2_CID_MPEG_VIDEO_VP8_PROFILE\n> -#define V4L2_CID_MPEG_VIDEO_VP9_PROFILE\t\t\t(V4L2_CID_MPEG_BASE+512)\n> +#define V4L2_CID_MPEG_VIDEO_VP9_PROFILE\t\t\t(V4L2_CID_CODEC_BASE+512)\n> enum v4l2_mpeg_video_vp9_profile {\n> \tV4L2_MPEG_VIDEO_VP9_PROFILE_0\t\t\t\t= 0,\n> \tV4L2_MPEG_VIDEO_VP9_PROFILE_1\t\t\t\t= 1,\n> \tV4L2_MPEG_VIDEO_VP9_PROFILE_2\t\t\t\t= 2,\n> \tV4L2_MPEG_VIDEO_VP9_PROFILE_3\t\t\t\t= 3,\n> };\n> +#define V4L2_CID_MPEG_VIDEO_VP9_LEVEL\t\t\t(V4L2_CID_CODEC_BASE+513)\n> +enum v4l2_mpeg_video_vp9_level {\n> +\tV4L2_MPEG_VIDEO_VP9_LEVEL_1_0\t= 0,\n> +\tV4L2_MPEG_VIDEO_VP9_LEVEL_1_1\t= 1,\n> +\tV4L2_MPEG_VIDEO_VP9_LEVEL_2_0\t= 2,\n> +\tV4L2_MPEG_VIDEO_VP9_LEVEL_2_1\t= 3,\n> +\tV4L2_MPEG_VIDEO_VP9_LEVEL_3_0\t= 4,\n> +\tV4L2_MPEG_VIDEO_VP9_LEVEL_3_1\t= 5,\n> +\tV4L2_MPEG_VIDEO_VP9_LEVEL_4_0\t= 6,\n> +\tV4L2_MPEG_VIDEO_VP9_LEVEL_4_1\t= 7,\n> +\tV4L2_MPEG_VIDEO_VP9_LEVEL_5_0\t= 8,\n> +\tV4L2_MPEG_VIDEO_VP9_LEVEL_5_1\t= 9,\n> +\tV4L2_MPEG_VIDEO_VP9_LEVEL_5_2\t= 10,\n> +\tV4L2_MPEG_VIDEO_VP9_LEVEL_6_0\t= 11,\n> +\tV4L2_MPEG_VIDEO_VP9_LEVEL_6_1\t= 12,\n> +\tV4L2_MPEG_VIDEO_VP9_LEVEL_6_2\t= 13,\n> +};\n> \n> /* CIDs for HEVC encoding. */\n> \n> -#define V4L2_CID_MPEG_VIDEO_HEVC_MIN_QP\t\t(V4L2_CID_MPEG_BASE + 600)\n> -#define V4L2_CID_MPEG_VIDEO_HEVC_MAX_QP\t\t(V4L2_CID_MPEG_BASE + 601)\n> -#define V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_QP\t(V4L2_CID_MPEG_BASE + 602)\n> -#define V4L2_CID_MPEG_VIDEO_HEVC_P_FRAME_QP\t(V4L2_CID_MPEG_BASE + 603)\n> -#define V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_QP\t(V4L2_CID_MPEG_BASE + 604)\n> -#define V4L2_CID_MPEG_VIDEO_HEVC_HIER_QP\t(V4L2_CID_MPEG_BASE + 605)\n> -#define V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_TYPE (V4L2_CID_MPEG_BASE + 606)\n> +#define V4L2_CID_MPEG_VIDEO_HEVC_MIN_QP\t\t(V4L2_CID_CODEC_BASE + 600)\n> +#define V4L2_CID_MPEG_VIDEO_HEVC_MAX_QP\t\t(V4L2_CID_CODEC_BASE + 601)\n> +#define V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_QP\t(V4L2_CID_CODEC_BASE + 602)\n> +#define V4L2_CID_MPEG_VIDEO_HEVC_P_FRAME_QP\t(V4L2_CID_CODEC_BASE + 603)\n> +#define V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_QP\t(V4L2_CID_CODEC_BASE + 604)\n> +#define V4L2_CID_MPEG_VIDEO_HEVC_HIER_QP\t(V4L2_CID_CODEC_BASE + 605)\n> +#define V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_TYPE (V4L2_CID_CODEC_BASE + 606)\n> enum v4l2_mpeg_video_hevc_hier_coding_type {\n> \tV4L2_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_B\t= 0,\n> \tV4L2_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_P\t= 1,\n> };\n> -#define V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_LAYER\t(V4L2_CID_MPEG_BASE + 607)\n> -#define V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L0_QP\t(V4L2_CID_MPEG_BASE + 608)\n> -#define V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L1_QP\t(V4L2_CID_MPEG_BASE + 609)\n> -#define V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L2_QP\t(V4L2_CID_MPEG_BASE + 610)\n> -#define V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L3_QP\t(V4L2_CID_MPEG_BASE + 611)\n> -#define V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L4_QP\t(V4L2_CID_MPEG_BASE + 612)\n> -#define V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L5_QP\t(V4L2_CID_MPEG_BASE + 613)\n> -#define V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L6_QP\t(V4L2_CID_MPEG_BASE + 614)\n> -#define V4L2_CID_MPEG_VIDEO_HEVC_PROFILE\t(V4L2_CID_MPEG_BASE + 615)\n> +#define V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_LAYER\t(V4L2_CID_CODEC_BASE + 607)\n> +#define V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L0_QP\t(V4L2_CID_CODEC_BASE + 608)\n> +#define V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L1_QP\t(V4L2_CID_CODEC_BASE + 609)\n> +#define V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L2_QP\t(V4L2_CID_CODEC_BASE + 610)\n> +#define V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L3_QP\t(V4L2_CID_CODEC_BASE + 611)\n> +#define V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L4_QP\t(V4L2_CID_CODEC_BASE + 612)\n> +#define V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L5_QP\t(V4L2_CID_CODEC_BASE + 613)\n> +#define V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L6_QP\t(V4L2_CID_CODEC_BASE + 614)\n> +#define V4L2_CID_MPEG_VIDEO_HEVC_PROFILE\t(V4L2_CID_CODEC_BASE + 615)\n> enum v4l2_mpeg_video_hevc_profile {\n> \tV4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN = 0,\n> \tV4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE = 1,\n> \tV4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10 = 2,\n> };\n> -#define V4L2_CID_MPEG_VIDEO_HEVC_LEVEL\t\t(V4L2_CID_MPEG_BASE + 616)\n> +#define V4L2_CID_MPEG_VIDEO_HEVC_LEVEL\t\t(V4L2_CID_CODEC_BASE + 616)\n> enum v4l2_mpeg_video_hevc_level {\n> \tV4L2_MPEG_VIDEO_HEVC_LEVEL_1\t= 0,\n> \tV4L2_MPEG_VIDEO_HEVC_LEVEL_2\t= 1,\n> @@ -691,64 +736,78 @@ enum v4l2_mpeg_video_hevc_level {\n> \tV4L2_MPEG_VIDEO_HEVC_LEVEL_6_1\t= 11,\n> \tV4L2_MPEG_VIDEO_HEVC_LEVEL_6_2\t= 12,\n> };\n> -#define V4L2_CID_MPEG_VIDEO_HEVC_FRAME_RATE_RESOLUTION\t(V4L2_CID_MPEG_BASE + 617)\n> -#define V4L2_CID_MPEG_VIDEO_HEVC_TIER\t\t\t(V4L2_CID_MPEG_BASE + 618)\n> +#define V4L2_CID_MPEG_VIDEO_HEVC_FRAME_RATE_RESOLUTION\t(V4L2_CID_CODEC_BASE + 617)\n> +#define V4L2_CID_MPEG_VIDEO_HEVC_TIER\t\t\t(V4L2_CID_CODEC_BASE + 618)\n> enum v4l2_mpeg_video_hevc_tier {\n> \tV4L2_MPEG_VIDEO_HEVC_TIER_MAIN = 0,\n> \tV4L2_MPEG_VIDEO_HEVC_TIER_HIGH = 1,\n> };\n> -#define V4L2_CID_MPEG_VIDEO_HEVC_MAX_PARTITION_DEPTH\t(V4L2_CID_MPEG_BASE + 619)\n> -#define V4L2_CID_MPEG_VIDEO_HEVC_LOOP_FILTER_MODE\t(V4L2_CID_MPEG_BASE + 620)\n> +#define V4L2_CID_MPEG_VIDEO_HEVC_MAX_PARTITION_DEPTH\t(V4L2_CID_CODEC_BASE + 619)\n> +#define V4L2_CID_MPEG_VIDEO_HEVC_LOOP_FILTER_MODE\t(V4L2_CID_CODEC_BASE + 620)\n> enum v4l2_cid_mpeg_video_hevc_loop_filter_mode {\n> \tV4L2_MPEG_VIDEO_HEVC_LOOP_FILTER_MODE_DISABLED\t\t\t = 0,\n> \tV4L2_MPEG_VIDEO_HEVC_LOOP_FILTER_MODE_ENABLED\t\t\t = 1,\n> \tV4L2_MPEG_VIDEO_HEVC_LOOP_FILTER_MODE_DISABLED_AT_SLICE_BOUNDARY = 2,\n> };\n> -#define V4L2_CID_MPEG_VIDEO_HEVC_LF_BETA_OFFSET_DIV2\t(V4L2_CID_MPEG_BASE + 621)\n> -#define V4L2_CID_MPEG_VIDEO_HEVC_LF_TC_OFFSET_DIV2\t(V4L2_CID_MPEG_BASE + 622)\n> -#define V4L2_CID_MPEG_VIDEO_HEVC_REFRESH_TYPE\t\t(V4L2_CID_MPEG_BASE + 623)\n> +#define V4L2_CID_MPEG_VIDEO_HEVC_LF_BETA_OFFSET_DIV2\t(V4L2_CID_CODEC_BASE + 621)\n> +#define V4L2_CID_MPEG_VIDEO_HEVC_LF_TC_OFFSET_DIV2\t(V4L2_CID_CODEC_BASE + 622)\n> +#define V4L2_CID_MPEG_VIDEO_HEVC_REFRESH_TYPE\t\t(V4L2_CID_CODEC_BASE + 623)\n> enum v4l2_cid_mpeg_video_hevc_refresh_type {\n> \tV4L2_MPEG_VIDEO_HEVC_REFRESH_NONE\t\t= 0,\n> \tV4L2_MPEG_VIDEO_HEVC_REFRESH_CRA\t\t= 1,\n> \tV4L2_MPEG_VIDEO_HEVC_REFRESH_IDR\t\t= 2,\n> };\n> -#define V4L2_CID_MPEG_VIDEO_HEVC_REFRESH_PERIOD\t\t(V4L2_CID_MPEG_BASE + 624)\n> -#define V4L2_CID_MPEG_VIDEO_HEVC_LOSSLESS_CU\t\t(V4L2_CID_MPEG_BASE + 625)\n> -#define V4L2_CID_MPEG_VIDEO_HEVC_CONST_INTRA_PRED\t(V4L2_CID_MPEG_BASE + 626)\n> -#define V4L2_CID_MPEG_VIDEO_HEVC_WAVEFRONT\t\t(V4L2_CID_MPEG_BASE + 627)\n> -#define V4L2_CID_MPEG_VIDEO_HEVC_GENERAL_PB\t\t(V4L2_CID_MPEG_BASE + 628)\n> -#define V4L2_CID_MPEG_VIDEO_HEVC_TEMPORAL_ID\t\t(V4L2_CID_MPEG_BASE + 629)\n> -#define V4L2_CID_MPEG_VIDEO_HEVC_STRONG_SMOOTHING\t(V4L2_CID_MPEG_BASE + 630)\n> -#define V4L2_CID_MPEG_VIDEO_HEVC_MAX_NUM_MERGE_MV_MINUS1\t(V4L2_CID_MPEG_BASE + 631)\n> -#define V4L2_CID_MPEG_VIDEO_HEVC_INTRA_PU_SPLIT\t\t(V4L2_CID_MPEG_BASE + 632)\n> -#define V4L2_CID_MPEG_VIDEO_HEVC_TMV_PREDICTION\t\t(V4L2_CID_MPEG_BASE + 633)\n> -#define V4L2_CID_MPEG_VIDEO_HEVC_WITHOUT_STARTCODE\t(V4L2_CID_MPEG_BASE + 634)\n> -#define V4L2_CID_MPEG_VIDEO_HEVC_SIZE_OF_LENGTH_FIELD\t(V4L2_CID_MPEG_BASE + 635)\n> +#define V4L2_CID_MPEG_VIDEO_HEVC_REFRESH_PERIOD\t\t(V4L2_CID_CODEC_BASE + 624)\n> +#define V4L2_CID_MPEG_VIDEO_HEVC_LOSSLESS_CU\t\t(V4L2_CID_CODEC_BASE + 625)\n> +#define V4L2_CID_MPEG_VIDEO_HEVC_CONST_INTRA_PRED\t(V4L2_CID_CODEC_BASE + 626)\n> +#define V4L2_CID_MPEG_VIDEO_HEVC_WAVEFRONT\t\t(V4L2_CID_CODEC_BASE + 627)\n> +#define V4L2_CID_MPEG_VIDEO_HEVC_GENERAL_PB\t\t(V4L2_CID_CODEC_BASE + 628)\n> +#define V4L2_CID_MPEG_VIDEO_HEVC_TEMPORAL_ID\t\t(V4L2_CID_CODEC_BASE + 629)\n> +#define V4L2_CID_MPEG_VIDEO_HEVC_STRONG_SMOOTHING\t(V4L2_CID_CODEC_BASE + 630)\n> +#define V4L2_CID_MPEG_VIDEO_HEVC_MAX_NUM_MERGE_MV_MINUS1\t(V4L2_CID_CODEC_BASE + 631)\n> +#define V4L2_CID_MPEG_VIDEO_HEVC_INTRA_PU_SPLIT\t\t(V4L2_CID_CODEC_BASE + 632)\n> +#define V4L2_CID_MPEG_VIDEO_HEVC_TMV_PREDICTION\t\t(V4L2_CID_CODEC_BASE + 633)\n> +#define V4L2_CID_MPEG_VIDEO_HEVC_WITHOUT_STARTCODE\t(V4L2_CID_CODEC_BASE + 634)\n> +#define V4L2_CID_MPEG_VIDEO_HEVC_SIZE_OF_LENGTH_FIELD\t(V4L2_CID_CODEC_BASE + 635)\n> enum v4l2_cid_mpeg_video_hevc_size_of_length_field {\n> \tV4L2_MPEG_VIDEO_HEVC_SIZE_0\t\t= 0,\n> \tV4L2_MPEG_VIDEO_HEVC_SIZE_1\t\t= 1,\n> \tV4L2_MPEG_VIDEO_HEVC_SIZE_2\t\t= 2,\n> \tV4L2_MPEG_VIDEO_HEVC_SIZE_4\t\t= 3,\n> };\n> -#define V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L0_BR\t(V4L2_CID_MPEG_BASE + 636)\n> -#define V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L1_BR\t(V4L2_CID_MPEG_BASE + 637)\n> -#define V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L2_BR\t(V4L2_CID_MPEG_BASE + 638)\n> -#define V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L3_BR\t(V4L2_CID_MPEG_BASE + 639)\n> -#define V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L4_BR\t(V4L2_CID_MPEG_BASE + 640)\n> -#define V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L5_BR\t(V4L2_CID_MPEG_BASE + 641)\n> -#define V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L6_BR\t(V4L2_CID_MPEG_BASE + 642)\n> -#define V4L2_CID_MPEG_VIDEO_REF_NUMBER_FOR_PFRAMES\t(V4L2_CID_MPEG_BASE + 643)\n> -#define V4L2_CID_MPEG_VIDEO_PREPEND_SPSPPS_TO_IDR\t(V4L2_CID_MPEG_BASE + 644)\n> +#define V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L0_BR\t(V4L2_CID_CODEC_BASE + 636)\n> +#define V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L1_BR\t(V4L2_CID_CODEC_BASE + 637)\n> +#define V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L2_BR\t(V4L2_CID_CODEC_BASE + 638)\n> +#define V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L3_BR\t(V4L2_CID_CODEC_BASE + 639)\n> +#define V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L4_BR\t(V4L2_CID_CODEC_BASE + 640)\n> +#define V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L5_BR\t(V4L2_CID_CODEC_BASE + 641)\n> +#define V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L6_BR\t(V4L2_CID_CODEC_BASE + 642)\n> +#define V4L2_CID_MPEG_VIDEO_REF_NUMBER_FOR_PFRAMES\t(V4L2_CID_CODEC_BASE + 643)\n> +#define V4L2_CID_MPEG_VIDEO_PREPEND_SPSPPS_TO_IDR\t(V4L2_CID_CODEC_BASE + 644)\n> +#define V4L2_CID_MPEG_VIDEO_CONSTANT_QUALITY\t\t(V4L2_CID_CODEC_BASE + 645)\n> +#define V4L2_CID_MPEG_VIDEO_FRAME_SKIP_MODE\t\t(V4L2_CID_CODEC_BASE + 646)\n> +enum v4l2_mpeg_video_frame_skip_mode {\n> +\tV4L2_MPEG_VIDEO_FRAME_SKIP_MODE_DISABLED\t= 0,\n> +\tV4L2_MPEG_VIDEO_FRAME_SKIP_MODE_LEVEL_LIMIT\t= 1,\n> +\tV4L2_MPEG_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT\t= 2,\n> +};\n> +\n> +#define V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_MIN_QP (V4L2_CID_CODEC_BASE + 647)\n> +#define V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_MAX_QP (V4L2_CID_CODEC_BASE + 648)\n> +#define V4L2_CID_MPEG_VIDEO_HEVC_P_FRAME_MIN_QP (V4L2_CID_CODEC_BASE + 649)\n> +#define V4L2_CID_MPEG_VIDEO_HEVC_P_FRAME_MAX_QP (V4L2_CID_CODEC_BASE + 650)\n> +#define V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_MIN_QP (V4L2_CID_CODEC_BASE + 651)\n> +#define V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_MAX_QP (V4L2_CID_CODEC_BASE + 652)\n> \n> /* MPEG-class control IDs specific to the CX2341x driver as defined by V4L2 */\n> -#define V4L2_CID_MPEG_CX2341X_BASE\t\t\t\t(V4L2_CTRL_CLASS_MPEG | 0x1000)\n> -#define V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE\t\t(V4L2_CID_MPEG_CX2341X_BASE+0)\n> +#define V4L2_CID_CODEC_CX2341X_BASE\t\t\t\t(V4L2_CTRL_CLASS_CODEC | 0x1000)\n> +#define V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE\t\t(V4L2_CID_CODEC_CX2341X_BASE+0)\n> enum v4l2_mpeg_cx2341x_video_spatial_filter_mode {\n> \tV4L2_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE_MANUAL = 0,\n> \tV4L2_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE_AUTO = 1,\n> };\n> -#define V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER\t\t(V4L2_CID_MPEG_CX2341X_BASE+1)\n> -#define V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE\t(V4L2_CID_MPEG_CX2341X_BASE+2)\n> +#define V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER\t\t(V4L2_CID_CODEC_CX2341X_BASE+1)\n> +#define V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE\t(V4L2_CID_CODEC_CX2341X_BASE+2)\n> enum v4l2_mpeg_cx2341x_video_luma_spatial_filter_type {\n> \tV4L2_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE_OFF = 0,\n> \tV4L2_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE_1D_HOR = 1,\n> @@ -756,18 +815,18 @@ enum v4l2_mpeg_cx2341x_video_luma_spatial_filter_type {\n> \tV4L2_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE_2D_HV_SEPARABLE = 3,\n> \tV4L2_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE_2D_SYM_NON_SEPARABLE = 4,\n> };\n> -#define V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE\t(V4L2_CID_MPEG_CX2341X_BASE+3)\n> +#define V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE\t(V4L2_CID_CODEC_CX2341X_BASE+3)\n> enum v4l2_mpeg_cx2341x_video_chroma_spatial_filter_type {\n> \tV4L2_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE_OFF = 0,\n> \tV4L2_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE_1D_HOR = 1,\n> };\n> -#define V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE\t(V4L2_CID_MPEG_CX2341X_BASE+4)\n> +#define V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE\t(V4L2_CID_CODEC_CX2341X_BASE+4)\n> enum v4l2_mpeg_cx2341x_video_temporal_filter_mode {\n> \tV4L2_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE_MANUAL = 0,\n> \tV4L2_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE_AUTO = 1,\n> };\n> -#define V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER\t\t(V4L2_CID_MPEG_CX2341X_BASE+5)\n> -#define V4L2_CID_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE\t\t(V4L2_CID_MPEG_CX2341X_BASE+6)\n> +#define V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER\t\t(V4L2_CID_CODEC_CX2341X_BASE+5)\n> +#define V4L2_CID_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE\t\t(V4L2_CID_CODEC_CX2341X_BASE+6)\n> enum v4l2_mpeg_cx2341x_video_median_filter_type {\n> \tV4L2_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE_OFF = 0,\n> \tV4L2_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE_HOR = 1,\n> @@ -775,38 +834,38 @@ enum v4l2_mpeg_cx2341x_video_median_filter_type {\n> \tV4L2_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE_HOR_VERT = 3,\n> \tV4L2_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE_DIAG = 4,\n> };\n> -#define V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_BOTTOM\t(V4L2_CID_MPEG_CX2341X_BASE+7)\n> -#define V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_TOP\t(V4L2_CID_MPEG_CX2341X_BASE+8)\n> -#define V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_BOTTOM\t(V4L2_CID_MPEG_CX2341X_BASE+9)\n> -#define V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_TOP\t(V4L2_CID_MPEG_CX2341X_BASE+10)\n> -#define V4L2_CID_MPEG_CX2341X_STREAM_INSERT_NAV_PACKETS\t\t(V4L2_CID_MPEG_CX2341X_BASE+11)\n> +#define V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_BOTTOM\t(V4L2_CID_CODEC_CX2341X_BASE+7)\n> +#define V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_TOP\t(V4L2_CID_CODEC_CX2341X_BASE+8)\n> +#define V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_BOTTOM\t(V4L2_CID_CODEC_CX2341X_BASE+9)\n> +#define V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_TOP\t(V4L2_CID_CODEC_CX2341X_BASE+10)\n> +#define V4L2_CID_MPEG_CX2341X_STREAM_INSERT_NAV_PACKETS\t\t(V4L2_CID_CODEC_CX2341X_BASE+11)\n> \n> /* MPEG-class control IDs specific to the Samsung MFC 5.1 driver as defined by V4L2 */\n> -#define V4L2_CID_MPEG_MFC51_BASE\t\t\t\t(V4L2_CTRL_CLASS_MPEG | 0x1100)\n> +#define V4L2_CID_CODEC_MFC51_BASE\t\t\t\t(V4L2_CTRL_CLASS_CODEC | 0x1100)\n> \n> -#define V4L2_CID_MPEG_MFC51_VIDEO_DECODER_H264_DISPLAY_DELAY\t\t(V4L2_CID_MPEG_MFC51_BASE+0)\n> -#define V4L2_CID_MPEG_MFC51_VIDEO_DECODER_H264_DISPLAY_DELAY_ENABLE\t(V4L2_CID_MPEG_MFC51_BASE+1)\n> -#define V4L2_CID_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE\t\t\t(V4L2_CID_MPEG_MFC51_BASE+2)\n> +#define V4L2_CID_MPEG_MFC51_VIDEO_DECODER_H264_DISPLAY_DELAY\t\t(V4L2_CID_CODEC_MFC51_BASE+0)\n> +#define V4L2_CID_MPEG_MFC51_VIDEO_DECODER_H264_DISPLAY_DELAY_ENABLE\t(V4L2_CID_CODEC_MFC51_BASE+1)\n> +#define V4L2_CID_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE\t\t\t(V4L2_CID_CODEC_MFC51_BASE+2)\n> enum v4l2_mpeg_mfc51_video_frame_skip_mode {\n> \tV4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_DISABLED\t\t= 0,\n> \tV4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_LEVEL_LIMIT\t= 1,\n> \tV4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT\t\t= 2,\n> };\n> -#define V4L2_CID_MPEG_MFC51_VIDEO_FORCE_FRAME_TYPE\t\t\t(V4L2_CID_MPEG_MFC51_BASE+3)\n> +#define V4L2_CID_MPEG_MFC51_VIDEO_FORCE_FRAME_TYPE\t\t\t(V4L2_CID_CODEC_MFC51_BASE+3)\n> enum v4l2_mpeg_mfc51_video_force_frame_type {\n> \tV4L2_MPEG_MFC51_VIDEO_FORCE_FRAME_TYPE_DISABLED\t\t= 0,\n> \tV4L2_MPEG_MFC51_VIDEO_FORCE_FRAME_TYPE_I_FRAME\t\t= 1,\n> \tV4L2_MPEG_MFC51_VIDEO_FORCE_FRAME_TYPE_NOT_CODED\t= 2,\n> };\n> -#define V4L2_CID_MPEG_MFC51_VIDEO_PADDING\t\t\t\t(V4L2_CID_MPEG_MFC51_BASE+4)\n> -#define V4L2_CID_MPEG_MFC51_VIDEO_PADDING_YUV\t\t\t\t(V4L2_CID_MPEG_MFC51_BASE+5)\n> -#define V4L2_CID_MPEG_MFC51_VIDEO_RC_FIXED_TARGET_BIT\t\t\t(V4L2_CID_MPEG_MFC51_BASE+6)\n> -#define V4L2_CID_MPEG_MFC51_VIDEO_RC_REACTION_COEFF\t\t\t(V4L2_CID_MPEG_MFC51_BASE+7)\n> -#define V4L2_CID_MPEG_MFC51_VIDEO_H264_ADAPTIVE_RC_ACTIVITY\t\t(V4L2_CID_MPEG_MFC51_BASE+50)\n> -#define V4L2_CID_MPEG_MFC51_VIDEO_H264_ADAPTIVE_RC_DARK\t\t\t(V4L2_CID_MPEG_MFC51_BASE+51)\n> -#define V4L2_CID_MPEG_MFC51_VIDEO_H264_ADAPTIVE_RC_SMOOTH\t\t(V4L2_CID_MPEG_MFC51_BASE+52)\n> -#define V4L2_CID_MPEG_MFC51_VIDEO_H264_ADAPTIVE_RC_STATIC\t\t(V4L2_CID_MPEG_MFC51_BASE+53)\n> -#define V4L2_CID_MPEG_MFC51_VIDEO_H264_NUM_REF_PIC_FOR_P\t\t(V4L2_CID_MPEG_MFC51_BASE+54)\n> +#define V4L2_CID_MPEG_MFC51_VIDEO_PADDING\t\t\t\t(V4L2_CID_CODEC_MFC51_BASE+4)\n> +#define V4L2_CID_MPEG_MFC51_VIDEO_PADDING_YUV\t\t\t\t(V4L2_CID_CODEC_MFC51_BASE+5)\n> +#define V4L2_CID_MPEG_MFC51_VIDEO_RC_FIXED_TARGET_BIT\t\t\t(V4L2_CID_CODEC_MFC51_BASE+6)\n> +#define V4L2_CID_MPEG_MFC51_VIDEO_RC_REACTION_COEFF\t\t\t(V4L2_CID_CODEC_MFC51_BASE+7)\n> +#define V4L2_CID_MPEG_MFC51_VIDEO_H264_ADAPTIVE_RC_ACTIVITY\t\t(V4L2_CID_CODEC_MFC51_BASE+50)\n> +#define V4L2_CID_MPEG_MFC51_VIDEO_H264_ADAPTIVE_RC_DARK\t\t\t(V4L2_CID_CODEC_MFC51_BASE+51)\n> +#define V4L2_CID_MPEG_MFC51_VIDEO_H264_ADAPTIVE_RC_SMOOTH\t\t(V4L2_CID_CODEC_MFC51_BASE+52)\n> +#define V4L2_CID_MPEG_MFC51_VIDEO_H264_ADAPTIVE_RC_STATIC\t\t(V4L2_CID_CODEC_MFC51_BASE+53)\n> +#define V4L2_CID_MPEG_MFC51_VIDEO_H264_NUM_REF_PIC_FOR_P\t\t(V4L2_CID_CODEC_MFC51_BASE+54)\n> \n> /* Camera class control IDs */\n> \n> @@ -1049,6 +1108,7 @@ enum v4l2_jpeg_chroma_subsampling {\n> #define V4L2_CID_TEST_PATTERN_GREENR\t\t(V4L2_CID_IMAGE_SOURCE_CLASS_BASE + 5)\n> #define V4L2_CID_TEST_PATTERN_BLUE\t\t(V4L2_CID_IMAGE_SOURCE_CLASS_BASE + 6)\n> #define V4L2_CID_TEST_PATTERN_GREENB\t\t(V4L2_CID_IMAGE_SOURCE_CLASS_BASE + 7)\n> +#define V4L2_CID_UNIT_CELL_SIZE\t\t\t(V4L2_CID_IMAGE_SOURCE_CLASS_BASE + 8)\n> \n> \n> /* Image processing controls */\n> @@ -1142,4 +1202,468 @@ enum v4l2_detect_md_mode {\n> #define V4L2_CID_DETECT_MD_THRESHOLD_GRID\t(V4L2_CID_DETECT_CLASS_BASE + 3)\n> #define V4L2_CID_DETECT_MD_REGION_GRID\t\t(V4L2_CID_DETECT_CLASS_BASE + 4)\n> \n> +\n> +/* Stateless CODECs controls */\n> +#define V4L2_CID_CODEC_STATELESS_BASE (V4L2_CTRL_CLASS_CODEC_STATELESS | 0x900)\n> +#define V4L2_CID_CODEC_STATELESS_CLASS (V4L2_CTRL_CLASS_CODEC_STATELESS | 1)\n> +\n> +#define V4L2_CID_STATELESS_H264_DECODE_MODE\t(V4L2_CID_CODEC_STATELESS_BASE + 0)\n> +/**\n> + * enum v4l2_stateless_h264_decode_mode - Decoding mode\n> + *\n> + * @V4L2_STATELESS_H264_DECODE_MODE_SLICE_BASED: indicates that decoding\n> + * is performed one slice at a time. In this mode,\n> + * V4L2_CID_STATELESS_H264_SLICE_PARAMS must contain the parsed slice\n> + * parameters and the OUTPUT buffer must contain a single slice.\n> + * V4L2_BUF_CAP_SUPPORTS_M2M_HOLD_CAPTURE_BUF feature is used\n> + * in order to support multislice frames.\n> + * @V4L2_STATELESS_H264_DECODE_MODE_FRAME_BASED: indicates that\n> + * decoding is performed per frame. The OUTPUT buffer must contain\n> + * all slices and also both fields. This mode is typically supported\n> + * by device drivers that are able to parse the slice(s) header(s)\n> + * in hardware. When this mode is selected,\n> + * V4L2_CID_STATELESS_H264_SLICE_PARAMS is not used.\n> + */\n> +enum v4l2_stateless_h264_decode_mode {\n> +\tV4L2_STATELESS_H264_DECODE_MODE_SLICE_BASED,\n> +\tV4L2_STATELESS_H264_DECODE_MODE_FRAME_BASED,\n> +};\n> +\n> +#define V4L2_CID_STATELESS_H264_START_CODE\t(V4L2_CID_CODEC_STATELESS_BASE + 1)\n> +/**\n> + * enum v4l2_stateless_h264_start_code - Start code\n> + *\n> + * @V4L2_STATELESS_H264_START_CODE_NONE: slices are passed\n> + * to the driver without any start code.\n> + * @V4L2_STATELESS_H264_START_CODE_ANNEX_B: slices are passed\n> + * to the driver with an Annex B start code prefix\n> + * (legal start codes can be 3-bytes 0x000001 or 4-bytes 0x00000001).\n> + * This mode is typically supported by device drivers that parse\n> + * the start code in hardware.\n> + */\n> +enum v4l2_stateless_h264_start_code {\n> +\tV4L2_STATELESS_H264_START_CODE_NONE,\n> +\tV4L2_STATELESS_H264_START_CODE_ANNEX_B,\n> +};\n> +\n> +#define V4L2_H264_SPS_CONSTRAINT_SET0_FLAG\t\t\t0x01\n> +#define V4L2_H264_SPS_CONSTRAINT_SET1_FLAG\t\t\t0x02\n> +#define V4L2_H264_SPS_CONSTRAINT_SET2_FLAG\t\t\t0x04\n> +#define V4L2_H264_SPS_CONSTRAINT_SET3_FLAG\t\t\t0x08\n> +#define V4L2_H264_SPS_CONSTRAINT_SET4_FLAG\t\t\t0x10\n> +#define V4L2_H264_SPS_CONSTRAINT_SET5_FLAG\t\t\t0x20\n> +\n> +#define V4L2_H264_SPS_FLAG_SEPARATE_COLOUR_PLANE\t\t0x01\n> +#define V4L2_H264_SPS_FLAG_QPPRIME_Y_ZERO_TRANSFORM_BYPASS\t0x02\n> +#define V4L2_H264_SPS_FLAG_DELTA_PIC_ORDER_ALWAYS_ZERO\t\t0x04\n> +#define V4L2_H264_SPS_FLAG_GAPS_IN_FRAME_NUM_VALUE_ALLOWED\t0x08\n> +#define V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY\t\t\t0x10\n> +#define V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD\t\t0x20\n> +#define V4L2_H264_SPS_FLAG_DIRECT_8X8_INFERENCE\t\t\t0x40\n> +\n> +#define V4L2_H264_SPS_HAS_CHROMA_FORMAT(sps) \\\n> +\t((sps)->profile_idc == 100 || (sps)->profile_idc == 110 || \\\n> +\t (sps)->profile_idc == 122 || (sps)->profile_idc == 244 || \\\n> +\t (sps)->profile_idc == 44 || (sps)->profile_idc == 83 || \\\n> +\t (sps)->profile_idc == 86 || (sps)->profile_idc == 118 || \\\n> +\t (sps)->profile_idc == 128 || (sps)->profile_idc == 138 || \\\n> +\t (sps)->profile_idc == 139 || (sps)->profile_idc == 134 || \\\n> +\t (sps)->profile_idc == 135)\n> +\n> +#define V4L2_CID_STATELESS_H264_SPS\t\t(V4L2_CID_CODEC_STATELESS_BASE + 2)\n> +/**\n> + * struct v4l2_ctrl_h264_sps - H264 sequence parameter set\n> + *\n> + * All the members on this sequence parameter set structure match the\n> + * sequence parameter set syntax as specified by the H264 specification.\n> + *\n> + * @profile_idc: see H264 specification.\n> + * @constraint_set_flags: see H264 specification.\n> + * @level_idc: see H264 specification.\n> + * @seq_parameter_set_id: see H264 specification.\n> + * @chroma_format_idc: see H264 specification.\n> + * @bit_depth_luma_minus8: see H264 specification.\n> + * @bit_depth_chroma_minus8: see H264 specification.\n> + * @log2_max_frame_num_minus4: see H264 specification.\n> + * @pic_order_cnt_type: see H264 specification.\n> + * @log2_max_pic_order_cnt_lsb_minus4: see H264 specification.\n> + * @max_num_ref_frames: see H264 specification.\n> + * @num_ref_frames_in_pic_order_cnt_cycle: see H264 specification.\n> + * @offset_for_ref_frame: see H264 specification.\n> + * @offset_for_non_ref_pic: see H264 specification.\n> + * @offset_for_top_to_bottom_field: see H264 specification.\n> + * @pic_width_in_mbs_minus1: see H264 specification.\n> + * @pic_height_in_map_units_minus1: see H264 specification.\n> + * @flags: see V4L2_H264_SPS_FLAG_{}.\n> + */\n> +struct v4l2_ctrl_h264_sps {\n> +\t__u8 profile_idc;\n> +\t__u8 constraint_set_flags;\n> +\t__u8 level_idc;\n> +\t__u8 seq_parameter_set_id;\n> +\t__u8 chroma_format_idc;\n> +\t__u8 bit_depth_luma_minus8;\n> +\t__u8 bit_depth_chroma_minus8;\n> +\t__u8 log2_max_frame_num_minus4;\n> +\t__u8 pic_order_cnt_type;\n> +\t__u8 log2_max_pic_order_cnt_lsb_minus4;\n> +\t__u8 max_num_ref_frames;\n> +\t__u8 num_ref_frames_in_pic_order_cnt_cycle;\n> +\t__s32 offset_for_ref_frame[255];\n> +\t__s32 offset_for_non_ref_pic;\n> +\t__s32 offset_for_top_to_bottom_field;\n> +\t__u16 pic_width_in_mbs_minus1;\n> +\t__u16 pic_height_in_map_units_minus1;\n> +\t__u32 flags;\n> +};\n> +\n> +#define V4L2_H264_PPS_FLAG_ENTROPY_CODING_MODE\t\t\t\t0x0001\n> +#define V4L2_H264_PPS_FLAG_BOTTOM_FIELD_PIC_ORDER_IN_FRAME_PRESENT\t0x0002\n> +#define V4L2_H264_PPS_FLAG_WEIGHTED_PRED\t\t\t\t0x0004\n> +#define V4L2_H264_PPS_FLAG_DEBLOCKING_FILTER_CONTROL_PRESENT\t\t0x0008\n> +#define V4L2_H264_PPS_FLAG_CONSTRAINED_INTRA_PRED\t\t\t0x0010\n> +#define V4L2_H264_PPS_FLAG_REDUNDANT_PIC_CNT_PRESENT\t\t\t0x0020\n> +#define V4L2_H264_PPS_FLAG_TRANSFORM_8X8_MODE\t\t\t\t0x0040\n> +#define V4L2_H264_PPS_FLAG_SCALING_MATRIX_PRESENT\t\t\t0x0080\n> +\n> +#define V4L2_CID_STATELESS_H264_PPS\t\t(V4L2_CID_CODEC_STATELESS_BASE + 3)\n> +/**\n> + * struct v4l2_ctrl_h264_pps - H264 picture parameter set\n> + *\n> + * Except where noted, all the members on this picture parameter set\n> + * structure match the sequence parameter set syntax as specified\n> + * by the H264 specification.\n> + *\n> + * In particular, V4L2_H264_PPS_FLAG_SCALING_MATRIX_PRESENT flag\n> + * has a specific meaning. This flag should be set if a non-flat\n> + * scaling matrix applies to the picture. In this case, applications\n> + * are expected to use V4L2_CID_STATELESS_H264_SCALING_MATRIX,\n> + * to pass the values of the non-flat matrices.\n> + *\n> + * @pic_parameter_set_id: see H264 specification.\n> + * @seq_parameter_set_id: see H264 specification.\n> + * @num_slice_groups_minus1: see H264 specification.\n> + * @num_ref_idx_l0_default_active_minus1: see H264 specification.\n> + * @num_ref_idx_l1_default_active_minus1: see H264 specification.\n> + * @weighted_bipred_idc: see H264 specification.\n> + * @pic_init_qp_minus26: see H264 specification.\n> + * @pic_init_qs_minus26: see H264 specification.\n> + * @chroma_qp_index_offset: see H264 specification.\n> + * @second_chroma_qp_index_offset: see H264 specification.\n> + * @flags: see V4L2_H264_PPS_FLAG_{}.\n> + */\n> +struct v4l2_ctrl_h264_pps {\n> +\t__u8 pic_parameter_set_id;\n> +\t__u8 seq_parameter_set_id;\n> +\t__u8 num_slice_groups_minus1;\n> +\t__u8 num_ref_idx_l0_default_active_minus1;\n> +\t__u8 num_ref_idx_l1_default_active_minus1;\n> +\t__u8 weighted_bipred_idc;\n> +\t__s8 pic_init_qp_minus26;\n> +\t__s8 pic_init_qs_minus26;\n> +\t__s8 chroma_qp_index_offset;\n> +\t__s8 second_chroma_qp_index_offset;\n> +\t__u16 flags;\n> +};\n> +\n> +#define V4L2_CID_STATELESS_H264_SCALING_MATRIX\t(V4L2_CID_CODEC_STATELESS_BASE + 4)\n> +/**\n> + * struct v4l2_ctrl_h264_scaling_matrix - H264 scaling matrices\n> + *\n> + * @scaling_list_4x4: scaling matrix after applying the inverse\n> + * scanning process. Expected list order is Intra Y, Intra Cb,\n> + * Intra Cr, Inter Y, Inter Cb, Inter Cr. The values on each\n> + * scaling list are expected in raster scan order.\n> + * @scaling_list_8x8: scaling matrix after applying the inverse\n> + * scanning process. Expected list order is Intra Y, Inter Y,\n> + * Intra Cb, Inter Cb, Intra Cr, Inter Cr. The values on each\n> + * scaling list are expected in raster scan order.\n> + *\n> + * Note that the list order is different for the 4x4 and 8x8\n> + * matrices as per the H264 specification, see table 7-2 \"Assignment\n> + * of mnemonic names to scaling list indices and specification of\n> + * fall-back rule\".\n> + */\n> +struct v4l2_ctrl_h264_scaling_matrix {\n> +\t__u8 scaling_list_4x4[6][16];\n> +\t__u8 scaling_list_8x8[6][64];\n> +};\n> +\n> +struct v4l2_h264_weight_factors {\n> +\t__s16 luma_weight[32];\n> +\t__s16 luma_offset[32];\n> +\t__s16 chroma_weight[32][2];\n> +\t__s16 chroma_offset[32][2];\n> +};\n> +\n> +#define V4L2_H264_CTRL_PRED_WEIGHTS_REQUIRED(pps, slice) \\\n> +\t((((pps)->flags & V4L2_H264_PPS_FLAG_WEIGHTED_PRED) && \\\n> +\t ((slice)->slice_type == V4L2_H264_SLICE_TYPE_P || \\\n> +\t (slice)->slice_type == V4L2_H264_SLICE_TYPE_SP)) || \\\n> +\t ((pps)->weighted_bipred_idc == 1 && \\\n> +\t (slice)->slice_type == V4L2_H264_SLICE_TYPE_B))\n> +\n> +#define V4L2_CID_STATELESS_H264_PRED_WEIGHTS\t(V4L2_CID_CODEC_STATELESS_BASE + 5)\n> +/**\n> + * struct v4l2_ctrl_h264_pred_weights - Prediction weight table\n> + *\n> + * Prediction weight table, which matches the syntax specified\n> + * by the H264 specification.\n> + *\n> + * @luma_log2_weight_denom: see H264 specification.\n> + * @chroma_log2_weight_denom: see H264 specification.\n> + * @weight_factors: luma and chroma weight factors.\n> + */\n> +struct v4l2_ctrl_h264_pred_weights {\n> +\t__u16 luma_log2_weight_denom;\n> +\t__u16 chroma_log2_weight_denom;\n> +\tstruct v4l2_h264_weight_factors weight_factors[2];\n> +};\n> +\n> +#define V4L2_H264_SLICE_TYPE_P\t\t\t\t0\n> +#define V4L2_H264_SLICE_TYPE_B\t\t\t\t1\n> +#define V4L2_H264_SLICE_TYPE_I\t\t\t\t2\n> +#define V4L2_H264_SLICE_TYPE_SP\t\t\t\t3\n> +#define V4L2_H264_SLICE_TYPE_SI\t\t\t\t4\n> +\n> +#define V4L2_H264_SLICE_FLAG_DIRECT_SPATIAL_MV_PRED\t0x01\n> +#define V4L2_H264_SLICE_FLAG_SP_FOR_SWITCH\t\t0x02\n> +\n> +#define V4L2_H264_TOP_FIELD_REF\t\t\t\t0x1\n> +#define V4L2_H264_BOTTOM_FIELD_REF\t\t\t0x2\n> +#define V4L2_H264_FRAME_REF\t\t\t\t0x3\n> +\n> +/**\n> + * struct v4l2_h264_reference - H264 picture reference\n> + *\n> + * @fields: indicates how the picture is referenced.\n> + * Valid values are V4L2_H264_{}_REF.\n> + * @index: index into v4l2_ctrl_h264_decode_params.dpb[].\n> + */\n> +struct v4l2_h264_reference {\n> +\t__u8 fields;\n> +\t__u8 index;\n> +};\n> +\n> +/*\n> + * Maximum DPB size, as specified by section 'A.3.1 Level limits\n> + * common to the Baseline, Main, and Extended profiles'.\n> + */\n> +#define V4L2_H264_NUM_DPB_ENTRIES 16\n> +#define V4L2_H264_REF_LIST_LEN (2 * V4L2_H264_NUM_DPB_ENTRIES)\n> +\n> +#define V4L2_CID_STATELESS_H264_SLICE_PARAMS\t(V4L2_CID_CODEC_STATELESS_BASE + 6)\n> +/**\n> + * struct v4l2_ctrl_h264_slice_params - H264 slice parameters\n> + *\n> + * This structure holds the H264 syntax elements that are specified\n> + * as non-invariant for the slices in a given frame.\n> + *\n> + * Slice invariant syntax elements are contained in struct\n> + * v4l2_ctrl_h264_decode_params. This is done to reduce the API surface\n> + * on frame-based decoders, where slice header parsing is done by the\n> + * hardware.\n> + *\n> + * Slice invariant syntax elements are specified in specification section\n> + * \"7.4.3 Slice header semantics\".\n> + *\n> + * Except where noted, the members on this struct match the slice header syntax.\n> + *\n> + * @header_bit_size: offset in bits to slice_data() from the beginning of this slice.\n> + * @first_mb_in_slice: see H264 specification.\n> + * @slice_type: see H264 specification.\n> + * @colour_plane_id: see H264 specification.\n> + * @redundant_pic_cnt: see H264 specification.\n> + * @cabac_init_idc: see H264 specification.\n> + * @slice_qp_delta: see H264 specification.\n> + * @slice_qs_delta: see H264 specification.\n> + * @disable_deblocking_filter_idc: see H264 specification.\n> + * @slice_alpha_c0_offset_div2: see H264 specification.\n> + * @slice_beta_offset_div2: see H264 specification.\n> + * @num_ref_idx_l0_active_minus1: see H264 specification.\n> + * @num_ref_idx_l1_active_minus1: see H264 specification.\n> + * @reserved: padding field. Should be zeroed by applications.\n> + * @ref_pic_list0: reference picture list 0 after applying the per-slice modifications.\n> + * @ref_pic_list1: reference picture list 1 after applying the per-slice modifications.\n> + * @flags: see V4L2_H264_SLICE_FLAG_{}.\n> + */\n> +struct v4l2_ctrl_h264_slice_params {\n> +\t__u32 header_bit_size;\n> +\t__u32 first_mb_in_slice;\n> +\t__u8 slice_type;\n> +\t__u8 colour_plane_id;\n> +\t__u8 redundant_pic_cnt;\n> +\t__u8 cabac_init_idc;\n> +\t__s8 slice_qp_delta;\n> +\t__s8 slice_qs_delta;\n> +\t__u8 disable_deblocking_filter_idc;\n> +\t__s8 slice_alpha_c0_offset_div2;\n> +\t__s8 slice_beta_offset_div2;\n> +\t__u8 num_ref_idx_l0_active_minus1;\n> +\t__u8 num_ref_idx_l1_active_minus1;\n> +\n> +\t__u8 reserved;\n> +\n> +\tstruct v4l2_h264_reference ref_pic_list0[V4L2_H264_REF_LIST_LEN];\n> +\tstruct v4l2_h264_reference ref_pic_list1[V4L2_H264_REF_LIST_LEN];\n> +\n> +\t__u32 flags;\n> +};\n> +\n> +#define V4L2_H264_DPB_ENTRY_FLAG_VALID\t\t0x01\n> +#define V4L2_H264_DPB_ENTRY_FLAG_ACTIVE\t\t0x02\n> +#define V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM\t0x04\n> +#define V4L2_H264_DPB_ENTRY_FLAG_FIELD\t\t0x08\n> +\n> +/**\n> + * struct v4l2_h264_dpb_entry - H264 decoded picture buffer entry\n> + *\n> + * @reference_ts: timestamp of the V4L2 capture buffer to use as reference.\n> + * The timestamp refers to the timestamp field in struct v4l2_buffer.\n> + * Use v4l2_timeval_to_ns() to convert the struct timeval to a __u64.\n> + * @pic_num: matches PicNum variable assigned during the reference\n> + * picture lists construction process.\n> + * @frame_num: frame identifier which matches frame_num syntax element.\n> + * @fields: indicates how the DPB entry is referenced. Valid values are\n> + * V4L2_H264_{}_REF.\n> + * @reserved: padding field. Should be zeroed by applications.\n> + * @top_field_order_cnt: matches TopFieldOrderCnt picture value.\n> + * @bottom_field_order_cnt: matches BottomFieldOrderCnt picture value.\n> + * Note that picture field is indicated by v4l2_buffer.field.\n> + * @flags: see V4L2_H264_DPB_ENTRY_FLAG_{}.\n> + */\n> +struct v4l2_h264_dpb_entry {\n> +\t__u64 reference_ts;\n> +\t__u32 pic_num;\n> +\t__u16 frame_num;\n> +\t__u8 fields;\n> +\t__u8 reserved[5];\n> +\t__s32 top_field_order_cnt;\n> +\t__s32 bottom_field_order_cnt;\n> +\t__u32 flags;\n> +};\n> +\n> +#define V4L2_H264_DECODE_PARAM_FLAG_IDR_PIC\t\t0x01\n> +#define V4L2_H264_DECODE_PARAM_FLAG_FIELD_PIC\t\t0x02\n> +#define V4L2_H264_DECODE_PARAM_FLAG_BOTTOM_FIELD\t0x04\n> +\n> +#define V4L2_CID_STATELESS_H264_DECODE_PARAMS\t(V4L2_CID_CODEC_STATELESS_BASE + 7)\n> +/**\n> + * struct v4l2_ctrl_h264_decode_params - H264 decoding parameters\n> + *\n> + * @dpb: decoded picture buffer.\n> + * @nal_ref_idc: slice header syntax element.\n> + * @frame_num: slice header syntax element.\n> + * @top_field_order_cnt: matches TopFieldOrderCnt picture value.\n> + * @bottom_field_order_cnt: matches BottomFieldOrderCnt picture value.\n> + * Note that picture field is indicated by v4l2_buffer.field.\n> + * @idr_pic_id: slice header syntax element.\n> + * @pic_order_cnt_lsb: slice header syntax element.\n> + * @delta_pic_order_cnt_bottom: slice header syntax element.\n> + * @delta_pic_order_cnt0: slice header syntax element.\n> + * @delta_pic_order_cnt1: slice header syntax element.\n> + * @dec_ref_pic_marking_bit_size: size in bits of dec_ref_pic_marking()\n> + * syntax element.\n> + * @pic_order_cnt_bit_size: size in bits of pic order count syntax.\n> + * @slice_group_change_cycle: slice header syntax element.\n> + * @reserved: padding field. Should be zeroed by applications.\n> + * @flags: see V4L2_H264_DECODE_PARAM_FLAG_{}.\n> + */\n> +struct v4l2_ctrl_h264_decode_params {\n> +\tstruct v4l2_h264_dpb_entry dpb[V4L2_H264_NUM_DPB_ENTRIES];\n> +\t__u16 nal_ref_idc;\n> +\t__u16 frame_num;\n> +\t__s32 top_field_order_cnt;\n> +\t__s32 bottom_field_order_cnt;\n> +\t__u16 idr_pic_id;\n> +\t__u16 pic_order_cnt_lsb;\n> +\t__s32 delta_pic_order_cnt_bottom;\n> +\t__s32 delta_pic_order_cnt0;\n> +\t__s32 delta_pic_order_cnt1;\n> +\t__u32 dec_ref_pic_marking_bit_size;\n> +\t__u32 pic_order_cnt_bit_size;\n> +\t__u32 slice_group_change_cycle;\n> +\n> +\t__u32 reserved;\n> +\t__u32 flags;\n> +};\n> +\n> +\n> +/* Stateless FWHT control, used by the vicodec driver */\n> +\n> +/* Current FWHT version */\n> +#define V4L2_FWHT_VERSION\t\t\t3\n> +\n> +/* Set if this is an interlaced format */\n> +#define V4L2_FWHT_FL_IS_INTERLACED\t\tBIT(0)\n> +/* Set if this is a bottom-first (NTSC) interlaced format */\n> +#define V4L2_FWHT_FL_IS_BOTTOM_FIRST\t\tBIT(1)\n> +/* Set if each 'frame' contains just one field */\n> +#define V4L2_FWHT_FL_IS_ALTERNATE\t\tBIT(2)\n> +/*\n> + * If V4L2_FWHT_FL_IS_ALTERNATE was set, then this is set if this\n> + * 'frame' is the bottom field, else it is the top field.\n> + */\n> +#define V4L2_FWHT_FL_IS_BOTTOM_FIELD\t\tBIT(3)\n> +/* Set if the Y' plane is uncompressed */\n> +#define V4L2_FWHT_FL_LUMA_IS_UNCOMPRESSED\tBIT(4)\n> +/* Set if the Cb plane is uncompressed */\n> +#define V4L2_FWHT_FL_CB_IS_UNCOMPRESSED\t\tBIT(5)\n> +/* Set if the Cr plane is uncompressed */\n> +#define V4L2_FWHT_FL_CR_IS_UNCOMPRESSED\t\tBIT(6)\n> +/* Set if the chroma plane is full height, if cleared it is half height */\n> +#define V4L2_FWHT_FL_CHROMA_FULL_HEIGHT\t\tBIT(7)\n> +/* Set if the chroma plane is full width, if cleared it is half width */\n> +#define V4L2_FWHT_FL_CHROMA_FULL_WIDTH\t\tBIT(8)\n> +/* Set if the alpha plane is uncompressed */\n> +#define V4L2_FWHT_FL_ALPHA_IS_UNCOMPRESSED\tBIT(9)\n> +/* Set if this is an I Frame */\n> +#define V4L2_FWHT_FL_I_FRAME\t\t\tBIT(10)\n> +\n> +/* A 4-values flag - the number of components - 1 */\n> +#define V4L2_FWHT_FL_COMPONENTS_NUM_MSK\t\tGENMASK(18, 16)\n> +#define V4L2_FWHT_FL_COMPONENTS_NUM_OFFSET\t16\n> +\n> +/* A 4-values flag - the pixel encoding type */\n> +#define V4L2_FWHT_FL_PIXENC_MSK\t\t\tGENMASK(20, 19)\n> +#define V4L2_FWHT_FL_PIXENC_OFFSET\t\t19\n> +#define V4L2_FWHT_FL_PIXENC_YUV\t\t\t(1 << V4L2_FWHT_FL_PIXENC_OFFSET)\n> +#define V4L2_FWHT_FL_PIXENC_RGB\t\t\t(2 << V4L2_FWHT_FL_PIXENC_OFFSET)\n> +#define V4L2_FWHT_FL_PIXENC_HSV\t\t\t(3 << V4L2_FWHT_FL_PIXENC_OFFSET)\n> +\n> +#define V4L2_CID_STATELESS_FWHT_PARAMS\t\t(V4L2_CID_CODEC_STATELESS_BASE + 100)\n> +/**\n> + * struct v4l2_ctrl_fwht_params - FWHT parameters\n> + *\n> + * @backward_ref_ts: timestamp of the V4L2 capture buffer to use as reference.\n> + * The timestamp refers to the timestamp field in struct v4l2_buffer.\n> + * Use v4l2_timeval_to_ns() to convert the struct timeval to a __u64.\n> + * @version: must be V4L2_FWHT_VERSION.\n> + * @width: width of frame.\n> + * @height: height of frame.\n> + * @flags: FWHT flags (see V4L2_FWHT_FL_*).\n> + * @colorspace: the colorspace (enum v4l2_colorspace).\n> + * @xfer_func: the transfer function (enum v4l2_xfer_func).\n> + * @ycbcr_enc: the Y'CbCr encoding (enum v4l2_ycbcr_encoding).\n> + * @quantization: the quantization (enum v4l2_quantization).\n> + */\n> +struct v4l2_ctrl_fwht_params {\n> +\t__u64 backward_ref_ts;\n> +\t__u32 version;\n> +\t__u32 width;\n> +\t__u32 height;\n> +\t__u32 flags;\n> +\t__u32 colorspace;\n> +\t__u32 xfer_func;\n> +\t__u32 ycbcr_enc;\n> +\t__u32 quantization;\n> +};\n> +\n> +/* MPEG-compression definitions kept for backwards compatibility */\n> +#define V4L2_CTRL_CLASS_MPEG V4L2_CTRL_CLASS_CODEC\n> +#define V4L2_CID_MPEG_CLASS V4L2_CID_CODEC_CLASS\n> +#define V4L2_CID_MPEG_BASE V4L2_CID_CODEC_BASE\n> +#define V4L2_CID_MPEG_CX2341X_BASE V4L2_CID_CODEC_CX2341X_BASE\n> +#define V4L2_CID_MPEG_MFC51_BASE V4L2_CID_CODEC_MFC51_BASE\n> +\n> #endif\n> diff --git a/include/linux/v4l2-mediabus.h b/include/linux/v4l2-mediabus.h\n> index 0fb5bfbec871..846dadfbfc64 100644\n> --- a/include/linux/v4l2-mediabus.h\n> +++ b/include/linux/v4l2-mediabus.h\n> @@ -16,6 +16,8 @@\n> #include \n> #include \n> \n> +#define V4L2_MBUS_FRAMEFMT_SET_CSC\t0x0001\n> +\n> /**\n> * struct v4l2_mbus_framefmt - frame format on the media bus\n> * @width:\timage width\n> @@ -24,8 +26,11 @@\n> * @field:\tused interlacing type (from enum v4l2_field)\n> * @colorspace:\tcolorspace of the data (from enum v4l2_colorspace)\n> * @ycbcr_enc:\tYCbCr encoding of the data (from enum v4l2_ycbcr_encoding)\n> + * @hsv_enc:\tHSV encoding of the data (from enum v4l2_hsv_encoding)\n> * @quantization: quantization of the data (from enum v4l2_quantization)\n> * @xfer_func: transfer function of the data (from enum v4l2_xfer_func)\n> + * @flags:\tflags (V4L2_MBUS_FRAMEFMT_*)\n> + * @reserved: reserved bytes that can be later used\n> */\n> struct v4l2_mbus_framefmt {\n> \t__u32\t\t\twidth;\n> @@ -33,10 +38,16 @@ struct v4l2_mbus_framefmt {\n> \t__u32\t\t\tcode;\n> \t__u32\t\t\tfield;\n> \t__u32\t\t\tcolorspace;\n> -\t__u16\t\t\tycbcr_enc;\n> +\tunion {\n> +\t\t/* enum v4l2_ycbcr_encoding */\n> +\t\t__u16\t\t\tycbcr_enc;\n> +\t\t/* enum v4l2_hsv_encoding */\n> +\t\t__u16\t\t\thsv_enc;\n> +\t};\n> \t__u16\t\t\tquantization;\n> \t__u16\t\t\txfer_func;\n> -\t__u16\t\t\treserved[11];\n> +\t__u16\t\t\tflags;\n> +\t__u16\t\t\treserved[10];\n> };\n> \n> /*\n> diff --git a/include/linux/v4l2-subdev.h b/include/linux/v4l2-subdev.h\n> index 03970ce30741..a38454d9e0f5 100644\n> --- a/include/linux/v4l2-subdev.h\n> +++ b/include/linux/v4l2-subdev.h\n> @@ -65,19 +65,27 @@ struct v4l2_subdev_crop {\n> \t__u32 reserved[8];\n> };\n> \n> +#define V4L2_SUBDEV_MBUS_CODE_CSC_COLORSPACE\t0x00000001\n> +#define V4L2_SUBDEV_MBUS_CODE_CSC_XFER_FUNC\t0x00000002\n> +#define V4L2_SUBDEV_MBUS_CODE_CSC_YCBCR_ENC\t0x00000004\n> +#define V4L2_SUBDEV_MBUS_CODE_CSC_HSV_ENC\tV4L2_SUBDEV_MBUS_CODE_CSC_YCBCR_ENC\n> +#define V4L2_SUBDEV_MBUS_CODE_CSC_QUANTIZATION\t0x00000008\n> +\n> /**\n> * struct v4l2_subdev_mbus_code_enum - Media bus format enumeration\n> * @pad: pad number, as reported by the media API\n> * @index: format index during enumeration\n> * @code: format code (MEDIA_BUS_FMT_ definitions)\n> * @which: format type (from enum v4l2_subdev_format_whence)\n> + * @flags: flags set by the driver, (V4L2_SUBDEV_MBUS_CODE_*)\n> */\n> struct v4l2_subdev_mbus_code_enum {\n> \t__u32 pad;\n> \t__u32 index;\n> \t__u32 code;\n> \t__u32 which;\n> -\t__u32 reserved[8];\n> +\t__u32 flags;\n> +\t__u32 reserved[7];\n> };\n> \n> /**\n> @@ -155,9 +163,25 @@ struct v4l2_subdev_selection {\n> \t__u32 reserved[8];\n> };\n> \n> +/**\n> + * struct v4l2_subdev_capability - subdev capabilities\n> + * @version: the driver versioning number\n> + * @capabilities: the subdev capabilities, see V4L2_SUBDEV_CAP_*\n> + * @reserved: for future use, set to zero for now\n> + */\n> +struct v4l2_subdev_capability {\n> +\t__u32 version;\n> +\t__u32 capabilities;\n> +\t__u32 reserved[14];\n> +};\n> +\n> +/* The v4l2 sub-device video device node is registered in read-only mode. */\n> +#define V4L2_SUBDEV_CAP_RO_SUBDEV\t\t0x00000001\n> +\n> /* Backwards compatibility define --- to be removed */\n> #define v4l2_subdev_edid v4l2_edid\n> \n> +#define VIDIOC_SUBDEV_QUERYCAP\t\t\t_IOR('V', 0, struct v4l2_subdev_capability)\n> #define VIDIOC_SUBDEV_G_FMT\t\t\t_IOWR('V', 4, struct v4l2_subdev_format)\n> #define VIDIOC_SUBDEV_S_FMT\t\t\t_IOWR('V', 5, struct v4l2_subdev_format)\n> #define VIDIOC_SUBDEV_G_FRAME_INTERVAL\t\t_IOWR('V', 21, struct v4l2_subdev_frame_interval)\n> diff --git a/include/linux/videodev2.h b/include/linux/videodev2.h\n> index c70d766187a0..f54075406e47 100644\n> --- a/include/linux/videodev2.h\n> +++ b/include/linux/videodev2.h\n> @@ -169,6 +169,8 @@ enum v4l2_buf_type {\n> \t || (type) == V4L2_BUF_TYPE_SDR_OUTPUT\t\t\t\\\n> \t || (type) == V4L2_BUF_TYPE_META_OUTPUT)\n> \n> +#define V4L2_TYPE_IS_CAPTURE(type) (!V4L2_TYPE_IS_OUTPUT(type))\n> +\n> enum v4l2_tuner_type {\n> \tV4L2_TUNER_RADIO\t = 1,\n> \tV4L2_TUNER_ANALOG_TV\t = 2,\n> @@ -217,9 +219,7 @@ enum v4l2_colorspace {\n> \tV4L2_COLORSPACE_470_SYSTEM_M = 5,\n> \n> \t/*\n> -\t * EBU Tech 3213 PAL/SECAM colorspace. This only makes sense when\n> -\t * dealing with really old PAL/SECAM recordings. Superseded by\n> -\t * SMPTE 170M.\n> +\t * EBU Tech 3213 PAL/SECAM colorspace.\n> \t */\n> \tV4L2_COLORSPACE_470_SYSTEM_BG = 6,\n> \n> @@ -367,9 +367,9 @@ enum v4l2_hsv_encoding {\n> \n> enum v4l2_quantization {\n> \t/*\n> -\t * The default for R'G'B' quantization is always full range, except\n> -\t * for the BT2020 colorspace. For Y'CbCr the quantization is always\n> -\t * limited range, except for COLORSPACE_JPEG: this is full range.\n> +\t * The default for R'G'B' quantization is always full range.\n> +\t * For Y'CbCr the quantization is always limited range, except\n> +\t * for COLORSPACE_JPEG: this is full range.\n> \t */\n> \tV4L2_QUANTIZATION_DEFAULT = 0,\n> \tV4L2_QUANTIZATION_FULL_RANGE = 1,\n> @@ -378,14 +378,13 @@ enum v4l2_quantization {\n> \n> /*\n> * Determine how QUANTIZATION_DEFAULT should map to a proper quantization.\n> - * This depends on whether the image is RGB or not, the colorspace and the\n> - * Y'CbCr encoding.\n> + * This depends on whether the image is RGB or not, the colorspace.\n> + * The Y'CbCr encoding is not used anymore, but is still there for backwards\n> + * compatibility.\n> */\n> #define V4L2_MAP_QUANTIZATION_DEFAULT(is_rgb_or_hsv, colsp, ycbcr_enc) \\\n> -\t(((is_rgb_or_hsv) && (colsp) == V4L2_COLORSPACE_BT2020) ? \\\n> -\t V4L2_QUANTIZATION_LIM_RANGE : \\\n> -\t (((is_rgb_or_hsv) || (colsp) == V4L2_COLORSPACE_JPEG) ? \\\n> -\t V4L2_QUANTIZATION_FULL_RANGE : V4L2_QUANTIZATION_LIM_RANGE))\n> +\t(((is_rgb_or_hsv) || (colsp) == V4L2_COLORSPACE_JPEG) ? \\\n> +\t V4L2_QUANTIZATION_FULL_RANGE : V4L2_QUANTIZATION_LIM_RANGE)\n> \n> /*\n> * Deprecated names for opRGB colorspace (IEC 61966-2-5)\n> @@ -416,6 +415,11 @@ struct v4l2_fract {\n> \t__u32 denominator;\n> };\n> \n> +struct v4l2_area {\n> +\t__u32 width;\n> +\t__u32 height;\n> +};\n> +\n> /**\n> * struct v4l2_capability - Describes V4L2 device caps returned by VIDIOC_QUERYCAP\n> *\n> @@ -505,7 +509,7 @@ struct v4l2_pix_format {\n> \n> /* Pixel format FOURCC depth Description */\n> \n> -/* RGB formats */\n> +/* RGB formats (1 or 2 bytes per pixel) */\n> #define V4L2_PIX_FMT_RGB332 v4l2_fourcc('R', 'G', 'B', '1') /* 8 RGB-3-3-2 */\n> #define V4L2_PIX_FMT_RGB444 v4l2_fourcc('R', '4', '4', '4') /* 16 xxxxrrrr ggggbbbb */\n> #define V4L2_PIX_FMT_ARGB444 v4l2_fourcc('A', 'R', '1', '2') /* 16 aaaarrrr ggggbbbb */\n> @@ -514,12 +518,6 @@ struct v4l2_pix_format {\n> #define V4L2_PIX_FMT_RGBX444 v4l2_fourcc('R', 'X', '1', '2') /* 16 rrrrgggg bbbbxxxx */\n> #define V4L2_PIX_FMT_ABGR444 v4l2_fourcc('A', 'B', '1', '2') /* 16 aaaabbbb ggggrrrr */\n> #define V4L2_PIX_FMT_XBGR444 v4l2_fourcc('X', 'B', '1', '2') /* 16 xxxxbbbb ggggrrrr */\n> -\n> -/*\n> - * Originally this had 'BA12' as fourcc, but this clashed with the older\n> - * V4L2_PIX_FMT_SGRBG12 which inexplicably used that same fourcc.\n> - * So use 'GA12' instead for V4L2_PIX_FMT_BGRA444.\n> - */\n> #define V4L2_PIX_FMT_BGRA444 v4l2_fourcc('G', 'A', '1', '2') /* 16 bbbbgggg rrrraaaa */\n> #define V4L2_PIX_FMT_BGRX444 v4l2_fourcc('B', 'X', '1', '2') /* 16 bbbbgggg rrrrxxxx */\n> #define V4L2_PIX_FMT_RGB555 v4l2_fourcc('R', 'G', 'B', 'O') /* 16 RGB-5-5-5 */\n> @@ -536,6 +534,8 @@ struct v4l2_pix_format {\n> #define V4L2_PIX_FMT_ARGB555X v4l2_fourcc_be('A', 'R', '1', '5') /* 16 ARGB-5-5-5 BE */\n> #define V4L2_PIX_FMT_XRGB555X v4l2_fourcc_be('X', 'R', '1', '5') /* 16 XRGB-5-5-5 BE */\n> #define V4L2_PIX_FMT_RGB565X v4l2_fourcc('R', 'G', 'B', 'R') /* 16 RGB-5-6-5 BE */\n> +\n> +/* RGB formats (3 or 4 bytes per pixel) */\n> #define V4L2_PIX_FMT_BGR666 v4l2_fourcc('B', 'G', 'R', 'H') /* 18 BGR-6-6-6\t */\n> #define V4L2_PIX_FMT_BGR24 v4l2_fourcc('B', 'G', 'R', '3') /* 24 BGR-8-8-8 */\n> #define V4L2_PIX_FMT_RGB24 v4l2_fourcc('R', 'G', 'B', '3') /* 24 RGB-8-8-8 */\n> @@ -556,6 +556,7 @@ struct v4l2_pix_format {\n> #define V4L2_PIX_FMT_Y6 v4l2_fourcc('Y', '0', '6', ' ') /* 6 Greyscale */\n> #define V4L2_PIX_FMT_Y10 v4l2_fourcc('Y', '1', '0', ' ') /* 10 Greyscale */\n> #define V4L2_PIX_FMT_Y12 v4l2_fourcc('Y', '1', '2', ' ') /* 12 Greyscale */\n> +#define V4L2_PIX_FMT_Y14 v4l2_fourcc('Y', '1', '4', ' ') /* 14 Greyscale */\n> #define V4L2_PIX_FMT_Y16 v4l2_fourcc('Y', '1', '6', ' ') /* 16 Greyscale */\n> #define V4L2_PIX_FMT_Y16_BE v4l2_fourcc_be('Y', '1', '6', ' ') /* 16 Greyscale BE */\n> \n> @@ -584,8 +585,6 @@ struct v4l2_pix_format {\n> #define V4L2_PIX_FMT_XYUV32 v4l2_fourcc('X', 'Y', 'U', 'V') /* 32 XYUV-8-8-8-8 */\n> #define V4L2_PIX_FMT_VUYA32 v4l2_fourcc('V', 'U', 'Y', 'A') /* 32 VUYA-8-8-8-8 */\n> #define V4L2_PIX_FMT_VUYX32 v4l2_fourcc('V', 'U', 'Y', 'X') /* 32 VUYX-8-8-8-8 */\n> -#define V4L2_PIX_FMT_HI240 v4l2_fourcc('H', 'I', '2', '4') /* 8 8-bit color */\n> -#define V4L2_PIX_FMT_HM12 v4l2_fourcc('H', 'M', '1', '2') /* 8 YUV 4:2:0 16x16 macroblocks */\n> #define V4L2_PIX_FMT_M420 v4l2_fourcc('M', '4', '2', '0') /* 12 YUV 4:2:0 2 lines y, 1 line uv interleaved */\n> \n> /* two planes -- one Y, one Cr + Cb interleaved */\n> @@ -595,6 +594,7 @@ struct v4l2_pix_format {\n> #define V4L2_PIX_FMT_NV61 v4l2_fourcc('N', 'V', '6', '1') /* 16 Y/CrCb 4:2:2 */\n> #define V4L2_PIX_FMT_NV24 v4l2_fourcc('N', 'V', '2', '4') /* 24 Y/CbCr 4:4:4 */\n> #define V4L2_PIX_FMT_NV42 v4l2_fourcc('N', 'V', '4', '2') /* 24 Y/CrCb 4:4:4 */\n> +#define V4L2_PIX_FMT_HM12 v4l2_fourcc('H', 'M', '1', '2') /* 8 YUV 4:2:0 16x16 macroblocks */\n> \n> /* two non contiguous planes - one Y, one Cr + Cb interleaved */\n> #define V4L2_PIX_FMT_NV12M v4l2_fourcc('N', 'M', '1', '2') /* 12 Y/CbCr 4:2:0 */\n> @@ -653,6 +653,10 @@ struct v4l2_pix_format {\n> #define V4L2_PIX_FMT_SGBRG12P v4l2_fourcc('p', 'G', 'C', 'C')\n> #define V4L2_PIX_FMT_SGRBG12P v4l2_fourcc('p', 'g', 'C', 'C')\n> #define V4L2_PIX_FMT_SRGGB12P v4l2_fourcc('p', 'R', 'C', 'C')\n> +#define V4L2_PIX_FMT_SBGGR14 v4l2_fourcc('B', 'G', '1', '4') /* 14 BGBG.. GRGR.. */\n> +#define V4L2_PIX_FMT_SGBRG14 v4l2_fourcc('G', 'B', '1', '4') /* 14 GBGB.. RGRG.. */\n> +#define V4L2_PIX_FMT_SGRBG14 v4l2_fourcc('G', 'R', '1', '4') /* 14 GRGR.. BGBG.. */\n> +#define V4L2_PIX_FMT_SRGGB14 v4l2_fourcc('R', 'G', '1', '4') /* 14 RGRG.. GBGB.. */\n> \t/* 14bit raw bayer packed, 7 bytes for every 4 pixels */\n> #define V4L2_PIX_FMT_SBGGR14P v4l2_fourcc('p', 'B', 'E', 'E')\n> #define V4L2_PIX_FMT_SGBRG14P v4l2_fourcc('p', 'G', 'E', 'E')\n> @@ -688,6 +692,7 @@ struct v4l2_pix_format {\n> #define V4L2_PIX_FMT_HEVC v4l2_fourcc('H', 'E', 'V', 'C') /* HEVC aka H.265 */\n> #define V4L2_PIX_FMT_FWHT v4l2_fourcc('F', 'W', 'H', 'T') /* Fast Walsh Hadamard Transform (vicodec) */\n> #define V4L2_PIX_FMT_FWHT_STATELESS v4l2_fourcc('S', 'F', 'W', 'H') /* Stateless FWHT (vicodec) */\n> +#define V4L2_PIX_FMT_H264_SLICE v4l2_fourcc('S', '2', '6', '4') /* H264 parsed slices */\n> \n> /* Vendor-specific formats */\n> #define V4L2_PIX_FMT_CPIA1 v4l2_fourcc('C', 'P', 'I', 'A') /* cpia1 YUV */\n> @@ -723,6 +728,7 @@ struct v4l2_pix_format {\n> #define V4L2_PIX_FMT_INZI v4l2_fourcc('I', 'N', 'Z', 'I') /* Intel Planar Greyscale 10-bit and Depth 16-bit */\n> #define V4L2_PIX_FMT_SUNXI_TILED_NV12 v4l2_fourcc('S', 'T', '1', '2') /* Sunxi Tiled NV12 Format */\n> #define V4L2_PIX_FMT_CNF4 v4l2_fourcc('C', 'N', 'F', '4') /* Intel 4-bit packed depth confidence information */\n> +#define V4L2_PIX_FMT_HI240 v4l2_fourcc('H', 'I', '2', '4') /* BTTV 8-bit dithered RGB */\n> \n> /* 10bit raw bayer packed, 32 bytes for every 25 pixels, last LSB 6 bits unused */\n> #define V4L2_PIX_FMT_IPU3_SBGGR10\tv4l2_fourcc('i', 'p', '3', 'b') /* IPU3 packed 10-bit BGGR bayer */\n> @@ -751,18 +757,20 @@ struct v4l2_pix_format {\n> #define V4L2_META_FMT_VSP1_HGT v4l2_fourcc('V', 'S', 'P', 'T') /* R-Car VSP1 2-D Histogram */\n> #define V4L2_META_FMT_UVC v4l2_fourcc('U', 'V', 'C', 'H') /* UVC Payload Header metadata */\n> #define V4L2_META_FMT_D4XX v4l2_fourcc('D', '4', 'X', 'X') /* D4XX Payload Header metadata */\n> +#define V4L2_META_FMT_VIVID\t v4l2_fourcc('V', 'I', 'V', 'D') /* Vivid Metadata */\n> #define V4L2_META_FMT_SENSOR_DATA v4l2_fourcc('S', 'E', 'N', 'S') /* Sensor Ancillary metadata */\n> #define V4L2_META_FMT_BCM2835_ISP_STATS v4l2_fourcc('B', 'S', 'T', 'A') /* BCM2835 ISP image statistics output */\n> \n> /* Vendor specific - used for RK_ISP1 camera sub-system */\n> -#define V4L2_META_FMT_RK_ISP1_PARAMS\tv4l2_fourcc('R', 'K', '1', 'P') /* Rockchip ISP1 params */\n> -#define V4L2_META_FMT_RK_ISP1_STAT_3A\tv4l2_fourcc('R', 'K', '1', 'S') /* Rockchip ISP1 3A statistics */\n> +#define V4L2_META_FMT_RK_ISP1_PARAMS\tv4l2_fourcc('R', 'K', '1', 'P') /* Rockchip ISP1 3A Parameters */\n> +#define V4L2_META_FMT_RK_ISP1_STAT_3A\tv4l2_fourcc('R', 'K', '1', 'S') /* Rockchip ISP1 3A Statistics */\n> \n> /* priv field value to indicates that subsequent fields are valid. */\n> #define V4L2_PIX_FMT_PRIV_MAGIC\t\t0xfeedcafe\n> \n> /* Flags */\n> #define V4L2_PIX_FMT_FLAG_PREMUL_ALPHA\t0x00000001\n> +#define V4L2_PIX_FMT_FLAG_SET_CSC\t0x00000002\n> \n> /*\n> *\tF O R M A T E N U M E R A T I O N\n> @@ -781,6 +789,12 @@ struct v4l2_fmtdesc {\n> #define V4L2_FMT_FLAG_EMULATED\t\t\t0x0002\n> #define V4L2_FMT_FLAG_CONTINUOUS_BYTESTREAM\t0x0004\n> #define V4L2_FMT_FLAG_DYN_RESOLUTION\t\t0x0008\n> +#define V4L2_FMT_FLAG_ENC_CAP_FRAME_INTERVAL\t0x0010\n> +#define V4L2_FMT_FLAG_CSC_COLORSPACE\t\t0x0020\n> +#define V4L2_FMT_FLAG_CSC_XFER_FUNC\t\t0x0040\n> +#define V4L2_FMT_FLAG_CSC_YCBCR_ENC\t\t0x0080\n> +#define V4L2_FMT_FLAG_CSC_HSV_ENC\t\tV4L2_FMT_FLAG_CSC_YCBCR_ENC\n> +#define V4L2_FMT_FLAG_CSC_QUANTIZATION\t\t0x0100\n> \n> \t/* Frame Size and frame rate enumeration */\n> /*\n> @@ -909,6 +923,8 @@ struct v4l2_jpegcompression {\n> /*\n> *\tM E M O R Y - M A P P I N G B U F F E R S\n> */\n> +\n> +\n> struct v4l2_requestbuffers {\n> \t__u32\t\t\tcount;\n> \t__u32\t\t\ttype;\t\t/* enum v4l2_buf_type */\n> @@ -918,11 +934,13 @@ struct v4l2_requestbuffers {\n> };\n> \n> /* capabilities for struct v4l2_requestbuffers and v4l2_create_buffers */\n> -#define V4L2_BUF_CAP_SUPPORTS_MMAP\t(1 << 0)\n> -#define V4L2_BUF_CAP_SUPPORTS_USERPTR\t(1 << 1)\n> -#define V4L2_BUF_CAP_SUPPORTS_DMABUF\t(1 << 2)\n> -#define V4L2_BUF_CAP_SUPPORTS_REQUESTS\t(1 << 3)\n> -#define V4L2_BUF_CAP_SUPPORTS_ORPHANED_BUFS (1 << 4)\n> +#define V4L2_BUF_CAP_SUPPORTS_MMAP\t\t\t(1 << 0)\n> +#define V4L2_BUF_CAP_SUPPORTS_USERPTR\t\t\t(1 << 1)\n> +#define V4L2_BUF_CAP_SUPPORTS_DMABUF\t\t\t(1 << 2)\n> +#define V4L2_BUF_CAP_SUPPORTS_REQUESTS\t\t\t(1 << 3)\n> +#define V4L2_BUF_CAP_SUPPORTS_ORPHANED_BUFS\t\t(1 << 4)\n> +#define V4L2_BUF_CAP_SUPPORTS_M2M_HOLD_CAPTURE_BUF\t(1 << 5)\n> +#define V4L2_BUF_CAP_SUPPORTS_MMAP_CACHE_HINTS\t\t(1 << 6)\n> \n> /**\n> * struct v4l2_plane - plane info for multi-planar buffers\n> @@ -1044,6 +1062,8 @@ static __inline__ __u64 v4l2_timeval_to_ns(const struct timeval *tv)\n> #define V4L2_BUF_FLAG_IN_REQUEST\t\t0x00000080\n> /* timecode field is valid */\n> #define V4L2_BUF_FLAG_TIMECODE\t\t\t0x00000100\n> +/* Don't return the capture buffer until OUTPUT timestamp changes */\n> +#define V4L2_BUF_FLAG_M2M_HOLD_CAPTURE_BUF\t0x00000200\n> /* Buffer is prepared for queuing */\n> #define V4L2_BUF_FLAG_PREPARED\t\t\t0x00000400\n> /* Cache handling flags */\n> @@ -1211,6 +1231,10 @@ struct v4l2_selection {\n> \n> typedef __u64 v4l2_std_id;\n> \n> +/*\n> + * Attention: Keep the V4L2_STD_* bit definitions in sync with\n> + * include/dt-bindings/display/sdtv-standards.h SDTV_STD_* bit definitions.\n> + */\n> /* one bit for each */\n> #define V4L2_STD_PAL_B ((v4l2_std_id)0x00000001)\n> #define V4L2_STD_PAL_B1 ((v4l2_std_id)0x00000002)\n> @@ -1678,6 +1702,14 @@ struct v4l2_ext_control {\n> \t\t__u8 *p_u8;\n> \t\t__u16 *p_u16;\n> \t\t__u32 *p_u32;\n> +\t\tstruct v4l2_area *p_area;\n> +\t\tstruct v4l2_ctrl_h264_sps *p_h264_sps;\n> +\t\tstruct v4l2_ctrl_h264_pps *p_h264_pps;\n> +\t\tstruct v4l2_ctrl_h264_scaling_matrix *p_h264_scaling_matrix;\n> +\t\tstruct v4l2_ctrl_h264_pred_weights *p_h264_pred_weights;\n> +\t\tstruct v4l2_ctrl_h264_slice_params *p_h264_slice_params;\n> +\t\tstruct v4l2_ctrl_h264_decode_params *p_h264_decode_params;\n> +\t\tstruct v4l2_ctrl_fwht_params *p_fwht_params;\n> \t\tvoid *ptr;\n> \t};\n> } __attribute__ ((packed));\n> @@ -1719,6 +1751,16 @@ enum v4l2_ctrl_type {\n> \tV4L2_CTRL_TYPE_U8\t = 0x0100,\n> \tV4L2_CTRL_TYPE_U16\t = 0x0101,\n> \tV4L2_CTRL_TYPE_U32\t = 0x0102,\n> +\tV4L2_CTRL_TYPE_AREA = 0x0106,\n> +\n> +\tV4L2_CTRL_TYPE_H264_SPS = 0x0200,\n> +\tV4L2_CTRL_TYPE_H264_PPS\t\t = 0x0201,\n> +\tV4L2_CTRL_TYPE_H264_SCALING_MATRIX = 0x0202,\n> +\tV4L2_CTRL_TYPE_H264_SLICE_PARAMS = 0x0203,\n> +\tV4L2_CTRL_TYPE_H264_DECODE_PARAMS = 0x0204,\n> +\tV4L2_CTRL_TYPE_H264_PRED_WEIGHTS = 0x0205,\n> +\n> +\tV4L2_CTRL_TYPE_FWHT_PARAMS\t = 0x0220,\n> };\n> \n> /* Used in the VIDIOC_QUERYCTRL ioctl for querying controls */\n> @@ -1974,6 +2016,7 @@ struct v4l2_encoder_cmd {\n> #define V4L2_DEC_CMD_STOP (1)\n> #define V4L2_DEC_CMD_PAUSE (2)\n> #define V4L2_DEC_CMD_RESUME (3)\n> +#define V4L2_DEC_CMD_FLUSH (4)\n> \n> /* Flags for V4L2_DEC_CMD_START */\n> #define V4L2_DEC_CMD_START_MUTE_AUDIO\t(1 << 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keydata=\n\tmQINBFYE/WYBEACs1PwjMD9rgCu1hlIiUA1AXR4rv2v+BCLUq//vrX5S5bjzxKAryRf0uHat\n\tV/zwz6hiDrZuHUACDB7X8OaQcwhLaVlq6byfoBr25+hbZG7G3+5EUl9cQ7dQEdvNj6V6y/SC\n\trRanWfelwQThCHckbobWiQJfK9n7rYNcPMq9B8e9F020LFH7Kj6YmO95ewJGgLm+idg1Kb3C\n\tpotzWkXc1xmPzcQ1fvQMOfMwdS+4SNw4rY9f07Xb2K99rjMwZVDgESKIzhsDB5GY465sCsiQ\n\tcSAZRxqE49RTBq2+EQsbrQpIc8XiffAB8qexh5/QPzCmR4kJgCGeHIXBtgRj+nIkCJPZvZtf\n\tKr2EAbc6tgg6DkAEHJb+1okosV09+0+TXywYvtEop/WUOWQ+zo+Y/OBd+8Ptgt1pDRyOBzL8\n\tRXa8ZqRf0Mwg75D+dKntZeJHzPRJyrlfQokngAAs4PaFt6UfS+ypMAF37T6CeDArQC41V3ko\n\tlPn1yMsVD0p+6i3DPvA/GPIksDC4owjnzVX9kM8Zc5Cx+XoAN0w5Eqo4t6qEVbuettxx55gq\n\t8K8FieAjgjMSxngo/HST8TpFeqI5nVeq0/lqtBRQKumuIqDg+Bkr4L1V/PSB6XgQcOdhtd36\n\tOe9X9dXB8YSNt7VjOcO7BTmFn/Z8r92mSAfHXpb07YJWJosQOQARAQABtDBLaWVyYW4gQmlu\n\tZ2hhbSA8a2llcmFuLmJpbmdoYW1AaWRlYXNvbmJvYXJkLmNvbT6JAlcEEwEKAEECGwMFCwkI\n\tBwIGFQgJCgsCBBYCAwECHgECF4ACGQEWIQSQLdeYP70o/eNy1HqhHkZyEKRh/QUCXWTtygUJ\n\tCyJXZAAKCRChHkZyEKRh/f8dEACTDsbLN2nioNZMwyLuQRUAFcXNolDX48xcUXsWS2QjxaPm\n\tVsJx8Uy8aYkS85mdPBh0C83OovQR/OVbr8AxhGvYqBs3nQvbWuTl/+4od7DfK2VZOoKBAu5S\n\tQK2FYuUcikDqYcFWJ8DQnubxfE8dvzojHEkXw0sA4igINHDDFX3HJGZtLio+WpEFQtCbfTAG\n\tYZslasz1YZRbwEdSsmO3/kqy5eMnczlm8a21A3fKUo3g8oAZEFM+f4DUNzqIltg31OAB/kZS\n\tenKZQ/SWC8PmLg/ZXBrReYakxXtkP6w3FwMlzOlhGxqhIRNiAJfXJBaRhuUWzPOpEDE9q5YJ\n\tBmqQL2WJm1VSNNVxbXJHpaWMH1sA2R00vmvRrPXGwyIO0IPYeUYQa3gsy6k+En/aMQJd27dp\n\taScf9am9PFICPY5T4ppneeJLif2lyLojo0mcHOV+uyrds9XkLpp14GfTkeKPdPMrLLTsHRfH\n\tfA4I4OBpRrEPiGIZB/0im98MkGY/Mu6qxeZmYLCcgD6qz4idOvfgVOrNh+aA8HzIVR+RMW8H\n\tQGBN9f0E3kfwxuhl3omo6V7lDw8XOdmuWZNC9zPq1UfryVHANYbLGz9KJ4Aw6M+OgBC2JpkD\n\thXMdHUkC+d20dwXrwHTlrJi1YNp6rBc+xald3wsUPOZ5z8moTHUX/uPA/qhGsbkCDQRWBP1m\n\tARAAzijkb+Sau4hAncr1JjOY+KyFEdUNxRy+hqTJdJfaYihxyaj0Ee0P0zEi35CbE6lgU0Uz\n\ttih9fiUbSV3wfsWqg1Ut3/5rTKu7kLFp15kF7eqvV4uezXRD3Qu4yjv/rMmEJbbD4cTvGCYI\n\td6MDC417f7vK3hCbCVIZSp3GXxyC1LU+UQr3fFcOyCwmP9vDUR9JV0BSqHHxRDdpUXE26Dk6\n\tmhf0V1YkspE5St814ETXpEus2urZE5yJIUROlWPIL+hm3NEWfAP06vsQUyLvr/GtbOT79vXl\n\tEn1aulcYyu20dRRxhkQ6iILaURcxIAVJJKPi8dsoMnS8pB0QW12AHWuirPF0g6DiuUfPmrA5\n\tPKe56IGlpkjc8cO51lIxHkWTpCMWigRdPDexKX+Sb+W9QWK/0JjIc4t3KBaiG8O4yRX8ml2R\n\t+rxfAVKM6V769P/hWoRGdgUMgYHFpHGSgEt80OKK5HeUPy2cngDUXzwrqiM5Sz6Od0qw5pCk\n\tNlXqI0W/who0iSVM+8+RmyY0OEkxEcci7rRLsGnM15B5PjLJjh1f2ULYkv8s4SnDwMZ/kE04\n\t/UqCMK/KnX8pwXEMCjz0h6qWNpGwJ0/tYIgQJZh6bqkvBrDogAvuhf60Sogw+mH8b+PBlx1L\n\toeTK396wc+4c3BfiC6pNtUS5GpsPMMjYMk7kVvEAEQEAAYkCPAQYAQoAJgIbDBYhBJAt15g/\n\tvSj943LUeqEeRnIQpGH9BQJdizzIBQkLSKZiAAoJEKEeRnIQpGH9eYgQAJpjaWNgqNOnMTmD\n\tMJggbwjIotypzIXfhHNCeTkG7+qCDlSaBPclcPGYrTwCt0YWPU2TgGgJrVhYT20ierN8LUvj\n\t6qOPTd+Uk7NFzL65qkh80ZKNBFddx1AabQpSVQKbdcLb8OFs85kuSvFdgqZwgxA1vl4TFhNz\n\tPZ79NAmXLackAx3sOVFhk4WQaKRshCB7cSl+RIng5S/ThOBlwNlcKG7j7W2MC06BlTbdEkUp\n\tECzuuRBv8wX4OQl+hbWbB/VKIx5HKlLu1eypen/5lNVzSqMMIYkkZcjV2SWQyUGxSwq0O/sx\n\tS0A8/atCHUXOboUsn54qdxrVDaK+6jIAuo8JiRWctP16KjzUM7MO0/+4zllM8EY57rXrj48j\n\tsbEYX0YQnzaj+jO6kJtoZsIaYR7rMMq9aUAjyiaEZpmP1qF/2sYenDx0Fg2BSlLvLvXM0vU8\n\tpQk3kgDu7kb/7PRYrZvBsr21EIQoIjXbZxDz/o7z95frkP71EaICttZ6k9q5oxxA5WC6sTXc\n\tMW8zs8avFNuA9VpXt0YupJd2ijtZy2mpZNG02fFVXhIn4G807G7+9mhuC4XG5rKlBBUXTvPU\n\tAfYnB4JBDLmLzBFavQfvonSfbitgXwCG3vS+9HEwAjU30Bar1PEOmIbiAoMzuKeRm2LVpmq4\n\tWZw01QYHU/GUV/zHJSFk","Organization":"Ideas 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